JP2010278400A - Low-loss multilayer on-chip inductor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To decrease the skin effect of an inductor to improve the Q value in an on-chip inductor element with a multilayer structure. <P>SOLUTION: The on-chip inductor in an insulating film on a semiconductor substrate, has three or more inductor wiring layers consisting of a single inductor wiring 1 or consisting of a plurality of inductor wirings 1 which are vertically stacked and connected in parallel. Each inductor wiring layer is vertically stacked and connected in series. An effective film thickness in each inductor wiring layer of intermediate layers except inductor wiring layers in a highest layer and a lowest layer, is larger than the effective film thickness in the inductor wiring layers in the highest layer and the lowest layer. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a low loss multilayer on-chip inductor.

  In recent years, various high-speed digital wireless systems such as mobile phones, wireless LANs, Bluetooth, and terrestrial digital TV have been put into practical use. In the case of digital semiconductor integrated circuits that operate at a high speed of GHz or higher, analog technology similar to that for wireless circuits is used. In such a circuit, an on-chip inductor formed on a semiconductor substrate is used as a passive element. This inductor has a shape in which a metal wiring on a semiconductor is spirally wound and has an inductance of about several nH at most, but is a practical inductance value for a circuit operating at a frequency of about GHz.

  In such a high-frequency / wireless circuit, a plurality of inductor elements are usually integrated. However, the size of one inductor element is as large as several tens of μm to several hundreds of μm square, which causes an increase in chip area. As a method for reducing the area of the inductor, a structure as shown in FIG. 10 (Japanese Utility Model Laid-Open No. 60-136156) has been proposed. This structure uses a multilayer wiring structure to form a spiral inductor in a number of wiring layers and connect the inductors in series to increase the overall inductance value. In the figure, inductor wirings of two wiring layers M1 and M2 are connected by vias. In such a system in which multilayer inductor wirings are connected in series, if the number of wiring layers is n, the chip area can be reduced to about 1 / n of a single-layer inductor.

  Further, in the on-chip inductor, the Q value is an important performance in addition to the inductance value. This Q value increases as the series resistance of the inductor is lower. The wiring used for the on-chip inductor has a high resistance because of a thin film, and generally has a low Q value. As a method for solving this, a structure as shown in FIG. 11 (Japanese Patent No. 2986081) has been proposed. Although the figure shows a cross section of the inductor wiring, a substantial wiring resistance can be lowered by connecting the wirings of a plurality of wiring layers in parallel by connecting vias as shown in the figure. In the drawing, vias are arranged over the entire length of the wiring of the three layers M1, M2, and M3, and the wiring layers are connected in parallel. As a result, the series resistance can be reduced to 1/3 when only one layer is used. In such a system in which multilayer inductor wirings are connected in parallel, if the number of wiring layers is n, the series resistance can be reduced to about 1 / n of an inductor having only one layer. Japanese Patent Application Laid-Open No. 2000-114044 also discloses a structure in which the thickness of the wiring layer is increased with a similar structure.

（ｄｉｊはｉ番目の配線とｊ番目の配線の中心間の距離）
で与えられる。 Here, the skin effect may be a problem in an inductor having a multilayer structure. 12 is a volume filament model for explaining the skin effect of the inductor (S. Mei et.al., IEEE Trans. On Very Large Scale Integration Systems, Vol. 12, No. 4, Apr 2004, pp 437-447). Here, it is assumed that the inductor wiring having a length L, a width W, and a height H is a set of N (= Nw × Nh) thin filament wirings having a width w0 and a height H0. The current is calculated on the assumption that the skin effect does not occur inside each filament wiring and the current flows uniformly, and the sum of them is considered to be the current in the entire wiring. As shown in FIG. 13, each filament wiring has a model of a series connection of a resistor Rsi (i is an integer of 1 to N) and an inductor Lsi (i is an integer of 1 to N), and these are all connected in parallel. Here, it is assumed that there is a mutual inductance Mij (i, j is an integer from 1 to N, i ≠ j) depending on the distance between the filament wires. At this time, if the conductivity of the inductor wiring is σ, each parameter is

(Dij is the distance between the center of the i-th wiring and the j-th wiring)
Given in.

  Since all filament wirings have the same width and height, Rsi and Lsi are all the same, but Mij has a distance dependency and therefore differs for each wiring. In the expression (3), since the length L of the wiring is sufficiently large with respect to the width and height in the inductor, the log component of one item is dominant. One item is smaller when the distance dij between the wirings is larger, so that the mutual inductance between the filament wirings separated from each other is small. FIG. 14 is an enlarged view of the cross section of FIG. 12 (in the case of N = 25). Here, the filament wiring of number 1 has only two adjacent filament wirings of number 6 and number 2. There are four filament wires 13, 8, 12, 14, and 18. For this reason, the filament of number 13 has a larger mutual inductance with the surrounding filament wiring than the filament of number 1. For this reason, the apparent series inductance value increases, so that current does not flow easily as the frequency increases. That is, the center portion has a mutual inductance with the surroundings rather than the peripheral portion of the inductor wiring, and current does not flow easily at high frequencies. In other words, the skin effect occurs.

Japanese Utility Model Publication No. 60-136156 Japanese Patent No. 2986081 Japanese Patent Laid-Open No. 2000-114044

S. Mei et. al. , IEEE Trans. on Very Large Scale Integration Systems, Vol. 12, no. 4, Apr 2004, pp 437-447

  An increase in series resistance due to the skin effect is a major problem with inductor wiring that operates at a high frequency of GHz or higher. The skin effect is a phenomenon in which a high-frequency signal flows only near the surface of a conductor, the inside of the conductor does not function as a current path, and a substantial series resistance at a high frequency increases. In the inductor composed of the conventional multilayer inductor wiring connection method, the problem of substantial increase in series resistance has occurred in the intermediate wiring layer, similar to the skin effect.

  FIG. 15 shows an example of an inductor wiring having a structure in which wirings of three wiring layers M1, M2, and M3 overlap each other. Also in this case, like the above description, the number 8 wiring, which is a part of the middle M2 wiring, has a larger mutual inductance with the surrounding wiring than the number 3 and number 13 wiring on the upper side and the lower side. For this reason, the intermediate wiring has a great skin effect and current does not flow easily. FIG. 16 shows the result of calculating the current density of the cross section of the three-layer wiring having a width of 10 μm, a thickness of 1 μm and an interlayer film thickness of 1 μm using the equations (1) to (3). The frequency is 10 GHz. As shown in the figure, the current density of M2 in the intermediate layer is lower than that of M1 and M3. In other words, the influence of the skin effect is great. As described above, the skin effect is a big problem in the multilayer inductor. In the structure described in Patent Document 3, an attempt is made to increase the Q value by making the film thickness of each metal layer approximately twice the skin depth at the operating frequency. It is a response and does not aim to reduce the skin effect as a whole.

  An object of the present invention is to provide an on-chip inductor that reduces the skin effect of the inductor and improves the Q value in an on-chip inductor having a multilayer structure.

  An on-chip inductor according to the present invention is an on-chip inductor in an insulating film on a semiconductor substrate, and is constituted by a single inductor wiring or a structure in which a plurality of inductor wirings are stacked vertically and connected in parallel. There are three or more inductor wiring layers, and each inductor wiring layer is laminated in the vertical direction and connected in series. The effective film thickness of each inductor wiring layer in the intermediate layer excluding the uppermost layer and the lowermost inductor wiring layer is larger than the effective film thickness of the uppermost layer and the lowermost inductor wiring layer. To do. Here, one inductor wiring is configured by winding a wiring in one plane, and the inductor wiring layer is one in which one or a plurality of inductor wirings are stacked one above the other and connected in parallel.

  In the present invention, it is possible to reduce the series resistance of the inductor wiring at a high frequency by reducing the skin effect of the multilayer inductor wiring.

It is a bird's-eye view of the inductor which concerns on Example 1 of this invention. It is a bird's-eye view of the inductor of the comparative example 1 in this invention. It is a bird's-eye view of the inductor of the comparative example 2 in this invention. It is a bird's-eye view of the conventional inductor. It is a figure which shows the inductance value of the inductor of Example 1 of this invention and each comparative example. It is a figure which shows Q value of the inductor of Example 1 of this invention and each comparative example. It is a bird's-eye view of the inductor which concerns on Example 2 of this invention. It is a bird's-eye view of the inductor which concerns on Example 3 of this invention. It is a bird's-eye view of the inductor which concerns on Example 4 of this invention. It is a bird's-eye view of the inductor which connected the conventional multilayer wiring in series. It is sectional drawing of the inductor which connected the conventional multilayer wiring in parallel. It is a figure for demonstrating the skin effect of an inductor. It is the equivalent circuit of FIG. It is an enlarged view of the cross section of FIG. It is a figure for demonstrating the skin effect of the inductor of a multilayer wiring. It is a calculation result of the current density distribution of the wiring cross section of three layers.

  In the on-chip inductor according to the present invention, the film thickness of at least a part of the inductor wiring in the intermediate layer is made larger than the effective film thickness of the uppermost inductor wiring layer and the lowermost inductor wiring layer. The effective film thickness of the entire inductor wiring layer in the intermediate layer can be made larger than the effective film thickness of the uppermost and lowermost inductor wiring layers.

  In addition, the inductor wiring layer of the intermediate layer can be configured by stacking two or more inductor wirings on top and bottom and connecting them in parallel. If the uppermost layer and the lowermost layer are single-layer inductor wirings, the effective film thickness of the entire intermediate inductor wiring layer should be larger than the effective film thickness of the uppermost and lowermost inductor wiring layers. Can do.

  Further, the inductor wiring layer of the intermediate layer can be configured by serially connecting a plurality of upper and lower inductor wiring layers in which two or more inductor wirings are stacked and connected in parallel. In this way, the effective film thickness of the entire intermediate inductor wiring layer can be made larger than the effective film thickness of the uppermost and lowermost inductor wiring layers.

  In addition, the wiring width of at least a part of the inductor wiring in the intermediate layer can be made larger than the wiring width of the uppermost and lowermost inductor wiring layers. In this way, the effective film thickness of the entire inductor wiring layer in the intermediate layer can be made larger than the effective film thickness of the uppermost and lowermost inductor wiring layers.

Example 1
FIG. 1 is a bird's-eye view of an inductor according to Example 1 of the present invention. This is a case where four layers of metal wiring (inductor wiring) of M1 to M4 are used. The on-chip inductor in this embodiment includes metal wirings M1 to M4 provided in an insulating film (not shown) on a semiconductor substrate (not shown). There is one round of inductor wiring in each of the metal wirings M1 to M4. The wiring of the uppermost layer M4 and the lowermost layer M1 is only one layer and is a one-turn inductor wiring 1, but the intermediate layers M2 and M3 are connected by vias 2 to form a single wiring. 1 turns into an inductor wiring layer. That is, a three-turn inductor is formed with four layers of metal wiring.

(Comparative Example 1)
FIG. 2 shows the case where the inductor of Comparative Example 1 (hereinafter, Comparative Example 1) uses four layers of metal wirings M1 to M4 as in FIG. 1, but the uppermost layer M4 and the metal wiring of M3 below it are shown. The two layers are connected by vias to form a single inductor wiring layer, and M2 and M1 below the two layers form a single-layer inductor wiring layer of only one layer.

(Comparative Example 2)
FIG. 3 shows the case where the inductor of Comparative Example 2 (hereinafter, Comparative Example 2) uses four layers of metal wirings M1 to M4 as in FIG. 2, but the lowermost layer M1 and the metal wiring of M2 above it are shown. The two layers are connected by vias to form one inductor wiring layer, and M3 and M4 above it are only one layer to form a single winding inductor wiring layer. That is, according to the present invention, the effective film thickness of the intermediate wiring layer is thicker than the upper and lower wiring layers, and Comparative Example 1 and Comparative Example 2 are wirings having an effective film thickness higher or lower than the intermediate wiring layer. There are layers.

  On the other hand, FIG. 4 shows a conventional multilayer inductor (hereinafter referred to as a conventional type). Here, each wiring layer has only one layer and is a one-turn inductor wiring. In the conventional type, by not using the lowermost M1 wiring, the parasitic capacitance between the substrate and the substrate becomes smaller than that in FIG. 1, but the wiring resistance increases.

  For these four types of inductor wiring structures, the characteristics of the inductor were predicted by electromagnetic field simulation. Here, a copper wiring of a 90 nm node is assumed. HFSS manufactured by Ansoft was used for the electromagnetic field simulation. FIG. 5 shows series inductance values of four types of inductors. As shown in the figure, the series inductance values of the four types of inductors are almost the same, and there is no significant difference due to the winding structure.

  On the other hand, FIG. 6 shows the result of comparing the Q values of the four types of inductors. In this case, the first embodiment of the present invention and the first and second comparative examples have little difference in the Q value at a low frequency, but the higher the frequency, the higher the Q value in the first embodiment. The conventional type has the lowest Q value because of the high original series resistance. This is because, as described above, the effect of the skin effect is larger in the intermediate layer wiring than in the upper and lower wiring layers, and therefore the effect of the skin effect can be reduced in the present invention where the effective wiring film thickness is thick in this part. is there. As described above, in the inductor structure of the present invention, the wiring layer is effectively distributed to the place where the skin effect is large, so that the characteristics of the inductor as a whole are improved.

(Example 2)
FIG. 7 is a bird's-eye view of the inductor according to the second embodiment of the present invention. The on-chip inductor in this embodiment is a case where six layers of metal wirings M1 to M6 provided in an insulating film (not shown) on a semiconductor substrate (not shown) are used. Each of the wirings M1 to M6 has one inductor wiring. The wiring of the uppermost layer M6 and the lowermost layer M1 is only one layer and is an inductor wiring layer of one turn. However, by connecting two layers of the intermediate layers M2 and M3 and M4 and M5 with vias, The wiring layer becomes a one-turn inductor wiring layer. These are connected in series. That is, a four-turn inductor is formed by six wiring layers. In this way, the effective film thickness of each inductor wiring layer in the intermediate layer can be made larger than the effective film thickness of the uppermost layer and the lowermost layer.

(Example 3)
FIG. 8 is a bird's-eye view of the inductor according to the third embodiment of the present invention. The on-chip inductor in this embodiment is a case where three-layer metal wirings M2 to M4 provided in an insulating film (not shown) on a semiconductor substrate (not shown) are used. Each of the wirings M2 to M4 has an inductor wiring of one turn, and each wiring becomes a single-turn inductor wiring layer by only one layer, and forms a three-turn inductor. Here, the metal wiring of the middle M3 is wider than the metal wirings M2 and M4 of the lowermost layer and the uppermost layer. As a result, the series resistance where the skin effect is large is reduced and the characteristics of the entire inductor are improved.

Example 4
FIG. 9 is a bird's-eye view of the inductor according to the fourth embodiment of the present invention. The on-chip inductor in this embodiment is a case where three-layer metal wirings M2 to M4 provided in an insulating film (not shown) on a semiconductor substrate (not shown) are used. Each of the wirings M2 to M4 has an inductor wiring of one turn, and each wiring becomes a single-turn inductor wiring layer by only one layer, and forms a three-turn inductor. Here, the metal wiring of M3 in the middle is thicker than the lowermost and uppermost wiring layers M2 and M4. As a result, the series resistance where the skin effect is large is reduced and the characteristics of the entire inductor are improved.

  Although the present invention has been described with reference to the above embodiments, the present invention is not limited only to the configurations of the above embodiments, and various modifications that can be made by those skilled in the art within the scope of the present invention. Of course, including modifications.

1 Inductor wiring 2 Via 3 Silicon substrate 4 Filament wiring 5 Voltage sources M1 to M6 Metal wiring

Claims (5)

An on-chip inductor in an insulating film on a semiconductor substrate,
It has three or more inductor wiring layers composed of a single inductor wiring, or a plurality of inductor wirings stacked in parallel and connected in parallel, and each inductor wiring layer is stacked vertically and connected in series. Connected,
The effective film thickness of each inductor wiring layer of the intermediate layer excluding the uppermost layer and the lowermost inductor wiring layer is larger than the effective film thickness of the uppermost layer and the lowermost inductor wiring layer. On-chip inductor.   The film thickness of at least a part of the inductor wiring in the intermediate layer is larger than the effective film thickness of the uppermost inductor wiring layer and the lowermost inductor wiring layer. On-chip inductor.   3. The on-chip inductor according to claim 1, wherein the inductor wiring layer of the intermediate layer is formed by stacking two or more inductor wirings vertically and connecting them in parallel. 4.   The intermediate inductor wiring layer is formed by serially connecting a plurality of upper and lower inductor wiring layers in which two or more inductor wirings are stacked vertically and connected in parallel. The on-chip inductor as described in any one of 1-3.   5. The on-state according to claim 1, wherein a wiring width of at least a part of the inductor wiring of the intermediate layer is larger than wiring widths of the uppermost and lowermost inductor wiring layers. Chip inductor.

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