JP2010114283A - Spiral inductor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make compact a shield member 12b which blocks noise from an external circuit without decreasing the Q value of an inductor. <P>SOLUTION: The spiral inductor includes a first conductor wire 11a arranged on a first conductor layer and formed in a spiral shape, a second conductor wire 12a arranged on a second conductor layer and formed in substantially the same spiral shape with the first conductor wire 11a, an insulating film arranged between the first conductor layer and the second conductor layer, a plurality of vias 21 disposed along the length of the second conductor wire 12a and penetrating the insulating film to electrically connect between the first conductor wire 11a and the second conductor wire 12a to each other, and the shield member 12b enclosing a periphery of the second conductor wire 12a. At outermost peripheral parts P2, P4, P6 and P8 of the second conductor wire 12a which are close to the shield member 12b among outermost peripheral parts P1 to P8, inner vias 21b come into contact with the second conductor wire 12a inside the center of the second conductor wire 12a in a wire-width direction. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a spiral inductor in which two or more spiral conductor wires arranged in different conductor layers are connected by vias.

  With advances in technology for manufacturing semiconductor elements by finely processing semiconductors, etc., circuit elements such as various types of transistors, diodes, resistors, and capacitors have been reduced in size. Many challenges remain.

  For example, a spiral inductor made of a spiral metal wiring formed on a metal wiring layer above a semiconductor substrate has been conventionally known. However, since the resistance of the spiral metal wiring is large, the Q value of the spiral inductor decreases. End up.

  Therefore, by arranging two metal wirings having the same spiral shape through an insulating film and connecting the two metal wirings in parallel by a plurality of vias penetrating the insulating film, the area occupied by the spiral inductor is increased. There has been proposed a spiral inductor in which the resistance of a metal wiring is reduced and the Q value is improved (see, for example, Patent Documents 1 and 2).

Furthermore, in order to reduce noise intruding from other circuits or the like, there has been proposed a spiral inductor in which a shield via hole surrounding the periphery of a metal wire having a spiral shape is formed (for example, claim 3 and patent document 2). 4).
Japanese Patent No. 2986081 JP 2006-173145 A

  However, in any of the patent documents, all vias are connected at substantially the center in the line width direction of the metal wiring, and the relationship between the position in the line width direction of the metal wiring that each via contacts and the Q value of the inductor. There is no description which shows.

  In addition, when a shield via hole is disposed around two stacked metal wirings, electromagnetic coupling occurs between the coil portion formed by the two metal wirings and the shield via hole, and this causes the Q of the spiral inductor to be changed. The value will decrease. In order to reduce the size of the inductor, it is desirable that the gap between the metal wiring and the shield member is narrow, but it is also desirable to avoid a decrease in the Q value of the spiral inductor.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a spiral inductor that can reduce the size of a shield member that blocks noise from an external circuit without reducing the Q value of the inductor. It is to be.

  A feature of the present invention is that a first conductor wire having a spiral shape disposed in the first conductor layer and a spiral shape substantially identical to the first conductor wire disposed in the second conductor layer are provided. A second conductor wire, an insulating film disposed between the first conductor layer and the second conductor layer, and arranged along the length direction of the second conductor wire, the insulating film being A spiral inductor comprising a plurality of vias penetrating and electrically connecting the first conductor line and the second conductor line, respectively, and a shield member surrounding the second conductor line In the outermost peripheral part of the second conductor line, at least in the part close to the shield member, the via is formed on the second conductor line inside the center in the line width direction of the second conductor line. It is in contact.

  The inventor of the present invention has found that the position of the first and second conductor lines in the line width direction where the via contacts the first and second conductor lines affects the Q value of the inductor. Therefore, the via is brought into contact with the second conductor line on the inner side of the center of the second conductor line in the line width direction at least in a part close to the shield member in the outermost peripheral part of the second conductor line. Thereby, even if the clearance gap between the 1st and 2nd conductor wire and a shield member is narrowed, the fall of the Q value of an inductor can be controlled.

  According to the spiral inductor of the present invention, it is possible to reduce the size of the shield member that blocks noise from the external circuit without reducing the Q value of the inductor.

  Embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings, the same parts are denoted by the same reference numerals.

  First, with reference to FIG. 1A to FIG. 1C, a description will be given of the conductor lines constituting the spiral inductor according to the embodiment of the present invention and vias connecting different conductor layers.

  A spiral inductor according to an embodiment of the present invention includes two or more spiral conductor wires stacked on an upper side of a semiconductor substrate such as a silicon substrate and an insulating film. And vias that electrically connect each other. In the embodiment of the present invention, as an example, the conductor wires 10, 11a, 11b, 12a, 12b arranged in three conductor layers and the vias that electrically connect the conductor wires 10, 11a, 11b, 12a. A spiral inductor provided with 21, 14a, 14b will be described.

  FIG. 1A shows a base conductor line 10 arranged in a base conductor layer. The base conductor layer is one of a plurality of conductor layers stacked above the semiconductor substrate via an insulating film. The base conductor line 10 is a wiring that connects an inner end portion of a first conductor line 11a, which will be described later, and a pad portion 11b via vias 14a and 14b. The base conductor line 10 is made of, for example, a conductor including a metal added with a metal such as aluminum or copper or a high-concentration impurity.

  FIG. 1B shows the first conductor wire 11a and the pad portion 11b arranged in the first conductor layer. The first conductor layer is a conductor layer disposed above the base conductor layer, that is, in a direction away from the semiconductor substrate, among the plurality of conductor layers stacked above the semiconductor substrate via an insulating film. The first conductor wire 11a has a spiral shape. Here, the “spiral (spiral) shape” indicates a shape of a plane curve created by a point that constantly moves away from or approaches a fixed point around a fixed point. The end portion of the first conductor wire 11a located on the inner side of the spiral shape (hereinafter referred to as “inner end portion”) contacts the via 14b and is electrically connected to one end portion of the base conductor wire 10 via the via 14b. Connected. An end portion (hereinafter referred to as “outer end portion”) of the first conductor wire 11a located outside the spiral shape is extended in a direction away from the above-described fixed point.

The first conductor wire 11a further has a shape approximating a regular octagon. Specifically, “a shape that approximates a regular octagon” means that the outermost periphery of the first conductor wire 11a has eight sides P ₁ , P ₂ , P ₃ , P ₄ , P, each consisting of a line segment having substantially the same length. _{5, P 6,} P 7, has spliced the shape _{P 8,} and the outermost of each round inside, is arranged inside the side _P 1 to P ₈ along the side _P 1 to P ₈ It has a shape in which eight sides are connected.

  The pad portion 11b is an electrode that serves as one input / output terminal of the spiral inductor. The pad portion 11b contacts the via 14a and is electrically connected to the other end of the base conductor line 10 through the via 14a. The material of the first conductor wire 11a and the pad portion 11b is, for example, a conductor including a metal such as aluminum or copper or a semiconductor to which a high concentration impurity is added. The line width of the first conductor wire 11a shown in FIG. 1B is 10 μm, the number of turns is 9, the inner diameter is 103 μm, the film thickness is 0.57 μm, and the distance between the lines is 1 μm.

  FIG.1 (c) shows the 2nd conductor wire 12a and the shield member 12b which are arrange | positioned at the 2nd conductor layer. The second conductor layer is a conductor layer disposed above the first conductor layer among the plurality of conductor layers formed above the semiconductor substrate via an insulating film. The second conductor wire 12a has substantially the same spiral shape as the first conductor wire 11a. Specifically, “substantially the same spiral shape” means that the positions and shapes of both end portions of the second conductor wire 12a are different from those of the first conductor wire 11a, but the second conductor wire 12a excluding both end portions. The line width, the number of turns, the inner diameter, the outer diameter, and the film thickness are the same as those of the first conductor wire 11a.

  The shield member 12b is a ring-shaped conductor surrounding the second conductor wire 12a and has a function of reducing noise entering from other circuits. In particular, in an integrated circuit in which a high-frequency circuit and a logic circuit including a spiral inductor are formed on the same semiconductor substrate, digital noise is prevented from entering the spiral inductor from the logic circuit through the semiconductor substrate. The shield member 12b further has a shape close to a regular square. A distance Dg between a portion adjacent to the shield member 12b in the outermost peripheral portion of the second conductor wire 12a and the shield member 12b is 20 μm.

  The first conductor line 11a and the second conductor line 12a are electrically connected by a plurality of vias 21. FIGS. 1B and 1C show locations where each via 21 contacts the first conductor line 11a and the second conductor line 12a. Each via 21 passes through an insulating film disposed between the first conductor layer and the second conductor layer, and electrically connects the first conductor line 11a and the second conductor line 12a. To do. The plurality of vias 21 are arranged along the length direction of the first conductor line 11a and the second conductor line 12a. The outer diameter of each via 21 shown in FIGS. 1B and 1C is 0.28 μm.

  The plurality of vias 21 are inside the center via 21a that contacts the second conductor line 12a at the approximate center in the line width direction of the second conductor line 12 and the center of the second conductor line 12 in the line width direction. The inner via 21b is in contact with the second conductor wire 12a. The inner via 21b is disposed in a portion adjacent to the shield member 12b in the outermost peripheral portion of the second conductor wire 12a. The central via 21a includes other portions of the second conductor wire 12a, that is, the other portions of the outermost peripheral portion of the second conductor wire 12a excluding the portion adjacent to the shield member 12b and the second conductor wire 12a. It is arranged on the inner periphery.

Specifically, when the second conductor wire 12a has a shape approximating a regular octagon and the shield member 12b has a shape substantially close to a regular square, the shield member 12b of the outermost peripheral portion of the second conductor wire 12a The adjacent portions correspond to the sides P ₂ , P ₄ , P ₆ , and P ₈ in the outermost peripheral portion of the second conductor line 12a. Therefore, the central via 21a and the inner via 21b are alternately arranged for each side of the regular octagon in the outermost peripheral portion of the second conductor wire 12a. Further, four central vias 21a or four inner vias 21b are arranged on each side of the regular octagon, but the present invention is not limited to this.

  FIG. 2 shows the overall configuration of the spiral inductor according to the embodiment of the present invention. The spiral inductor is formed by sequentially superposing the base conductor wire 10, the first conductor wire 11a, the pad portion 11b, the second conductor wire 12a, and the shield member 12b shown in FIGS. 1 (a) to 1 (c). Composed. As described above, the base conductor layer, the first conductor layer, and the second conductor layer are stacked via the insulating film in order from the semiconductor substrate side. Therefore, when the spiral inductor is viewed from the opposite side of the semiconductor substrate, as shown in FIG. 2, the second conductor wire 12a and the shield member 12b appear on the outermost surface, and the first conductor is behind the second conductor wire 12a. The line 11a and the pad part 11b appear, and the base conductor line 10 appears behind the first conductor line 11a and the pad part 11b.

  As described above, the position and shape of both ends of the second conductor wire 12a are different from those of the first conductor wire 11a, but the line width, number of turns, inner diameter, outer diameter of the second conductor wire 12a excluding both ends. Since the first conductor wire 11a has the same thickness as the first conductor wire 11a, only the both ends of the first conductor wire 11a appear in FIG. 2, and the portions other than the both ends of the first conductor wire 11a are the second conductor. It is hidden by the line 12a.

  The inner end of the first conductor line 11a is connected to one end of the base conductor line 10 via the via 14b, and the other end of the base conductor line 10 is connected to the pad part 11b via the via 14a.

3 is a cross-sectional view of the spiral inductor along the AA section of FIG. 2, and FIG. 4 is a cross-sectional view of the spiral inductor along the BB section of FIG. As shown in FIGS. 3 and 4, the spiral inductor is disposed above the semiconductor substrate 1 via the silicon oxide film 2. Specifically, the silicon oxide film 2 is disposed on the semiconductor substrate 1, the first conductor line 11a is disposed on the silicon oxide film 2, and the insulating film 15 is disposed on the first conductor line 11a. The second conductor line 12a and the shield member 12b are disposed on the insulating film 15. A protective film 3 made of a laminated film such as a silicon oxide film or a silicon nitride film is further disposed on the second conductor line 12a. For example, silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ O ₄ ) can be used as the material of the insulating film 15.

FIG. 3 shows a cut surface of the side P2 of the _second conductor wire 12a adjacent to the shield member 12b. Accordingly, in the outermost peripheral portion of the second conductor wire 12a adjacent to the shield member 12b, the inner via 21b is located on the inner side of the center in the line width direction of the second conductor wire 12 and the second conductor wire 11a The conductor wire 12a is connected. Specifically, the inner via 21b is in contact with the second conductor line at the innermost position permitted by the process conditions used when the spiral inductor is formed on the semiconductor wafer. Further, in the inner peripheral portion of the second conductor line 12a, the central via 21a extends between the first conductor line 11a and the second conductor line 12a at the approximate center in the line width direction of the second conductor line 12. Connected. The central via 21a and the inner via 21b penetrate the insulating film 15 substantially parallel to the stacking direction of the first and second conductor layers. The spiral inductor shown in FIG. 2 has a cutting configuration similar to that in FIG. 3 at sides P ₄ , P ₆ , and P ₈ .

In contrast, FIG. 4 shows a cross section of the side P ₁ of the second conductor line 12a which is not close to the shield member 12b. Therefore, in all the portions of the second conductor line 12a, the central via 21a is located between the first conductor line 11a and the second conductor line 12a at the approximate center of the second conductor line 12 in the line width direction. Is connected. The spiral inductor shown in FIG. 2 has a cutting configuration similar to that in FIG. 4 also on the sides P ₃ , P ₅ , and P ₇ .

  3 and 4, the base conductor line 10 does not appear and is not shown, but the base conductor line 10 is a base conductor layer located between the semiconductor substrate 1, the second conductor line 11a, and the pad portion 11b. The vias 14a and 14b penetrate part of the silicon oxide film 2 to connect the base conductor line 10, the second conductor line 11a, and the pad portion 11b.

  The spiral inductor shown in FIGS. 1 to 4 can be manufactured using a known semiconductor manufacturing process. For example, a semiconductor described in JN Burghartz, M. Soyuer, and KA Jenkins, “Integrated RF and Microwave Components in BiCMOS Technology,” IEEE Trans. Electron Devices, vol. 43, no. 9, pp. 1559-1570. It can be manufactured using a manufacturing process. A specific example of the manufacturing method of the spiral inductor is shown below.

  (A) First, a silicon substrate 1 is prepared, and a silicon oxide film is laminated on the silicon substrate 1 by a chemical vapor deposition method (CVD method). A metal film of an alloy of aluminum and copper (AlCu) is deposited on the silicon oxide film 2 by sputtering. A resist pattern corresponding to the shape of the base conductor line 10 is formed by photolithography, and the metal film is selectively etched using an anisotropic etching method such as reactive ion etching (RIE) using the resist pattern as a mask. Thus, the base conductor line 10 is formed.

  (B) Then, a silicon oxide film is laminated by a CVD method, and a resist pattern having openings corresponding to the shapes of the vias 14a and 14b is formed by a photolithography method. Using this resist pattern as a mask, the silicon oxide film is selectively etched using RIE to form contact holes in the silicon oxide film. Tungsten is buried in the contact hole by sputtering and RIE to form vias 14a and 14b.

  (C) Thereafter, a metal film is deposited again by sputtering. The metal film is etched using photolithography and RIE to form the first conductor line 11a and the pad portion 11b. Then, an insulating film 15 made of a silicon oxide film is stacked by CVD, and a contact hole corresponding to the shape of the via 21 is formed in the insulating film 15 by photolithography and RIE. Tungsten is buried in the contact hole by sputtering and RIE to form a via 21.

  (D) After that, the second conductor wire 12a and the shield member 12b are formed in the same manner as the first conductor wire 11a and the pad portion 11b, and the CVD method is performed on the second conductor wire 12a and the shield member 12b. The protective film 3 is formed using Through the above semiconductor manufacturing process, the spiral inductor shown in FIGS. 1 to 4 is completed.

  Next, with reference to FIG. 5 and FIG. 6, the effect which the spiral inductor shown in FIGS. 1-4 shows will be described.

  FIG. 5 is a graph showing the distribution of the Q values of the spiral inductors related to the spiral inductors shown in FIGS. 1 to 4 and the comparative examples 1 and 2 in the frequency band of 100 MHz to 5.00 GHz, The result of the simulation which the inventor performed using the computer is shown.

  The spiral inductor related to the “present invention” in FIG. 5 is the spiral inductor shown in FIGS. The spiral inductor relating to the “comparative example” in FIG. 5 is only shown in FIG. 1 in that the plurality of vias 21 connecting the first conductor line 11a and the second conductor line 12a are all composed of the central via 21a. Unlike the spiral inductor shown in FIG. 4, other configurations are the same as those of the spiral inductor shown in FIGS. 1 to 4. The spiral inductor relating to “Reference Example 1” in FIG. 5 differs from the spiral inductor shown in FIGS. 1 to 4 only in that the shield member 12b is not provided, and other configurations are shown in FIGS. Same as spiral inductor. And the spiral inductor concerning "reference example 2" in FIG. 5 is that the plurality of vias 21 connecting between the first conductor line 11a and the second conductor line 12a are all composed of the central via 21a, The only difference from the spiral inductor shown in FIGS. 1 to 4 is that the shield member 12b is not provided, and the other configuration is the same as that of the spiral inductor shown in FIGS.

  FIG. 6 is a graph showing the distribution of the Q value of each spiral inductor when the distance Dg in the “comparative example” of FIG. 5 is 20 μm, 70 μm, and infinite (no shield), and the inventor performed using a computer. The results of simulation are shown. “Dg = 20 μm” in FIG. 6 corresponds to “Comparative Example” in FIG. 5, and “No Shield” in FIG. 6 corresponds to “Reference Example 2” in FIG.

  As shown in FIG. 6, the shield member 12b is reduced in size by reducing the distance Dg. However, the electromagnetics between the coil portion formed by the first and second conductor wires 11a and 12a and the shield member 12b are shown. Coupling increases, and the Q value of the spiral inductor decreases.

  As shown in FIG. 5, when comparing the “present invention” and the “comparative example”, the inner via 21 b is connected to the second conductor in the portion near the shield member 12 b in the outermost peripheral portion of the second conductor wire 12 a. It can be seen that the Q value of the spiral inductor is increased by contacting the second conductor line 12a inside the center of the line 12a in the line width direction.

  Furthermore, considering “Reference Example 1” and “Reference Example 2”, the spiral inductor shown in FIGS. 1 to 4 does not include the shield member 12b even if the distance Dg is shortened and the shield member 12b is downsized. The peak of Q value almost the same as “Reference Example 1” and “Reference Example 2” can be obtained, and is higher than “Reference Example 1” and “Reference Example 2” in the frequency band of 1.00 GHz to 5.00 GHz. Q value can be obtained.

  As described above, in the outermost peripheral portion of the second conductor wire 12a, at least in the portion close to the shield member 12b, the inner via 21b is second on the inner side of the center in the line width direction of the second conductor wire 12a. It is made to contact with the conductor wire 12a. Thereby, even if the clearance gap between the 2nd conductor wire 12a and the shield member 12b is narrowed, the fall of the Q value of an inductor can be suppressed. Therefore, according to the spiral inductor according to the embodiment of the present invention, the shield member 12b that blocks noise from the external circuit can be reduced in size without reducing the Q value of the inductor.

  The first conductor wire 11a and the second conductor wire 12a may have a shape that approximates the same polygon. Thereby, the data amount of the pattern data of the first conductor line 11a and the second conductor line 12a can be reduced. Further, the polygon may be a regular octagon. Thereby, the parasitic resistance of the first conductor line 11a and the second conductor line 12a is reduced, and at the same time, the amount of pattern data of the first conductor line 11a and the second conductor line 12a can be reduced.

  As described above, the present invention has been described by way of one embodiment, but it should not be understood that the discussion and drawings that form part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  In FIGS. 1 to 4, the central via 21 a is substantially the same as the second conductor line 12 a in the line width direction in other parts of the outermost peripheral part of the second conductor line 12 a except the part adjacent to the shield member 12 b. Although the spiral inductor in contact with the second conductor wire at the center is shown, the present invention is not limited to this. For example, the inner via 21b may be in contact with the second conductor line 12a inside the center in the line width direction of the second conductor line 12a in the entire outermost peripheral portion of the second conductor line 12a.

  Although the case where the first conductor wire 11a and the second conductor wire 12a have a shape that approximates a regular octagon has been described, even if it is a shape that approximates another polygon such as a hexagon, or a shape that includes a curve I do not care. Similarly, the shield member 12b is not limited to a substantially square shape, and may be another polygonal shape or a curved shape.

  The number of vias formed on each side of the regular octagon is not limited to four, and may be a number other than four.

  The number of conductor wires having substantially the same spiral shape is not limited to two, and may be three or more. By connecting three or more conductor wires in parallel by vias, the parasitic resistance is further reduced, so that the Q value is further improved.

  Thus, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention is limited only by the invention specifying matters according to the scope of claims reasonable from this disclosure.

FIGS. 1A and 1B are top views showing conductor wires constituting a spiral inductor according to an embodiment of the present invention. FIG. 1A shows a base conductor wire 10 disposed in a base conductor layer, and FIG. The first conductor wire 11a and the pad portion 11b arranged in one conductor layer are shown, and FIG. 1C shows the second conductor wire 12a and the shield member 12b arranged in the second conductor layer. It is a top view which shows the whole structure of the spiral inductor concerning embodiment of this invention. FIG. 3 is a cross-sectional view of the spiral inductor taken along the line AA in FIG. 2. FIG. 3 is a cross-sectional view of the spiral inductor taken along the line BB in FIG. 2. 5 is a graph showing a distribution of Q values of spiral inductors related to the spiral inductor shown in FIGS. 1 to 4 and the comparative example, reference example 1 and reference example 2 in a frequency band of 100 MHz to 5.00 GHz. 6 is a graph showing a Q value distribution of each spiral inductor when the distance Dg in the “comparative example” of FIG. 5 is 20 μm, 70 μm, and infinite (no shield) in the frequency band of 100 MHz to 5.00 GHz.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Silicon oxide film 3 ... Protective film 10 ... Base conductor wire 11a ... 1st conductor wire 11b ... Pad part 12a ... 2nd conductor wire 12b ... Shield member 14a, 14b, 21 ... Via 15 ... Insulation film 21a ... center via 21b ... inside vias P ₁ ~P 8 _... side

Claims (4)

A first conductor wire having a spiral shape disposed in the first conductor layer;
A second conductor wire disposed in a second conductor layer and having a spiral shape substantially the same as the first conductor wire;
An insulating film disposed between the first conductor layer and the second conductor layer;
A plurality of vias that are arranged along the length direction of the second conductor line and that electrically connect between the first conductor line and the second conductor line through the insulating film;
A shield member surrounding the second conductor wire,
The via contacts the second conductor line on the inner side of the center in the line width direction of the second conductor line in at least a part of the outermost peripheral part of the second conductor line close to the shield member. Spiral inductors characterized by   2. The spiral according to claim 1, wherein the via is in contact with the second conductor line at an innermost position allowed by a process condition used when the spiral inductor is formed on the semiconductor wafer. Inductor.   In the other part of the outermost peripheral part of the second conductor line except for the part close to the shield member, the via is substantially the center in the line width direction of the second conductor line. The spiral inductor according to claim 1, wherein the spiral inductor is in contact with the spiral inductor.   The via is in contact with the second conductor line on the inner side of the center in the line width direction of the second conductor line in the entire outermost peripheral portion of the second conductor line. Item 3. The spiral inductor according to Item 1 or 2.

Images