JP2010273470A - Control circuit of multiplex chopper circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To automatically adjust gate signals to equalize the pulse widths of gate signals between chopper circuits. <P>SOLUTION: A first triangular wave SC1 and a prescribed offset voltage are input into an inverted input terminal of an operational amplifier 301 to obtain a signal, where an inverted signal of the first triangular wave SC1 is offset by a prescribed amount, as a second triangular wave SC2. First and second gate signals g1, g2 are generated from the first and second triangular waves SC1, SC2 and a command signal Sm, respectively. A deviation signal Δg, where the second gate signal g2 is subtracted from the first gate signal g1, is subjected to low-pass filter processing before integration, an error amount ε, namely the integrated value, is input into the inverted input terminal of the operational amplifier 301 as an offset voltage. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a control circuit for a multiple chopper circuit that operates a plurality of chopper circuits in parallel.

  Conventionally, a multiple chopper circuit has been proposed in which a plurality of chopper circuits are connected in parallel and a load current is shared by the plurality of chopper circuits. In such a multi-chopper circuit, for example, when two chopper circuits are operated in parallel, the load chopper circuit is operated with a load current of 50%. For this reason, the gate signals for driving the two chopper circuits have the same conduction ratio, thereby avoiding an unbalance in the output current of each chopper circuit.

FIG. 10 is a circuit diagram showing an example of a double chopper circuit, in which a first chopper circuit 1, a second chopper circuit 2, and a smoothing capacitor 3 are connected in parallel to both ends of a DC power supply 4. Composed. In addition, a control circuit 6 that drives and controls the first chopper circuit 1 and the second chopper circuit 2 is provided.
As shown in FIG. 10, the first chopper circuit 1 has, for example, an IGBT (Insulated Gate Bipolar Transistor) 11 as a switching element, a diode 12 connected in reverse parallel to the IGBT 11, and one end connected to the emitter of the IGBT 11. The direct current reactor 13 and the free wheel diode 14 are provided. The collector of the IGBT 11 is connected to the high potential side of the DC power supply 4, and the end opposite to the IGBT 11 side of the DC reactor 13 is connected to the high potential side of the smoothing capacitor 3. Further, the anode of the reflux diode 14 is connected between the IGBT 11 and the DC reactor 13, and the other end is connected to the low potential side of the DC power supply 4.

Similarly, the second chopper circuit 2 includes an IGBT 21, a diode 22 connected in reverse parallel to the IGBT 21, a DC reactor 23 having one end connected to the emitter of the IGBT 21, and a free wheeling diode 24. The collector of the IGBT 21 is connected to the high potential side of the DC power source 4, and the end opposite to the IGBT 21 side of the DC reactor 23 is connected to the high potential side of the smoothing capacitor 3. Further, the anode of the reflux diode 24 is connected between the IGBT 21 and the DC reactor 23, and the other end is connected to the low potential side of the DC power supply 4.
Then, both ends of the smoothing capacitor 3 are connected to the output ends t1 and t2 of the double chopper circuit.

  The control circuit 6 inputs a voltage detection value V which is a voltage across the smoothing capacitor 3 detected by a voltage sensor (not shown) and a voltage command value V0 which is a target value of the output voltage of the double chopper circuit. Based on the above, a first gate signal g1 for controlling the IGBT 11 of the first chopper circuit 1 and a second gate signal g2 for controlling the IGBT 21 of the second chopper circuit 2 are generated. Then, the first gate signal g1 and the second gate signal g2 are output to the corresponding IGBT 11 or IGBT 21, respectively.

FIG. 11 is a circuit diagram showing a conventional configuration of the control circuit 6 of FIG.
As shown in FIG. 11, the control circuit 6 includes a regulator 81 and a gate signal generation circuit 82.
The regulator 81 is a voltage detected value V across the smoothing capacitor 3 detected by a voltage sensor (not shown), that is, automatic voltage adjustment control (hereinafter referred to as AVR (Automatic Voltage Control)) for controlling the output voltage of the double chopper circuit to a constant voltage. A circuit that performs voltage regulator) control. The regulator 81 receives a voltage command value V0 that is a target value of the output voltage of the double chopper circuit and a voltage detection value V. The regulator 81 includes a computing unit 81a and a PI processing unit 81b. The computing unit 81a subtracts the voltage detection value V from the input voltage command value V0, and the subtraction result is input to the PI processing unit 81b. Is done. The PI processing unit 81b performs a proportional integration process on the calculation result of the calculator 81a, and generates a command signal Sm for making the output voltage of the double chopper circuit coincide with the voltage command value V0.

The gate signal generating circuit 82 is based on a first carrier wave generating circuit 82a that generates a triangular wave (hereinafter also referred to as a first triangular wave) SC1 as a carrier wave, and the triangular wave SC1 generated by the first carrier wave generating circuit 82a. A second carrier wave generation circuit 82b that generates a second triangular wave SC2 whose phase is shifted by 180 ° as a carrier wave, and a first comparator 82c and a second comparator 82d are provided.
The first comparator 82c compares the command signal Sm with the first triangular wave SC1, and outputs the comparison result as a gate signal (hereinafter also referred to as a first gate signal) g1. Similarly, the second comparator 82d compares the command signal Sm with the second triangular wave SC2, and outputs the comparison result as a gate signal (hereinafter also referred to as a second gate signal) g2.

  The second carrier wave generation circuit 82b includes a reference power source 801, a resistor 802 and a variable resistor 803 connected in series, and the resistor 802 and the variable resistor 803 connected in series serve as the reference power source 801. Connected to both ends. In addition, the potential at the connection point between the resistor 802 and the variable resistor 803 is input to the inverting input terminal of the operational amplifier 805 via the resistor 804 as the voltage offset “−Voffset”. The operational amplifier 805 constitutes an adder circuit. The first triangular wave SC1 generated by the first carrier wave generation circuit 82a is input to the operational amplifier 805 via the resistor 806, and the output of the operational amplifier 805 is Input via resistor 807.

The voltage offset “−Voffset” is set to have the same value as the peak value “0-VP” of the first triangular wave SC1, and the adjustment of the voltage offset “−Voffset” is performed by changing the resistance value of the variable resistor 803. This is done by adjusting.
The operational amplifier 805 outputs a waveform based on 0 [V] obtained by adding the peak value “0-VP” to the inverted signal of the first triangular wave SC1, which is the first triangular wave SC1. And a waveform having a phase difference of 180 °, which is a second triangular wave SC2.

  FIG. 12 is a waveform diagram showing the relationship between the signals. FIG. 12A shows the correspondence between the first triangular wave SC1, the command signal Sm, and the first gate signal g1. Further, (b) shows an inverted signal obtained by inverting the first triangular wave SC1 with “0 [V]” as a reference. (C) shows correspondence between the second triangular wave SC2, the command signal Sm, and the second gate signal g2.

As shown in FIG. 12A, the first gate signal g1 has a waveform that becomes a HIGH level when the first triangular wave SC1 is smaller than the command signal Sm.
Further, as shown in FIG. 12C, the second triangular wave SC2 is obtained by adding the peak value “0-VP” of the first triangular wave SC1 to the inverted signal of the first triangular wave SC1 shown in FIG. The added waveform. Further, the second gate signal g2 has a waveform that becomes a HIGH level when the second triangular wave SC2 is smaller than the command signal Sm.

  The second triangular wave SC2 is a waveform obtained by adding the peak value “0-VP” to the inverted signal of the first triangular wave SC1, and the first triangular wave SC1 and the second triangular wave SC2 are 180 °. If the command signal Sm has a phase difference and is substantially constant, the first gate signal g1 and the second gate signal g2 generated based on the first triangular wave SC1 and the second triangular wave SC2 are substantially the same pulse. The signal has a width. That is, the first chopper circuit 1 and the second chopper circuit 2 are controlled so that the conduction ratios α1 and α2 are substantially the same, so that the output current of each chopper circuit is balanced. Energization is performed.

By the way, as described above, by generating the first triangular wave SC1 and the second triangular wave SC2 having a phase difference of 180 °, the first chopper circuit 1 and the second chopper circuit 2 have substantially the same conduction ratio. It can control to become.
However, as shown in FIG. 11, the second triangular wave SC2 is generated by using the inverted signal of the first triangular wave SC1, and the voltage offset “−Voffset” is generated from the reference power source 801 and the variable resistor 803. When configured, a generation error may occur in the second triangular wave SC <b> 2 due to variations in adjustment by the variable resistor 803. Further, even if the voltage offset “−Voffset” is adjusted to a predetermined offset voltage, the voltage offset “−Voffset” may be affected by drift due to a temperature change, and a generation error may occur in the second triangular wave SC2. There is.

  This means that the peak values of the first triangular wave SC1 and the second triangular wave SC2 are deviated, which causes an error in the pulse width between the first gate signal g1 and the second gate signal g2. Become. For this reason, there is a difference in the conduction ratio between the first chopper circuit 1 and the second chopper circuit 2, and an unbalance in the energization current occurs between the two chopper circuits. When the imbalance of the energization current is extreme, there is a possibility of causing a failure in the first chopper circuit 1 and the second chopper circuit 2.

For this reason, for example, based on the output voltage of each chopper circuit, it is determined whether each chopper circuit is operating normally, and when an abnormality is detected, a multiple chopper circuit provided with a protection circuit that issues an alarm Etc. have been proposed (see, for example, Patent Document 1).
In addition, as a method for suppressing changes in the output characteristics of the comparator due to changes in the temperature environment, for example, an offset correction unit is provided on the output side of the comparator, and the offset output signal when the input signal to the comparator is zero A method has also been proposed that suppresses changes in the output characteristics of the comparator due to changes in the temperature environment, etc. by adding and subtracting the offset output signal from the output signal amplified and output by the comparator after reading and storing it. (For example, refer to Patent Document 2).

JP-A-11-289755 JP-A-8-203565

As described above, the first and second gate signals g1 and g2 are generated using the first triangular wave SC1 and the second triangular wave SC2 having a phase difference of 180 °, and the first chopper circuit 1 is By controlling the pulse width of the second chopper circuit so that it matches the pulse width of the first chopper circuit as a reference, the unbalance between the first chopper circuit 1 and the second chopper circuit 2 is suppressed. Can do.
Further, by correcting using the offset output signal so that the valley of the second triangular wave SC2, which is the output of the operational amplifier 805, substantially matches the reference potential 0V, the output characteristic of the operational amplifier 805 is changed with the change of the temperature environment. It can suppress changing.

Here, as described above, when the offset output signal is used to correct the output of the operational amplifier 805, even if the offset output signal is acquired once, the temperature environment after the time when the offset output signal is acquired When the change is relatively large, i.e., when the output characteristics of the operational amplifier 805 may fluctuate as the temperature environment changes, the offset output signal needs to be updated, resulting in the same pulse width or the same It is necessary to have a function of constantly correcting the offset value of the second triangular wave so as to obtain the current value of the flow rate.
Therefore, the present invention has been made paying attention to the above-mentioned conventional unsolved problems, and avoids affecting the multiple chopper circuit due to the generation error of the second carrier wave caused by a change in temperature environment or the like. It is an object of the present invention to provide a control circuit for a multi-chopper circuit capable of such a situation.

  In order to achieve the above object, an invention according to claim 1 of the present invention is applied to a multiple chopper circuit including a plurality of chopper circuits, and a first chopper circuit driving first circuit based on a first carrier wave is applied. A drive signal is generated, and a second drive signal for driving a second chopper circuit is generated based on a second carrier wave whose phase difference from the first carrier wave is a predetermined value set in advance. In the control circuit of the multiple chopper circuit in which the conduction ratio is substantially the same between the drive signal of the second drive signal and the second drive signal, the difference between the first drive signal and the second drive signal is determined as the drive signal. Drive signal difference calculation means for calculating as a difference, and correction means for correcting the second carrier wave based on an integral value of the drive signal difference are characterized.

  According to a second aspect of the present invention, there is provided a control circuit for a multiple chopper circuit, wherein a first carrier wave generating means for generating the first carrier wave and an offset value for a signal obtained by shifting the first carrier wave by the predetermined phase difference. Second carrier generation means for adding and generating the second carrier, and the first drive signal and the second drive signal from the first carrier, the second carrier and the output command value. First drive signal generation means and second drive signal generation means for generating, wherein the drive signal difference calculation means includes the first drive signal generated by the first drive signal generation means and the first drive signal generation means. A drive signal difference with the second drive signal generated by the second drive signal generation means is calculated, and the correction means calculates an integral value obtained by integrating the drive signal difference calculated by the drive signal difference calculation means. Offset in the second carrier generation means It is characterized by setting the preparative value.

Further, in the control circuit of the multiple chopper circuit according to claim 3, the correction means includes offset fixed value generation means for generating a preset fixed offset value, and the offset fixed value generated by the offset fixed value generation means. And an integral value of the drive signal difference is set as an offset value in the second carrier wave generation means.
Further, in the control circuit of the multiple chopper circuit according to claim 4, the multiple chopper circuit has two chopper circuits, and the second carrier wave generating means converts the offset value into a signal obtained by inverting the first carrier wave. Is added to generate the second carrier wave.

  According to a fifth aspect of the present invention, there is provided a multiple chopper circuit control circuit comprising: a first output current detecting means for detecting an output current of the first chopper circuit; and a second output for detecting an output current of the second chopper circuit. Output current detecting means, and the drive signal difference calculating means calculates the deviation between the detected value of the first output current detecting means and the detected value of the second output current detecting means as the drive signal. It is characterized by calculating as a difference.

According to a sixth aspect of the present invention, there is provided a control circuit for a multiple chopper circuit comprising an abnormality detecting means for notifying an abnormality when the integral value of the drive signal difference is equal to or greater than a preset threshold value.
According to the present invention, the second carrier wave is based on the integral value of the drive signal difference, which is the difference between the first drive signal for the first chopper drive circuit and the second drive signal for driving the second chopper circuit. Since the second drive signal is generated based on the corrected second carrier wave, the second drive signal is generated according to the variation in the integral value of the difference between the first drive signal and the second drive signal. It becomes possible to correct the drive signal.

Further, when the second carrier wave is generated by adding the offset value to the signal obtained by shifting the first carrier wave by a predetermined phase difference, the integrated value of the difference between the first drive signal and the second drive signal is By using the sum of the predetermined fixed offset value as the offset value, the offset value can be roughly adjusted by the fixed offset value, and the offset value can be finely adjusted by the drive signal difference.
Further, when the integrated value of the difference between the first drive signal and the second drive signal is equal to or greater than the threshold value, the abnormality detection means notifies the abnormality, so that the multiple chopper circuit is stopped or the abnormality is externally transmitted. Notifications can be made.

According to the present invention, the second carrier wave is based on the integral value of the drive signal difference, which is the difference between the first drive signal for driving the first chopper circuit and the second drive signal for driving the second chopper circuit. As a result, the second drive signal generated based on the second carrier wave is automatically corrected according to the integral value of the difference between the first drive signal and the second drive signal. be able to.
In addition, since the second drive signal is generated by using the sum of the integral value of the difference between the first drive signal and the second drive signal and the predetermined offset fixed value as an offset value, it is roughly based on the offset fixed value. The adjustment can be performed in two stages: a simple adjustment and a fine adjustment based on the integral value of the drive signal difference.
In addition, when the integral value of the drive signal difference is equal to or greater than the threshold value, the abnormality detection means notifies the abnormality, so that the abnormality of the multiple chopper circuit can be notified to the outside.

It is a schematic block diagram which shows an example of the control circuit of the double chopper circuit to which this invention is applied. It is a wave form diagram with which it uses for operation | movement description of this invention. It is a wave form diagram with which it uses for operation | movement description of this invention. It is a wave form diagram with which it uses for operation | movement description of this invention. It is a schematic block diagram which shows an example of the control circuit of the double chopper circuit in 2nd Embodiment. It is a schematic block diagram which shows an example of the double chopper circuit in 3rd Embodiment. It is a schematic block diagram which shows an example of the control circuit of the double chopper circuit in 3rd Embodiment. It is a wave form diagram with which it uses for operation | movement description of 3rd Embodiment. It is a schematic block diagram which shows an example of the control circuit of the double chopper circuit in 4th Embodiment. It is a schematic block diagram which shows an example of a double chopper circuit. It is a schematic block diagram which shows an example of the control circuit of the conventional double chopper circuit. It is a wave form diagram with which it uses for operation | movement description of the conventional control circuit.

Embodiments of the present invention will be described below.
First, the first embodiment will be described.
FIG. 1 is a circuit diagram showing a configuration of a control circuit 6 of a double chopper circuit in the first embodiment. Since the configuration of the double chopper circuit is the same as the configuration of the double chopper circuit shown in FIG. 10, detailed description of the same part is omitted.
As shown in FIG. 1, the control circuit 6 in the first embodiment includes a regulator 31 and a gate signal generation circuit 32.

  Like the conventional regulator 81, the regulator 31 is a circuit that performs automatic voltage adjustment control (hereinafter also referred to as AVR control) for controlling the output voltage of the double chopper circuit to a predetermined voltage. An arithmetic unit 31a for subtracting a voltage detection value V of the output voltage of the double chopper circuit detected by a voltage sensor (not shown) from a voltage command value V0 that is a target value of the output voltage of the heavy chopper circuit, and an arithmetic operation by the arithmetic unit 31a A PI processing unit 31b that performs a proportional integration process on the calculated result and generates a command signal Sm for making the output voltage of the double chopper circuit coincide with the voltage command value V0 is provided.

The gate signal generation circuit 32 generates a first carrier wave, a first carrier wave generation circuit 32a, and a second carrier wave based on the first carrier wave generated by the first carrier wave generation circuit 32a. A carrier wave generation circuit 32b, a first comparator 32c, and a second comparator 32d are provided.
The first carrier wave generation circuit 32a generates a triangular wave (hereinafter also referred to as a first triangular wave) SC1 as a carrier wave.
The first comparator 32c compares the command signal Sm with the first triangular wave SC1, and outputs the comparison result as a gate signal (hereinafter also referred to as a first gate signal) g1. Similarly, the second comparator 32d compares the command signal Sm with a later-described second triangular wave SC2 generated by the second carrier wave generation circuit 32b, and the comparison result is a gate signal (hereinafter referred to as a second signal). (Also referred to as a gate signal).

  Then, the second carrier wave generation circuit 32b includes the operational amplifier 301 that outputs the second triangular wave SC2, and the output signals of the comparator 32c and the comparator 32d, that is, the first gate signal g1 and the second gate signal g2. An arithmetic unit 302 that calculates a deviation, a low-pass filter (also referred to as LPF) 303 that performs a low-pass filter process on the output of the arithmetic unit 302, and an integrator 304 that integrates the output of the low-pass filter 303 are provided.

The computing unit 302 subtracts the output of the comparator 32c, that is, the first gate signal g1, from the output of the comparator 32d, that is, the second gate signal g2, and uses this as the deviation signal Δg of the gate signal, thereby the low-pass filter 303. Output to.
The low-pass filter 303 performs low-pass filter processing on the input deviation signal Δg to remove high-frequency components.
The integrator 304 receives the deviation signal Δg from which the high-frequency component has been removed by the low-pass filter 303 and integrates the deviation signal Δg to obtain an integrated value of the deviation signal Δg. This is held as an error amount ε.

  The operational amplifier 301 constitutes an addition operation circuit, and the first triangular wave SC1 generated by the first carrier wave generation circuit 32a is input via the resistor 305, and the output of the integrator 304 is the resistor 306. Further, the output of the operational amplifier 301 is input via the resistor 307, and the error amount ε, that is, the offset value obtained from the difference between the gate signals g1 and g2 is added to the first triangular wave SC1, It is output to the comparator 32d.

Next, the operation of the first embodiment will be described with reference to the waveform diagrams of FIGS.
2 to 4 are waveform diagrams showing signal waveforms of respective parts of the control circuit 6. FIG. 2A shows a first triangular wave SC1, a command signal Sm, and a first gate signal g1. (B) represents an inverted signal of the first triangular wave SC1. (C) represents the second triangular wave SC2, the command signal Sm, and the second gate signal g2. (D) represents the deviation signal Δg.

As shown in FIG. 2A, the first gate signal g1 has a waveform that is at a HIGH level when the first triangular wave SC1 is smaller than the command signal Sm.
As shown in FIG. 2B, the inverted signal is a signal obtained by inverting the first triangular wave SC1 with “0 [V]” as a reference.
As shown in FIG. 2 (c), the second triangular wave SC2 is a waveform obtained by adding an offset signal to the inverted signal shown in FIG. 2 (b). Therefore, the phase thereof is the same as that of the first triangular wave SC1 and the second triangular wave SC2. The triangular wave SC2 has a waveform shifted by 180 °.

Then, the second gate signal g2 has a waveform that becomes a HIGH level when the second triangular wave SC2 is smaller than the command signal Sm.
Therefore, the conduction ratio α1 of the first gate signal g1 and the conduction ratio α2 of the second gate signal g2 are substantially the same, and the conduction ratio is the same between the first chopper circuit 1 and the second chopper circuit 2. α1 and α2 are controlled to be substantially the same, and energization is performed so that the output currents of the chopper circuits are balanced.

  Here, it is assumed that the signal value when the first gate signal g1 and the second gate signal g2 are HIGH level (on) is “1”, and the signal value when the first gate signal g2 is LOW level (off) is “0”. When the signal values of the first gate signal g1 and the second gate signal g2 are switched at a period approximately half that of the first triangular wave SC1 and the second triangular wave SC2, the gate signal calculated by the calculator 302 is changed. The deviation signal Δg (= first gate signal g1−second gate signal g2) takes a binary value of “+1” and “−1” as shown in FIG. For this reason, even if the deviation signal Δg after the low-pass filter processing is integrated, since “+1” and “−1” are repeated, the integration value repeatedly increases and decreases, and as a result, the integrator The error amount ε, which is the output of 304, maintains the previous value.

Therefore, the inverted signal is offset by the amount corresponding to the previous error amount, and the first gate signal g1 and the second gate signal g2 maintain the waveform having the same pulse width, that is, the first chopper circuit. The conduction ratios of 1 and the second chopper circuit 2 are equal and maintain an equilibrium state.
When the timing of switching the signal values of the first gate signal g1 and the second gate signal g2 is shorter than a half cycle of each triangular wave, the deviation signal Δg is “+1”, “0”, “ −1 ”, but the width of“ +1 ”and the width of“ −1 ”are substantially the same. In this case as well, the integral value simply increases and decreases, resulting in the error amount ε being The value up to will be maintained.

From this state, when the output characteristic of the operational amplifier 301 fluctuates due to a temperature change or the like, for example, as shown in FIG. 3C, when the second triangular wave SC2 is output to a higher value, the command signal Sm and the second The pulse width of the second gate signal g2 generated from the triangular wave SC2 (pulse width when at the HIGH level) becomes shorter.
For this reason, the deviation signal Δg of the gate signal calculated by the calculator 302 from the first gate signal g1 (FIG. 3A) and the second gate signal g2 (FIG. 3C) is as shown in FIG. As shown in (d), the waveform takes “+1”, “0”, and “−1”, and the deviation signal Δg has a period that takes “+1” with respect to a period that takes “−1”. The gate signal g2 becomes longer as the pulse width becomes shorter. Therefore, the deviation signal Δg acts in a direction to increase the integrated value so far, and as a result, the error amount ε increases positively.

Therefore, the error amount ε acts to increase the offset voltage positively, and the second triangular wave SC2 calculated by the operational amplifier 301 moves downward in FIG. 3C. .
As the second triangular wave SC2 moves downward, the pulse width of the second gate signal g2 increases, so that the pulse widths of the first gate signal g1 and the second gate signal g2 are substantially the same. Therefore, the flow rate to the first chopper circuit 1 and the second chopper circuit 2 is controlled to be the same.

On the other hand, when the output characteristic of the operational amplifier 301 fluctuates and the second triangular wave SC2 is output to a lower value as shown in FIG. 4C, for example, the command signal Sm and the second triangular wave SC2 The pulse width of the generated second gate signal g2 (the pulse width when it is at the HIGH level) becomes longer.
Therefore, the deviation signal Δg of the gate signal calculated by the calculator 302 from the first gate signal g1 (FIG. 4A) and the second gate signal g2 (FIG. 4C) is shown in FIG. As shown in d), the waveform takes “+1”, “0”, and “−1”, and the deviation signal Δg has a period that is “−1” with respect to a period that is “+1”. The gate signal g2 becomes longer as the pulse width becomes longer. Therefore, the deviation signal Δg acts in a direction to decrease the integrated value so far, and as a result, the error amount ε increases negatively.

Therefore, the error amount ε acts to increase the offset voltage negatively, and the second triangular wave SC2 calculated by the operational amplifier 301 moves upward in FIG. 4C. .
As the second triangular wave SC2 moves upward, the pulse width of the second gate signal g2 becomes smaller, so that the pulse widths of the first gate signal g1 and the second gate signal g2 become substantially the same. Therefore, the flow rate to the first chopper circuit 1 and the second chopper circuit 2 is controlled to be the same.

As described above, the deviation of the pulse width between the first gate signal g1 and the second gate signal g2 is input as an error amount ε to the addition circuit of the operational amplifier 301, and the deviation of the pulse width corresponding to the error amount ε. Since the offset signal is added so as to eliminate this, the shift amount of the pulse width between the first and second gate signals g1 and g2 can be automatically adjusted.
For this reason, since the gate signals g1 and g2 having substantially the same pulse width can be obtained, the conduction ratios in the first chopper circuit 1 and the second chopper circuit 2 can be made substantially the same. It can be maintained in an equilibrium state.

Even when the output characteristic of the operational amplifier 301 fluctuates due to a change in temperature environment or the like, the first chopper circuit 1 and the second chopper circuit 1 are used to adjust the offset voltage so as to suppress the deviation of the pulse width. The current flowing through the chopper circuit 2 can be maintained in an equilibrium state.
Furthermore, since the offset of the inverted signal is adjusted based on the deviation signal Δg between the first gate signal g1 and the second gate signal g2, the offset is adjusted even when the double chopper circuit is in operation. be able to.

Next, a second embodiment of the present invention will be described.
In the second embodiment, the second carrier wave generation circuit 32b of the gate signal generation circuit 32 is replaced with a second carrier wave generation circuit 40 in the first embodiment. The same parts are denoted by the same reference numerals, and detailed description thereof is omitted.
As shown in FIG. 5, the second carrier wave generation circuit 40 in the second embodiment is further provided with a fixed offset value generation circuit 400 in the second carrier wave generation circuit 32b shown in FIG.

  The offset fixed value generation circuit 400 includes a reference power supply 401, a resistor 402 and a resistor 403 connected in series, and a resistor 404. The resistor 402 and the resistor 403 connected in series are connected to the reference power supply 401. Connected to both ends of the. The potential at the connection point between the resistor 402 and the resistor 403 is input to the inverting input terminal of the operational amplifier 301 via the resistor 404 as the offset fixed value “−Voff”. This fixed offset value “−Voff” is set so as to correspond to the peak value “0-VP” of the first triangular wave SC1.

  Here, at the inverting input terminal of the operational amplifier 301, the first triangular wave SC1 generated by the first carrier wave generation circuit 32a, the offset fixed value “−Voff” generated by the offset fixed value generation circuit 400, and The error amount ε from the integrator 304 is input to an adder circuit constituted by the operational amplifier 301. As a result, the output of the operational amplifier 301 has a waveform obtained by adding the sum of the fixed offset value “−Voff” and the error amount ε to the inverted signal of the first triangular wave SC1.

As a result, the offset voltage necessary for suppressing the deviation of the pulse width between the first gate signal g1 and the second gate signal g2 is composed of the offset fixed value “−Voff” and the error amount ε. The rough potential can be adjusted by the offset fixed value “−Voff” and fine adjustment can be performed by the error amount ε.
Specifically, the offset adjustment amount by the feedback circuit can be reduced by increasing the resistance value of the resistor 306 of the adding circuit and decreasing the adding gain. As an effect of this, the imbalance until the initial value is held in the integrator 304 can be reduced, and the influence when the feedback circuit breaks down can be reduced. be able to.

  In particular, the peak value “0-VP” of the first triangular wave SC1 necessary for setting the inverted signal of the first triangular wave SC1 to a waveform with “0 [V]” as a reference by the offset fixed value “−Voff”. By setting “equivalent” as an offset fixed value “−Voff”, the offset amount to be covered by the error amount ε can be limited only to the offset portion in order to suppress fluctuation due to a change in temperature environment, etc. Is.

Next, a third embodiment of the present invention will be described.
FIG. 6 is a circuit diagram showing an example of a double chopper circuit in the third embodiment. The double chopper circuit according to the third embodiment is further provided with current sensors 7a and 7b in the double chopper circuit according to the first embodiment shown in FIG.
The current sensor 7a is provided between the DC reactor 13 of the first chopper circuit 1 and the output terminal t1 of the double chopper circuit, and detects the output current of the first chopper circuit 1. The current sensor 7b is provided between the DC reactor 23 of the second chopper circuit 2 and the output terminal t1 of the double chopper circuit, and detects the output current of the second chopper circuit 2.
The current detection value I1 of the current sensor 7a and the current detection value I2 of the current sensor 7b are input to the control circuit 6.

FIG. 7 is a circuit diagram showing an example of the control circuit 6 in the third embodiment.
The control circuit 6 according to the third embodiment includes a second carrier generation circuit in place of the second carrier generation circuit 32b in the gate signal generation circuit 32 of the control circuit 6 according to the first embodiment shown in FIG. 50. Note that, in the second carrier wave generation circuit 32 in the first embodiment, the same reference numerals are given to the same parts, and detailed descriptions thereof are omitted.
As shown in FIG. 7, the second carrier wave generation circuit 50 in the third embodiment is generated by the first carrier wave generation circuit 32a that generates the first carrier wave and the first carrier wave generation circuit 32a. A second carrier generation circuit 50 that generates a second carrier based on the first carrier, a first comparator 32c, and a second comparator 32d are provided.

  The first carrier wave generation circuit 32a is similar to the first embodiment, and generates the first triangular wave SC1 as a carrier wave. Further, the comparator 32c generates a first gate signal from the first triangular wave SC1 generated by the first carrier wave generation circuit 32a and the command signal Sm in the same procedure as the comparator 32c in the first embodiment. g1 is generated. On the other hand, the comparator 32d receives the second triangular wave SC2 generated by the second carrier wave generation circuit 50, and from the second triangular wave SC2 and the command signal Sm, the comparator 32d in the first embodiment. The second gate signal g2 is generated in the same procedure as in FIG.

  The second carrier wave generation circuit 50 includes an operational amplifier 501 that outputs the second triangular wave SC2, a calculator 502 that calculates a difference between the current detection value I1 of the current sensor 7a and the current detection value I2 of the current sensor 7b, A low-pass filter (also referred to as LPF) 503 that performs low-pass filter processing on the output of the integrator 502, and an integrator 504 that integrates the output of the low-pass filter 503.

The computing unit 502 subtracts the current detection value I1 that is the output current of the first chopper circuit 1 from the current detection value I2 that is the output current of the second chopper circuit 2, and uses this as the current deviation signal ΔI to perform a low-pass operation. Output to the filter 503.
The low-pass filter 503 performs low-pass filter processing on the input current deviation signal ΔI to remove high-frequency components.
The integrator 504 receives the current deviation signal ΔI from which the high frequency component has been removed by the low-pass filter 503, and integrates this to obtain an integrated value of the current deviation signal ΔI. This is held as an error amount Iε.

  The operational amplifier 501 constitutes an addition operation circuit, and the first triangular wave SC1 generated by the first carrier wave generation circuit 32a is input via the resistor 505, and an error amount that is an output of the integrator 504. Iε is input through the resistor 506, and the output of the operational amplifier 501 is input through the resistor 507, and an error amount Iε, that is, an offset value obtained from the difference between the current detection values I1 and I2 in the first triangular wave SC1. Are added and output to the comparator 32d.

Here, as described above, when the double chopper circuits are operated in parallel, it is necessary to avoid the occurrence of unbalance in the output current of each chopper circuit. For this reason, the first gate signal g1 and the first gate signal g1 The pulse widths of the two gate signals g2 are made the same.
Therefore, adjusting the offset voltage of the second triangular wave SC2 so that the difference in the amount of current flowing through the first chopper circuit 1 and the second chopper circuit 2 becomes zero is different from that of the first chopper circuit 1. This is equivalent to adjusting so that the amount of current flowing through the second chopper circuit 2 matches.
For this reason, an error amount Iε corresponding to an integral value of the current deviation signal ΔI that is a deviation between the current detection value I1 of the current sensor 7a and the current detection value I2 of the current sensor 7b is set as the offset voltage. The effect of the first embodiment can be obtained.

Next, the operation of the third embodiment will be described with reference to the waveform diagram of FIG.
In FIG. 8, (a) represents the first triangular wave SC1, the command signal Sm, and the first gate signal g1. (B) shows the current deviation signal ΔI, (c) to (e) show the second triangular wave SC2, the command signal Sm, and the second gate signal g2, and (c) When the pulse widths of the first gate signal g1 and the second gate signal g2 are the same, (d) shows that the pulse width of the second gate signal g2 is shorter than the pulse width of the first gate signal g1. In this case, (e) represents each waveform when the pulse width of the second gate signal g2 is longer than the pulse width of the first gate signal g1.

  As shown in FIG. 8C, when the pulse widths when the first gate signal g1 and the second gate signal g2 are at the HIGH level match, the current amount of the first chopper circuit 1 is The amount of current of the second chopper circuit 2 substantially matches. For this reason, the current deviation signal ΔI calculated by the calculator 502 becomes substantially zero, and the current error amount Iε output from the integrator 504 maintains the previous value. Therefore, since the offset voltage of the inverted signal of the first triangular wave SC1 maintains the previous value, the second gate signal g2 continues to have a waveform having a pulse width equivalent to that of the first gate signal g1. The conduction ratios of the chopper circuit 1 and the second chopper circuit 2 maintain an equilibrium state.

From this state, when the output characteristic of the operational amplifier 501 fluctuates due to a change in the temperature environment and the second triangular wave SC2 is output to a higher value as shown in FIG. 8D, the second gate signal Since the pulse width of g2 becomes shorter, the energization amount of the second chopper circuit 2 becomes smaller than the energization amount of the first chopper circuit 1.
For this reason, the current deviation signal ΔI calculated by the calculator 502 becomes a positive value as indicated by ΔIa in FIG. 8B, and the current deviation signal ΔI acts in the direction of decreasing the current error amount Iε. As a result, the offset voltage of the inverted signal of the first triangular wave SC1 decreases, and the second triangular wave SC2 moves downward in FIG. 8D. Along with this movement, the pulse width of the second gate signal g2 increases, so that the energization amount to the second chopper circuit 2 increases, and when the energization amount to the first chopper circuit 1 substantially matches, Is maintained at the offset voltage, and the energization amount to each chopper circuit is in a state of maintaining an equilibrium state.

Conversely, as shown in FIG. 8 (e), when the second triangular wave SC2 is output to a lower value, the pulse width of the second gate signal g2 becomes longer, and thus the first chopper circuit 1 is energized. The energization amount of the second chopper circuit 2 is larger than the amount.
For this reason, the current deviation signal ΔI calculated by the calculator 502 becomes a negative value as indicated by ΔIb in FIG. 8B, and the current deviation signal ΔI acts in the direction of increasing the current error amount Iε. As a result, the offset voltage of the inverted signal of the first triangular wave SC1 increases, and the second triangular wave SC2 moves upward in FIG. 8D. Along with this movement, the pulse width of the second gate signal g2 decreases, so that the energization amount to the second chopper circuit 2 decreases, and when the energization amount to the first chopper circuit 1 substantially matches, Is maintained at the offset voltage, and the energization amount to each chopper circuit is in a state of maintaining an equilibrium state.

Therefore, also in this case, the same effect as that of the first embodiment can be obtained.
In the third embodiment as well, as in the second embodiment, an offset fixed value generation that generates an offset fixed value “−Voff” corresponding to the peak value “0-VP” of the first triangular wave SC1 is generated. The circuit 400 may be provided so that the offset voltage is roughly adjusted by the offset fixed value “−Voff”, and the offset voltage is finely adjusted based on the current deviation signal ΔI calculated by the calculator 502.

Next, a fourth embodiment of the present invention will be described.
In the fourth embodiment, an abnormality detection circuit 33 is further provided in the control circuit 6 in the first embodiment. The same parts as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
FIG. 9 shows the configuration of the control circuit 6 in the fourth embodiment. The controller 31 and the gate signal generation circuit 32 have the same functional configuration as that of the first embodiment shown in FIG. And an abnormality detection circuit 33.

As shown in FIG. 9, the abnormality detection circuit 33 includes a comparator 601 and resistors 602 and 603 connected in series. One end of the resistor 602 is connected to the power supply Vcc, and the other end of the resistor 603 is connected. Is grounded.
The error amount ε from the integrator 304 is input to the non-inverting input terminal of the comparator 601 via the absolute value calculation circuit 604. Further, the potential at the connection point between the resistor 602 and the resistor 603 is input to the inverting input terminal of the comparator 601 as a failure determination potential.

Then, the output of the comparator 601 is output to the outside as the failure signal Se. That is, when the error amount ε exceeds a value corresponding to the failure determination potential, the failure signal Se is output to the outside because the pulse width cannot be adjusted.
Here, as described above, since the error amount ε is a value corresponding to the difference in pulse width between the first gate signal g1 and the second gate signal g2, the range of values that the error amount ε can normally take. When it exceeds, it means that the difference in pulse width exceeds the range of pulse width that can normally be taken. That is, if the range of the pulse width that can normally be taken is exceeded, that is, for example, the first gate signal g1 or the second gate signal g2 can be regarded as abnormal, so the pulse width is further adjusted. This is determined to be difficult, and a failure signal Se is output.

  Therefore, by monitoring this failure signal Se, it is possible to detect that some abnormality has occurred, such as an abnormality in the first gate signal g1 or the second gate signal g2. For this reason, by taking measures such as stopping the double chopper circuit based on the failure signal Se, the pulse width is different, and the energization amount to each chopper circuit is operated in an unbalanced state. It is possible to avoid further failure.

For example, an alarm may be issued when the failure signal Se becomes HIGH level, or the output of the first and second gate signals g1 and g2 may be prohibited.
In the fourth embodiment, the case where the abnormality detection circuit 33 is provided in the first embodiment has been described. However, the present invention is not limited to this and is provided in the second to fourth embodiments. In this case as well, the same effects as those of the fourth embodiment can be obtained.

  In particular, in the third embodiment, the current is detected based on the current detection values Ia and Ib, which are current values flowing through the first chopper circuit 1 and the second chopper circuit 2 detected by the current sensors 7a and 7b. Since the error signal Iε is generated, an abnormality of the semiconductor switching element such as the IGBTs 11 and 21 of the first and second chopper circuits 1 and 2, an abnormality of the first gate signal g 1 or the second gate signal g 2, current It is possible to detect that some abnormality such as a detection circuit abnormality has occurred in the double chopper circuit.

  In addition, although the case where it applied to the double chopper circuit was demonstrated in the said embodiment, it does not restrict to this. By making the pulse widths between any gate signal and other gate signals equal, the flow rates of any chopper circuit and the other second, third, etc. chopper circuits are made to coincide. The multi-chopper circuit configured as described above can be applied even to a multi-chopper circuit including three or more chopper circuits.

Further, in the above embodiment, the case where an isosceles triangular triangular wave is applied as a carrier wave has been described. However, the present invention is not limited to this, and for example, a right triangular triangular saw wave can be applied. it can.
Here, in the above embodiment, the first chopper circuit 1 and the second chopper circuit 2 correspond to a plurality of chopper circuits, the first triangular wave SC1 corresponds to the first carrier wave, and the second triangular wave SC2 Corresponds to the second carrier wave, the first gate signal g1 corresponds to the first drive signal, the second gate signal g2 corresponds to the second drive signal, and the calculator 302 or the calculator 502 is driven. It corresponds to the signal difference calculation means.

  In addition, the low-pass filter 303, the integrator 304, the resistor 306, and the operational amplifier 301 in the first and fourth embodiments, and the low-pass filter 303, the integrator 304, the resistor 306, and the offset fixing in the second embodiment. The value generation circuit 400, the low-pass filter 503, the integrator 504, the resistor 506, and the operational amplifier 501 in the third embodiment correspond to correction means.

The first carrier generation circuit 32a corresponds to the first carrier generation means, the second carrier generation circuit 32b corresponds to the second carrier generation means, and the first comparator 32c is the first drive signal. Corresponding to the generation means, the second comparator 32d corresponds to the second drive signal generation means.
Further, the offset fixed value generation circuit 400 corresponds to the offset fixed value generation means, the current sensor 7a corresponds to the first output current detection means, and the current sensor 7b corresponds to the second output current detection means, and the abnormality detection The circuit 33 corresponds to the abnormality detection means.

DESCRIPTION OF SYMBOLS 1 1st chopper circuit 2 2nd chopper circuit 4 DC power supply 6 Control circuit 7a, 7b Current sensor 11, 21 IGBT
31 regulator 32 gate signal generation circuit 32a first carrier wave generation circuit 32b, 40, 50 second carrier wave generation circuit 32c first comparator 32d second comparator 33 abnormality detection circuit 301, 501 operational amplifiers 302, 502 Operators 303 and 503 Low-pass filter 304 and 504 Integrator 400 Offset fixed value generation circuit

Claims (6)

Applied to a multi-chopper circuit having a plurality of chopper circuits, generates a first drive signal for driving the first chopper circuit based on the first carrier wave, and sets a phase difference with the first carrier wave in advance The second drive signal for driving the second chopper circuit is generated based on the second carrier wave having the predetermined value, and the conduction ratio between the first drive signal and the second drive signal is approximately. In the control circuit of the multiple chopper circuit designed to be the same,
Drive signal difference calculating means for calculating a difference between the first drive signal and the second drive signal as a drive signal difference;
And a correction means for correcting the second carrier wave based on an integral value of the drive signal difference. First carrier generation means for generating the first carrier;
Second carrier wave generating means for generating the second carrier wave by adding an offset value to a signal obtained by shifting the first carrier wave by the predetermined phase difference;
First drive signal generation means and second drive signal generation means for generating the first drive signal and the second drive signal from the first carrier wave, the second carrier wave and an output command value; Have
The drive signal difference calculation means calculates a drive signal difference between the first drive signal generated by the first drive signal generation means and the second drive signal generated by the second drive signal generation means. And
2. The multi-chopper circuit according to claim 1, wherein the correction unit sets an integral value obtained by integrating the drive signal difference calculated by the drive signal difference calculation unit as an offset value in the second carrier wave generation unit. Control circuit. The correction means includes offset fixed value generation means for generating a preset fixed offset value,
3. The multiple chopper according to claim 2, wherein a sum of an offset fixed value generated by the offset fixed value generating means and an integral value of the drive signal difference is set as an offset value in the second carrier wave generating means. Circuit control circuit. The multiple chopper circuit has two chopper circuits,
4. The multi-chopper according to claim 2, wherein the second carrier wave generation unit generates the second carrier wave by adding the offset value to a signal obtained by inverting the first carrier wave. 5. Circuit control circuit. First output current detection means for detecting an output current of the first chopper circuit;
Second output current detection means for detecting an output current of the second chopper circuit,
The drive signal difference calculation means calculates a deviation between a detection value of the first output current detection means and a detection value of the second output current detection means as the drive signal difference. The control circuit of the multiple chopper circuit according to any one of claims 2 to 4.   The multiplexing according to any one of claims 1 to 5, further comprising abnormality detection means for performing abnormality notification when the integral value of the drive signal difference is equal to or greater than a preset threshold value. Chopper circuit control circuit.

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