JP2010273376A - Solid imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid imaging device which uses an amplifier type MOS sensor provided with an addition function of the optional number of lines of vertical pixels without increasing the number of lines of memory. <P>SOLUTION: The solid imaging device is equipped with: a pixel array where an unit pixel 6 composed of a photodiode 1, an amplifier Tr 2, a reset Tr 3, a selection Tr 4, and a pixel power source 5 is two-dimensionally arranged; a plurality of first vertical signal lines 8 which transmit an amplifying signal of an unit pixel in a row direction, vertical and horizontal scanning circuits 7, 43 to read out each pixel signal of the pixel array; and noise canceler circuits 13-1, 13-2 which have an adding function of amplifying signals of at least two unit pixels connected with a first vertical signal line of each row. The noise canceler circuit is composed of: a change component detecting circuit 14; an analogue adding means 15; and a memory 16, and the change component of amplifying signal output from the pixel is analogously added to the output of memory kept before adding processing, and the newest output after adding processing is superscribed on the memory. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device using an amplification type MOS sensor.

  In recent years, a solid-state imaging device using an imaging element called an amplification type MOS sensor as a solid-state imaging device is mounted on a low power consumption solid-state imaging device for mobile devices and a high-resolution electronic still camera. The solid-state imaging device using the current amplification type MOS sensor generally uses progressive scanning that reads out pixel signals in the row direction in order, but in order to correspond to the current television system such as the NTSC system or the PAL system, the imaging apparatus A means for adding the pixel signals in the vertical direction is proposed. Also, in a high-resolution solid-state imaging device, pixel signals in the vertical and horizontal directions are added in the imaging device in order to read out a relatively low-resolution image signal at high speed on an electronic viewfinder or a small monitor screen. Means have been proposed.

  FIG. 15 discloses an example of a solid-state imaging device having means for adding pixel signals in the vertical direction, which is disclosed in Japanese Patent Laid-Open No. 2000-106653. As shown in FIG. 15, this solid-state imaging device includes a photodiode 1 as a photoelectric conversion unit, an amplification transistor 2 for amplifying a detection signal of the photodiode 1, a reset transistor 3 for resetting the detection signal of the photodiode 1, and each row. A unit pixel 6 comprising a selection transistor 4 and a pixel power source 5 for selecting the pixel, a vertical scanning circuit 7 for driving the unit pixel 6, and first vertical signal lines 8-1 and 8- , Bias transistors 9-1, 9-2,..., And a bias transistor 9-1 that flow a constant current through the first vertical signal lines 8-1, 8-2,. , 9-2,..., 9-2,..., 9-2,..., 9-2,. Second through A first selection switch transistor 53 and a first hold capacitor 54, and a second selection switch transistor 55 and a second hold connected to the direct signal line 52 and connected in series to the second vertical signal line 52. .., Each comprising a capacitor 56 and a clamp transistor 57 for clamping the second vertical signal line 52 to a predetermined voltage, and the output of the second vertical signal line 52 in each column. .. For reading signals, and a horizontal signal line 42 to which the other terminals of the column selection transistors 41-1, 41-2,. Are composed of a horizontal scanning circuit 43 for driving the column selection transistors 41-1, 41-2,... And an output amplifier 44.

  The adder circuits 58-1, 58-2,... Have first and second hold capacitors 54 and 56 that serve as line memories for two rows, and pixel signals of N rows are supplied to the first hold capacitor 54. , N + 1 rows of signals are stored in the second hold capacitor 56. Thereafter, the first selection switch transistor 53 and the second selection switch transistor 55 are simultaneously turned ON, so that line addition is performed on the second vertical signal line 52.

The sample and hold transistor 51 transmits a signal voltage to the second vertical signal line 52 in response to the ON voltage of the sample and hold line 59. The clamp transistor 57 is arranged to clamp the second vertical signal line 52 to a predetermined voltage (V _REF ) by the reference voltage line 63 corresponding to the ON voltage of the clamp line 62. Reference numerals 60 and 61 denote H1 and H2 lines for applying ON voltages to the first and second selection switch transistors 53 and 55, respectively.

FIG. 16 is a diagram showing an outline of a drive timing chart of the solid-state imaging device having the above configuration. When the address line 12- (N) of the Nth row is selected during the horizontal blanking period, the signal of the unit pixel 6 of the Nth row is sent to the first vertical signal lines 8-1, 8-2,. A voltage is output. At this time, the H1 line 60 is in the ON state and the H2 line 61 is in the OFF state. At the same time, the sample hold line 59 is turned on to connect the first vertical signal lines 8-1, 8-2,... And the clamp capacitor 21 through the sample hold transistor 51. Further, by turning on the clamp line 62, the second vertical signal line 52 is clamped to a predetermined voltage (V _REF ) by the reference voltage line 63 via the clamp transistor 57.

Next, after the clamp line 62 is turned off and the second vertical signal line 52 is placed in a floating state, the reset line 11- (N) in the Nth row is turned on to reset the detection signal of the photodiode 1. At this time, a voltage change ΔVsig (N) before and after resetting the photodiode 1 appears on the first vertical signal lines 8-1, 8-2,. Is transmitted and stored in the first hold capacitor 54. Here, if the capacitance value of the clamp capacitor 21 is C1, and the capacitance values of the first and second hold capacitors 54 and 56 are C2, the amount of charge change ΔQ (N) accumulated in the first hold capacitor 54 is Equation (1) is obtained.
ΔQ (N) = ΔVsig (N) × {C1 / (C1 + C2)} × C2 (1)

Similarly, the H1 line 60 is turned off and the H2 line 61 is turned on, and the pixel signals of N + 1 rows are accumulated in the second hold capacitor 56. At this time, if the voltage change of the first vertical signal lines 8-1, 8-2,... Before and after resetting the photodiode 1 is ΔVsig (N + 1), it is accumulated in the second hold capacitor 56. The charge change amount ΔQ (N + 1) is expressed by the following equation (2).
ΔQ (N + 1) = ΔVsig (N + 1) × {C1 / (C1 + C2)} × C2 (2)

Finally, the H1 line 60 and the H2 line 61 are turned on simultaneously, so that addition in the charge region is performed in the second vertical signal line 52. The charge change amount ΔQ addition in the second vertical signal line 52 after the addition is expressed by the following equation (3).
ΔQ addition = ΔQ (N) + ΔQ (N + 1) = {ΔVsig (N) + ΔVsig (N + 1)}
X {C1 / (C1 + C2)} x C2 (3)

JP 2000-106653 A

  However, in the method using a line memory such as the conventional solid-state imaging device shown in FIGS. 15 and 16, the maximum number of lines that can be added is determined by the number of lines in the line memory, that is, the number of hold capacities. Therefore, it is necessary to prepare in advance line memories for the maximum number of lines to be added, resulting in an increase in the area of the line memory and an increase in the chip area. Further, even when the number of lines to be added is increased as necessary, there is a restriction that it is not possible to add more than the number of lines corresponding to a line memory prepared in advance. As described above, in the solid-state imaging device having a vertical pixel addition function that has been proposed in the past, sufficient consideration is given to the addition of vertical pixels with flexibility, such as changing the number of rows to be added as necessary. Not done.

  The present invention has been made to solve the above-described problems in a solid-state imaging device having a conventional vertical pixel addition function, and can add an arbitrary number of vertical pixels without increasing the number of lines in the line memory. MOS type sensor that can realize the function and also has the function of reducing fixed pattern noise by adding the change component of the pixel signal, which can suppress the increase in sensor chip area and cost An object of the present invention is to provide a solid-state imaging device using the above.

  In order to solve the above problems, the invention according to claim 1 is directed to a unit pixel including a photoelectric conversion unit and an amplification unit that amplifies an output of the photoelectric conversion unit and outputs an amplified signal in a row direction and a column direction. A two-dimensionally arranged pixel array, a plurality of vertical signal lines for transmitting amplified signals of the unit pixels in the column direction, vertical and horizontal scanning circuits for reading out each pixel signal of the pixel array, and each column A clamp means connected to the vertical signal line, and a sample hold means connected to the clamp means via an inverting amplifier, and adds the amplified signals of at least two unit pixels to the feedback capacitance of the inverting amplifier. The solid-state imaging device is configured with a noise canceling unit having an adding function.

  In the solid-state imaging device configured as described above, since the signal of the vertical pixel can be continuously stored in the feedback capacitor of the inverting amplifier, the number of arbitrary rows can be increased without increasing the feedback capacitance of the inverting amplifier serving as a line memory. These pixel signals can be added. In addition, the fixed pattern noise is reduced simultaneously with the addition operation. Thereby, an increase in the chip area of the solid-state imaging device and an increase in cost can be suppressed.

  According to a second aspect of the present invention, in the solid-state imaging device according to the first aspect, the inverting amplifier constituting the noise canceling unit having the addition function can change an amplification factor of the inverting amplifier, and at least two of the inverting amplifiers can be changed. It is characterized by having an addition function for weighting and adding the amplified signal of the unit pixel to the feedback capacitance of the inverting amplifier.

  In the solid-state imaging device configured as described above, since the signal of the vertical pixel can be continuously stored in the feedback capacitor of the inverting amplifier, the number of arbitrary rows can be increased without increasing the feedback capacitance of the inverting amplifier serving as a line memory. These pixel signals can be added. In addition, the fixed pattern noise is reduced simultaneously with the addition operation. Furthermore, since the gain of the inverting amplifier can be changed for each row, an edge enhancement function such as weighted addition can be realized. Thereby, an increase in the chip area of the solid-state imaging device and an increase in cost can be suppressed.

  According to the first aspect of the present invention, since the signal of the vertical pixel can be continuously stored in the feedback capacitor of the inverting amplifier, the number of rows can be increased without increasing the number of inverting amplifiers having the feedback capacitor serving as a line memory. Pixel signals can be added, and fixed pattern noise is reduced simultaneously with the addition operation, thereby suppressing an increase in chip area and an increase in cost. According to the fifth aspect of the present invention, since the signal of the vertical pixel signal can be continuously stored in the feedback capacitor of the inverting amplifier, the number of inverting amplifiers having a feedback capacitor serving as a line memory is not increased. Any number of rows of pixel signals can be added, fixed pattern noise is reduced simultaneously with the addition operation, and the gain of the inverting amplifier can be changed for each row. Can be given.

1 is a circuit configuration diagram showing a first embodiment of a solid-state imaging device according to the present invention. FIG. 2 is a circuit configuration diagram illustrating a specific configuration example of a noise cancellation circuit having an addition function in the embodiment illustrated in FIG. 1. FIG. 3 is a circuit configuration diagram illustrating a configuration example of a third vertical signal line buffer in the noise cancellation circuit having the addition function illustrated in FIG. 2. 5 is a drive timing chart for explaining the operation of the first embodiment. It is a circuit block diagram which shows the structure of the noise cancellation circuit with an addition function which is the principal part of the 2nd Embodiment of this invention. It is a circuit block diagram which shows the structure of the noise cancellation circuit with an addition function which is the principal part of the 3rd Embodiment of this invention. It is a drive timing chart for demonstrating the operation | movement of 3rd Embodiment. It is a circuit block diagram which shows the 4th Embodiment of this invention. FIG. 9 is a circuit configuration diagram illustrating a configuration example of an inverting amplifier according to the fourth embodiment illustrated in FIG. 8. It is a drive timing chart for demonstrating the operation | movement of 4th Embodiment. It is a circuit block diagram which shows the structure of the noise cancellation circuit with an addition function which is the principal part of the 5th Embodiment of this invention. It is a drive timing chart for demonstrating the operation | movement of 5th Embodiment. It is a circuit block diagram which shows the structure of the modification of the noise cancellation circuit with an addition function which is the principal part of 4th Embodiment shown in FIG. FIG. 14 is a drive timing chart for explaining the operation of the modification shown in FIG. It is a circuit block diagram which shows the structural example of the solid-state imaging device with the conventional addition means. 16 is a drive timing chart for explaining the operation of the conventional example shown in FIG.

(First embodiment)
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit configuration diagram showing a first embodiment of a solid-state imaging device using an amplifying MOS sensor according to the present invention. Components corresponding to those in the conventional example shown in FIG. Is shown. The solid-state imaging device according to this embodiment includes a photodiode 1 that is a photoelectric conversion unit, an amplification transistor 2 that amplifies the detection signal of the photodiode 1, and a reset transistor 3 that resets the detection signal of the photodiode 1. A vertical scanning circuit for driving the unit pixel 6, further comprising: a selection transistor 4 for selecting each row; and a pixel array in which a plurality of unit pixels 6 each including a pixel power source 5 are arranged in a row direction and a column direction. 7 and the first vertical signal lines 8-1, 8-2,... That output the pixel signal of the unit pixel 6 and the first vertical signal lines 8-1, 8-2,. .., A bias current adjustment voltage line 10 for determining the current value of the bias transistors 9-1, 9-2,. Noise .., And column selection transistors 41-1 for reading out the output signals of the noise cancellation circuits 13-1, 13-2,. , 41-2,..., And the horizontal signal line 42 to which the other terminals of the column selection transistors 41-1, 41-2,... Are connected, and the column selection transistors 41-1, 41-2,. , And an output amplifier 44 are provided.

  The noise cancellation circuits 13-1, 13-2,... Having an addition function are composed of a change component detection circuit 14, an analog addition means 15, and a memory 16, and are stored in a memory 16 stored before the addition process. The change component of the amplified signal output from the new pixel is added to the output of the new analog in an analog manner, and the latest output after the addition processing is overwritten in the memory 16. In this way, by repeatedly performing analog addition on the output of the memory 16 stored before the addition processing and overwriting the addition output on the memory 16, the pixel signals of any number of rows can be obtained without providing a plurality of memories 16. Can be added.

  FIG. 2 shows a specific configuration example of noise cancellation circuits 13-1, 13-2,... (Hereinafter, represented by reference numeral 13) having an addition function in the present embodiment. In FIG. 2, a noise cancellation circuit 13 having an addition function includes a clamp capacitor 21 connected to first vertical signal lines 8-1, 8-2,. A second vertical signal line 22 connected to the first vertical signal line 8 via the clamp capacitor 21, and a third vertical signal line connected to the second vertical signal line 22 via the sample hold transistor 23. 24, a hold capacitor 25 connected to the third vertical signal line 24, a third vertical signal line buffer 26 whose input terminal is connected to the third vertical signal line 24, a second vertical signal line 22 and a second The clamp transistor 27 is connected to the three vertical signal line buffers 26, and the initialization transistor 28 clamps the third vertical signal line 24 and the hold capacitor 25 to a predetermined voltage (VREF) of the reference voltage line 34. The clamp capacitor 21 in the noise cancellation circuit having the above configuration corresponds to the change component detection circuit 14 in FIG.

  The voltage value of the hold capacitor 25 can be fed back to the second vertical signal line 22 via the third vertical signal line buffer 26 and can be used as the clamp voltage of the second vertical signal line 22. By using this function, a new pixel signal can be added in an analog manner via the clamp capacitor 21 to the output of the hold capacitor 25 stored before the addition process.

  Note that the sample hold transistor 23 connects the second vertical signal line 22 and the third vertical signal line 24 corresponding to the ON voltage of the sample hold line 32. The clamp transistor 27 clamps the second vertical signal line 22 using the output voltage of the third vertical signal line buffer 26 corresponding to the ON voltage of the clamp line 31. The initialization transistor 28 clamps the third vertical signal line 24 and the hold capacitor 25 to a predetermined voltage (VREF) of the reference voltage line 34 corresponding to the ON voltage of the initialization line 33.

  FIG. 3 is a diagram showing a configuration example of the third vertical signal line buffer 26 shown in the present embodiment. This configuration example is configured by connecting a differential amplifier circuit to a voltage follower. That is, a differential input stage composed of transistors 71 and 72, a load composed of transistors 73 and 74, a current source 75, and a power source 76. The gate terminal of the transistor 71 serves as a buffer input terminal 77, and the transistor 72 The output terminal 78 is formed by short-circuiting the gate terminal with the drain. In this way, the voltage applied to the input terminal 77 is output at a lower impedance than the output terminal 78 by connecting the differential amplifier circuit to the voltage follower.

  Next, the operation of the present embodiment will be described with reference to the schematic diagram of the drive timing chart shown in FIG. When the Nth row address line 12-(N) is selected within the horizontal blanking period of the horizontal synchronization signal, the signal voltage of the Nth unit pixel 6 is output to the first vertical signal line 8. At the same time, the clamp line 31 and the initialization line 33 are simultaneously turned on, whereby the third vertical signal line 24 and the hold capacitor 25 are initialized to the predetermined voltage VREF via the initialization transistor 28. The second vertical signal line 22 is also clamped to the predetermined voltage VREF via the third vertical signal line buffer 26 and the clamp transistor 27.

Next, after the clamp line 31 and the initialization line 33 are turned off simultaneously, the sample hold line 32 is turned on, and the second vertical signal line 22 and the third vertical signal line 24 are connected. At this time, the second vertical signal line 22 and the third vertical signal line 24 are in a floating state. Thereafter, the reset line 11- (N) in the Nth row is turned on, and the photodiode 1 is reset. As a result, a voltage change ΔVsig (N) before and after resetting the photodiode 1 appears on the first vertical signal line 8 and is transmitted to the second vertical signal line 22 and the third vertical signal line 24 via the clamp capacitor 21. Accumulated in the hold capacitor 25. Here, when the capacitance value of the clamp capacitor 21 is C1 and the capacitance value of the hold capacitor 25 is C2, the voltage change amount ΔVout (N) and the charge change amount ΔQ (N) accumulated in the hold capacitor 25 are expressed by the following equation ( 4) and (5).
ΔVout (N) = ΔVsig (N) × {C1 / (C1 + C2)} / (4)
ΔQ (N) = ΔVsig (N) × {C1 / (C1 + C2)} × C2 (5)

Subsequently, the initialization line 33 is fixed to the OFF state, and the second vertical signal line 22 is clamped with the voltage value [VREF + ΔVout (N)] of the third vertical signal line 24 reflecting the voltage change amount ΔVout (N). Thereafter, a pixel reset operation of the (N + 1) th row is performed, whereby the pixel signals of the (N + 1) th row are accumulated in the hold capacitor 25 via the clamp capacitor 21. Here, if the voltage change of the first vertical signal line 8 before and after resetting the photodiode 1 is ΔVsig (N + 1), the voltage change amount ΔVout (N) newly accumulated in the hold capacitor 25 and the charge change amount ΔQ (N) is expressed by the following equations (6) and (7).
ΔVout (N + 1) = ΔVsig (N + 1) × {C1 / (C1 + C2)} (6)
ΔQ (N + 1) = ΔVsig (N + 1) × {C1 / (C1 + C2)} × C2 (7)

In this way, analog addition of the vertical pixel signals is performed by clamping the second vertical signal line 22 using the voltage value of the hold capacitor 25 stored before the addition processing. The voltage change amount ΔVout addition and the charge change amount ΔQ addition after the addition in the hold capacitor 25 are expressed by the following equations (8) and (9).
ΔVout addition = ΔVout (N) + ΔVout (N + 1) = {ΔVsig (N) + ΔVsig (N + 1)}
× {C1 / (C1 + C2)} (8)
ΔQ addition = ΔQ (N) + ΔQ (N + 1) = {ΔVsig (N) + ΔVsig (N + 1)}
X {C1 / (C1 + C2)} x C2 (9)

(Second Embodiment)
FIG. 5 is a circuit configuration diagram showing a configuration of a noise canceling circuit portion which is a main part of the second embodiment of the solid-state imaging device using the amplification type MOS sensor according to the present invention. The noise cancellation circuit in this embodiment is configured so that the voltage fluctuation value of the first vertical signal line 8 can be stored in the hold capacitor 25 as it is, and the configuration will be described next. In addition, the same code | symbol is attached | subjected and shown to the component corresponding to 1st Embodiment.

  The noise cancellation circuit of the present embodiment is obtained by adding a second vertical signal line buffer 80 between the second vertical signal line 22 and the sample and hold transistor 23. The other configuration is the first embodiment shown in FIG. It is the same as the form. The outline of the drive timing chart is the same as that of the first embodiment shown in FIG.

  Next, the operation of the present embodiment will be described. The selection operation of the N-th address line 12- (N) and the initialization operation of the second vertical signal line 22, the third vertical signal line 24, and the hold capacitor 25 in the horizontal blanking period are shown in FIG. The operation is the same as that of the noise cancellation circuit of the first embodiment. Next, the clamp line 31 and the initialization line 33 are simultaneously turned off, the sample hold line 32 is turned on, and the clamp voltage of the second vertical signal line 22 is output via the second vertical signal line buffer 80. The third vertical signal line 24 and the hold capacitor 25 are driven. At this time, the second vertical signal line 22 is in a floating state.

Thereafter, the reset line 11- (N) in the Nth row is turned on, and the detection signal of the photodiode 1 is reset. As a result, a voltage change ΔVsig (N) before and after resetting the photodiode 1 appears on the first vertical signal line 8, and the clamp capacitor 21, the second vertical signal line 22, the second vertical signal line buffer 80, and the third vertical signal. Accumulated in the hold capacitor 25 via the line 24. Here, since the clamp capacitor 21 and the hold capacitor 25 are connected via the second vertical signal line buffer 80, the voltage change ΔVsig of the first vertical signal line 8 as shown in the following equations (10) and (11). (N) is stored in the hold capacitor 25 as it is.
ΔVout (N) = ΔVsig (N) (10)
ΔQ (N) = ΔVsig (N) × C2 (11)

Subsequently, the initialization line 33 is fixed to the OFF state, and the second vertical signal line 22 is clamped with the voltage value [V _REF + ΔVout (N)] of the third vertical signal line 24 reflecting the voltage change amount ΔVout (N). After that, the pixel signal of the (N + 1) th row is accumulated in the hold capacitor 25 by performing the pixel reset operation of the (N + 1) th row. Here, if the voltage change of the first vertical signal line 8 before and after resetting the photodiode 1 is ΔVsig (N + 1), the voltage change amount ΔVout (N) newly accumulated in the hold capacitor 25 and the charge change amount ΔQ (N) is expressed by the following equations (12) and (13).
ΔVout (N + 1) = ΔVsig (N + 1) (12)
ΔQ (N + 1) = ΔVsig (N + 1) × C2 (13)

In this way, analog addition of the vertical pixel signals is performed by clamping the second vertical signal line 22 using the voltage value of the hold capacitor 25 stored before the addition processing. The voltage change amount ΔVout addition and the charge change amount ΔQ addition after the addition in the hold capacitor 25 are expressed by the following equations (14) and (15).
ΔVout addition = ΔVout (N) + ΔVout (N + 1) = ΔVsig (N) + ΔVsig (N + 1)
·········(14)
ΔQ addition = ΔQ (N) + ΔQ (N + 1) = {ΔVsig (N) + ΔVsig (N + 1)} × C 2
・ ・ ・ ・ ・ ・ ・ ・ ・ (15)

  As described above, according to the present embodiment, the voltage fluctuation of the first vertical signal line 8 can be accumulated in the hold capacitor 25 without attenuation. Furthermore, since the voltage change amount and the charge change amount are determined independently of the clamp capacitor 21, the degree of freedom in design can be increased, for example, by reducing the clamp capacitor 21 for higher speed.

(Third embodiment)
FIG. 6 is a circuit configuration diagram showing a configuration of a noise canceling circuit portion which is a main part of a third embodiment of the solid-state imaging device using the amplification type MOS sensor according to the present invention. In this embodiment, the third vertical signal line buffer 26 and the second vertical signal line buffer 80 in the second embodiment shown in FIG. 5 can be shared, and the voltage fluctuation value of the first vertical signal line 8 can be changed. The configuration is such that it can be stored in the hold capacitor 25 as it is. Next, the configuration will be described. In FIG. 6, components corresponding to those in the second embodiment shown in FIG. 5 are denoted by the same reference numerals.

  In the present embodiment, as shown in FIG. 6, the first buffer output switching transistor 81 for connecting the clamp transistor 27 and the output of the third vertical signal line buffer 26, the sample hold transistor 23, and the third vertical signal line buffer. 26, a second buffer output switching transistor 82 for connecting the outputs of 26, a first buffer input switching transistor 83 for connecting the input terminals of the third vertical signal line 24 and the third vertical signal line buffer 26, and a second vertical signal. By using the second buffer input switching transistor 84 that connects the line 22 and the input terminal of the third vertical signal line buffer 26, the third vertical signal line buffer 26 and the second vertical signal line buffer 26 in the second embodiment shown in FIG. Two vertical signal line buffers 80 are shared.

  The first buffer output switching transistor 81 and the first buffer input switching transistor 83 are turned on in response to the on voltage of the first buffer switching line 85, and the voltage of the third vertical signal line 24 is set to the second voltage. The signal is transmitted to the vertical signal line 22. The second buffer output switching transistor 82 and the second buffer input switching transistor 84 are turned on in response to the on voltage of the second buffer switching line 86, and the voltage of the second vertical signal line 22 is changed to the third voltage. The signal is transmitted to the vertical signal line 24.

FIG. 7 is a diagram showing an outline of a drive timing chart for explaining the operation of the present embodiment. Next, the operation of the present embodiment will be described with reference to this timing chart. When the second vertical signal line 22 is clamped, the first buffer switching line 85 is on and the second buffer switching line 86 is off. Further, when the voltage fluctuation of the first vertical signal line 8 is accumulated in the hold capacitor 25, the first buffer switching line 85 is set to the off voltage and the second buffer switching line 86 is set to the on voltage. The voltage change amount ΔVout addition and the charge change amount ΔQ addition in the hold capacitor 25 when the pixel signals of the Nth row and the N + 1th row are added are expressed by the following equations (16) and (17).
ΔVout addition = ΔVout (N) + ΔVout (N + 1) = ΔVsig (N) + ΔVsig (N + 1)
・ ・ ・ ・ ・ ・ ・ ・ ・ (16)
ΔQ addition = ΔQ (N) + ΔQ (N + 1) = {ΔVsig (N) + ΔVsig (N + 1)} × C 2
・ ・ ・ ・ ・ ・ ・ ・ ・ (17)

  In the present embodiment, as described above, the voltage fluctuation of the first vertical signal line 8 can be accumulated in the hold capacitor 25 without attenuation. Further, since the third vertical signal line buffer 26 and the second vertical signal line buffer 80 can be shared, the number of elements and current consumption can be reduced.

(Fourth embodiment)
FIG. 8 is a circuit configuration diagram showing a fourth embodiment of the solid-state imaging device using the amplification type MOS sensor according to the present invention, and the constituent elements corresponding to those in the first embodiment shown in FIG. Are denoted by the same reference numerals. The solid-state imaging device according to this embodiment includes a photodiode 1 as a photoelectric conversion unit, an amplification transistor 2 that amplifies a detection signal of the photodiode 1, a reset transistor 3 that resets the detection signal of the photodiode 1, and each row. A unit pixel 6 including a selection transistor 4 and a pixel power source 5 for selection, a vertical scanning circuit 7 for driving the unit pixel 6, and first vertical signal lines 8-1 and 8 for outputting pixel signals of the unit pixel 6. ,..., Bias transistors 9-1, 9-2,... That pass a constant current through the first vertical signal lines 8-1, 8-2,. Are provided with bias current adjustment voltage lines 10 for determining current values of 1, 9-2,..., And noise cancellation circuits 97-1, 97-2,.

  The noise cancellation circuits 97-1, 97-2,... Are connected to the first vertical signal lines 8-1, 8-2,. A signal line 22, an inverting amplifier 91 that inverts and amplifies the voltage change of the second vertical signal line 22, and a third vertical signal line 24 to which the output of the inverting amplifier 91 is connected via the first sample and hold transistor 23. The hold capacitor 25 connected to the third vertical signal line 24, the clamp transistor 92 having a function of short-circuiting the output of the second vertical signal line 22 and the inverting amplifier 91, the second vertical signal line 22 and the feedback capacitor 93 The fourth vertical signal line 94 connected via the second vertical signal line 94, the second sample hold transistor 95 connecting the fourth vertical signal line 94 and the output of the inverting amplifier 91, and the fourth vertical signal line 94 are clamped to a predetermined voltage. An initialization transistor 96 is included.

  Further, in the solid-state imaging device according to this embodiment, the column selection transistor 41- for reading out the output signal of the third vertical signal line 24 of each column of the noise cancellation circuits 97-1, 97-2,. Are connected to the other terminals of the column selection transistors 41-1, 41-2,... And the column selection transistors 41-1, 41-2. ,... Are provided with a horizontal scanning circuit 43 and an output amplifier 44.

  The first and second sample and hold transistors 23 and 95 connect the output of the inverting amplifier 91 to the third vertical signal line 24 and the fourth vertical signal line 94 corresponding to the ON voltage of the sample and hold line 99. . The clamp transistor 92 sets the voltage of the second vertical signal line 22 to the optimum operating point of the inverting amplifier 91 by short-circuiting the input / output terminal of the inverting amplifier corresponding to the ON voltage of the clamp line 98. The initialization transistor 96 clamps the voltage of the fourth vertical signal line 94 to a predetermined voltage of the reference voltage line 101 in response to the ON voltage of the initialization line 100.

  Here, if the open loop gain of the inverting amplifier 91 is sufficiently large (for example, 100 or more), an inverted signal of gain = − (C1 / C3) is obtained at the output of the inverting amplifier 91 by the clamp capacitor 21 and the feedback capacitor 93. Thus, the pixel signal can be continuously accumulated in the feedback capacitor 93.

  FIG. 9 is a diagram illustrating a configuration example of the inverting amplifier 91 according to the present embodiment. In this configuration example, the inverting amplifier transistor 105 includes a inverting amplification transistor 105, a current source 106, and a power source 107, and a gate terminal of the inverting amplification transistor 105 is input. A connection point between the terminal 108, the inverting amplification transistor 105 and the current source 106 is used as an output terminal 109.

  FIG. 10 is a diagram showing an outline of a drive timing chart for explaining the operation of the present embodiment. Next, the operation of the present embodiment will be described with reference to this timing chart. When the Nth row address line 12-(N) is selected within the horizontal blanking period, the signal voltage of the Nth unit pixel 6 is output to the first vertical signal line 8. At the same time, by turning on the clamp line 98, the input / output of the inverting amplifier 91 is short-circuited, the second vertical signal line 22 is clamped at the optimum operating point of the inverting amplifier, and the initialization line 100 is turned on. The fourth vertical signal line 94 is initialized to a predetermined voltage VREF via the initialization transistor 96.

  Next, after the clamp line 98 and the initialization line 100 are turned off, the sample hold line 99 is turned on, and the fourth vertical signal line 94, the output of the inverting amplifier 91, and the hold capacitor 25 are connected. At this time, assuming that the capacitance value of the feedback capacitor 93 is C3, the inverting amplifier 91, the clamp capacitor 21 and the feedback capacitor 93 constitute an inverting amplifier circuit with a gain =-(C1 / C3), and the second vertical signal line 22 is The optimum operating point is fixed by the feedback loop of the inverting amplifier 91.

Thereafter, the reset line 11- (N) in the Nth row is turned on, and the detection signal of the photodiode 1 is reset. At this time, a voltage change ΔVsig (N) before and after resetting the photodiode 1 appears on the first vertical signal line 8 and is transmitted to the third vertical signal line 24 via the clamp capacitor 21 and the feedback capacitor 93, thereby holding capacitance 25. Accumulated in. Here, when the capacitance value of the clamp capacitor 21 is C1 and the capacitance value of the feedback capacitor 93 is C3, the voltage change amount ΔVout (N) and the charge change amount ΔQ (N) accumulated in the hold capacitor 25 are expressed by the following formulas ( 18) and (19).
ΔVout (N) = − ΔVsig (N) × (C1 / C3) (18)
ΔQ (N) = − ΔVsig (N) × (C1 / C3) × C2 (19)

Subsequently, by fixing the initialization line 100 to the OFF state, the second vertical signal line 22 can be clamped while the voltage fluctuation accumulated in the feedback capacitor 93 is maintained. Thereafter, the pixel signal of N + 1 rows is accumulated in the hold capacitor 25 via the feedback capacitor 93 by performing the same readout operation. At this time, if the voltage change of the first vertical signal line 8 before and after resetting the photodiode 1 is ΔVsig (N + 1), the voltage change amount ΔVout (N) newly accumulated in the hold capacitor 25 and the charge change amount ΔQ (N) is expressed by the following equations (20) and (21).
ΔVout (N + 1) = − ΔVsig (N + 1) × (C1 / C3) (20)
ΔQ (N + 1) = − ΔVsig (N + 1) × (C1 / C3) × C2 (21)

As described above, the inverting amplifier 91, the clamp capacitor 21 and the feedback capacitor 93 constitute an inverting amplifier circuit with a gain =-(C1 / C3), and the voltage change of the first vertical signal line 8 is inverted and amplified to provide feedback. Addition is continuously performed in the capacitor 93. The voltage change amount ΔVout addition and the charge change amount ΔQ addition in the hold capacitor 25 after the addition are expressed by the following equations (22) and (23).
ΔVout addition = ΔVout (N) + ΔVout (N + 1) = − {ΔVsig (N) + ΔVsig (N + 1)}
× (C1 / C3) (22)
ΔQ addition = ΔQ (N) + ΔQ (N + 1) = − {ΔVsig (N) + ΔVsig (N + 1)}
X (C1 / C3) x C2 (23)

(Fifth embodiment)
FIG. 11 is a circuit configuration diagram showing a configuration of a noise canceling circuit portion which is a main part of the fifth embodiment of the solid-state imaging device using the amplification type MOS sensor according to the present invention. In this embodiment, the value of the clamp capacitor 21 that connects the first vertical signal line 8 and the second vertical signal line 22 can be changed, so that the gain of the inverted signal can be increased for each row. Since adjustment is possible, an edge enhancement function such as weighted addition can be realized. Next, the configuration will be described. In addition, the same code | symbol is attached | subjected and shown to the component corresponding to 4th Embodiment.

  In the present embodiment, a second clamp capacitor 111 and a clamp capacitor selection transistor are provided between the first vertical signal line 8 and the second vertical signal line 22 in the noise cancellation circuit of the fourth embodiment shown in FIG. 112 is added, and the clamp capacitor selection transistor 112 is configured to connect the second clamp capacitor 111 in parallel to the clamp capacitor 21 in accordance with the ON voltage of the gain switching line 113.

  FIG. 12 is a diagram showing an outline of a drive timing chart for explaining the operation of the present embodiment. Next, the operation of the present embodiment will be described with reference to this timing chart. When adding pixel signals in the (N + 1) th row, the gain switching line 113 is turned on, and the second clamp capacitor 111 is connected in parallel to the clamp capacitor 21. At this time, if the capacitance value of the second clamp capacitor 111 is C4, the gain of the inverting amplifier circuit is-{(C1 + C4) / C3}, which is a larger gain.

The basic operation is the same as that of the fourth embodiment shown in FIG. 8 except that the gain of the inverting amplifier circuit is changed when adding the pixel signals of the (N + 1) th row, and the voltage change amount ΔVout in the hold capacitor 25 after the addition is added. The addition and the charge change amount ΔQ addition are expressed by the following equations (24) and (25).
ΔVout addition = ΔVout (N) + ΔVout (N + 1) = − {ΔVsig (N)} × (C1 / C3)
− {ΔVsig (N + 1)} × {(C1 + C4) / C3}
·········(twenty four)
ΔQ addition = ΔQ (N) + ΔQ (N + 1) = − {ΔVsig (N)} × (C1 / C3) × C2
-{ΔVsig (N + 1)} × {(C1 + C4) / C3} × C2
·········(twenty five)

  As described above, according to this embodiment, since the gain of the inverted signal can be adjusted for each row, an edge enhancement function such as weighted addition can be realized.

  In addition, the change of the circuit configuration and the driving method of each embodiment according to the present invention can be widely performed without departing from the scope of the claims. For example, the number of pixels to be vertically added can be two or more. Further, as shown in FIG. 13, the hold capacitor 25 is reduced from the configuration of the fourth embodiment shown in FIG. 8, and the output voltage of the inverting amplifier 91 is directly connected to the column selection transistors 41-1, 41-2,. It is also possible to output a voltage to the horizontal signal line 42 via A drive timing chart in the case of this modification is shown in FIG. Further, even when the constituent elements and the driving method of the unit pixel 6 are changed, it can be dealt with by changing the driving method of the adding circuit.

DESCRIPTION OF SYMBOLS 1 Photodiode 2 Amplification transistor 3 Reset transistor 4 Selection transistor 5 Pixel power supply 6 Unit pixel 7 Vertical scanning circuit 8-1, 8-2, ... 1st vertical signal line 9-1, 9-2, ... Bias Transistor
10 Bias current adjustment voltage line
11- (N), 11- (N + 1), .. Reset line
12- (N), 12- (N + 1), .. Address line
13-1, 13-2, ... Noise cancellation circuit
14 Change component detection circuit
15 Analog addition means
16 memory
21 Clamp capacity
22 Second vertical signal line
23 Sample hold transistor
24 3rd vertical signal line
25 Hold capacity
26 Third vertical signal line buffer
27 Clamp transistor
28 Initializing transistor
31 Clamp wire
32 Sample hold wire
33 Initialization line
34 Reference voltage line
41-1, 41-2, ... Column selection transistor
42 Horizontal signal line
43 Horizontal scanning circuit
44 Output amplifier
71, 72 Differential input stage transistors
73, 74 Load transistor
75 Current source
76 Power supply
77 Input terminal
78 Output terminal
80 Second vertical signal line buffer
81 First buffer output switching transistor
82 Second buffer output switching transistor
83 First buffer input switching transistor
84 Second buffer input switching transistor
85 First buffer switching line
86 Second buffer switching line
91 Inverting amplifier
92 Clamp transistor
93 Return capacity
94 Fourth vertical signal line
95 Second sample and hold transistor
97-1, 97-2, ... Noise cancellation circuit
98 Clamp wire
99 Sample hold line
100 Initialization line
101 Reference voltage line
105 Inverting amplification transistor
106 Current source
107 Power supply
108 Input terminal
109 Output terminal
111 Second clamp capacity
112 Clamp capacitance selection transistor
113 Gain switching line

Claims (2)

  A pixel array in which unit pixels including a photoelectric conversion unit and an amplification unit that amplifies an output of the photoelectric conversion unit and outputs an amplified signal are two-dimensionally arranged in a row direction and a column direction, and the unit pixel in a column direction A plurality of vertical signal lines for transmitting the amplified signal, vertical and horizontal scanning circuits for reading out each pixel signal of the pixel array, clamping means connected to the vertical signal line for each column, and the clamping means And a sample-and-hold unit connected via an inverting amplifier, and a noise canceling unit having an addition function for adding amplified signals of at least two unit pixels to a feedback capacitor of the inverting amplifier. A solid-state imaging device.   The inverting amplifier that constitutes the noise canceling unit having the adding function is capable of changing an amplification factor of the inverting amplifier, and an addition function that weights and adds amplified signals of at least two unit pixels to a feedback capacitor of the inverting amplifier. The solid-state imaging device according to claim 1, wherein:

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