JP2010273095A - Imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an imaging apparatus which stably supplies operation voltage and suppresses a crosstalk phenomenon between the adjacent pixels even when the number of pixels increases. <P>SOLUTION: Voltage supply lines (30, 34A) which supply the operation voltage are arranged like a mesh according to each pixel part (PD), and the voltage supply lines are interconnected via a jumper wiring (36A) of another wiring layer. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an imaging apparatus, and more particularly to a wiring structure that can stably supply an operating voltage and efficiently supply an optical signal to a photoelectric conversion unit to suppress a crosstalk phenomenon between adjacent pixels.

  In recent years, digital cameras have been used for a wide range of applications. High performance is required for single-lens reflex cameras, compact digital cameras, cameras mounted on mobile phones, and the like. The specifications that require high performance include the number of pixels, image quality, processing speed, and the number of images that can be continuously shot.

  A CMOS image sensor has been widely used as an image sensor used in the digital camera. As the number of pixels increases for higher performance of the image sensor, the number of pixels arranged in the horizontal and vertical directions increases. Usually, a high-side power supply line (VDD power supply line) and a low-side power supply line (ground line) that supply an operating voltage to the transistors that constitute the pixel reading unit continuously extend in the vertical direction to each pixel column. Arranged accordingly. In this configuration, the number of pixels provided corresponding to one power supply line is large, and the wiring length of the power supply line becomes long. In order to reduce the voltage drop due to the resistance of the wiring, the power supply voltage is supplied from both ends of the power supply line.

  However, when the power supply line is locally narrowed or disconnected due to variations in the manufacturing process, a voltage drop occurs in the power supply line, and a necessary level of voltage is transferred to the defective wiring ( Therefore, the pixel cannot be supplied to the pixel arranged corresponding to the power source line), and the image quality is deteriorated.

  Although it is a different technical field, the structure which strengthens power supply wiring is shown by patent document 1 (patent publication 2758504). This Patent Document 1 shows a configuration in which power supply lines are arranged on a memory array in a mesh shape in the semiconductor memory field. Specifically, in the power supply wiring layout shown in Patent Document 1, local power supply lines are arranged in the sense amplifier band and the word line backing region. In the sense amplifier band, sense amplifiers for reading data are arranged corresponding to the memory cell columns (bit lines). A word line for selecting a memory cell row has a word line shunt structure and is composed of a polysilicon gate wiring and an upper metal wiring. In the word line backing region, the polysilicon gate wiring and the metal wiring are electrically connected. These word line backing regions and sense amplifier bands are orthogonal to each other, and the local power supply lines arranged in these orthogonal directions are electrically connected. By arranging the power supply lines in this mesh shape, the wiring resistance of the power supply lines is reduced and the power supply voltage is stably supplied.

  Further, when the number of pixels increases, the layout area of the photoelectric conversion unit that converts the received light signal into an electrical signal is reduced. In this case, it is necessary to efficiently supply the light reception signal to the photoelectric conversion unit, reliably transmit the light reception signal to each pixel, and reduce the crosstalk phenomenon due to the penetration of the light reception signal between adjacent pixels. A configuration for reducing such a crosstalk phenomenon is disclosed in Japanese Patent Application Laid-Open No. 2004-104203. In the configuration shown in Patent Document 2, in addition to the horizontal light-shielding portion disposed above the photodiode, adjacent to the photodiode of the photoelectric conversion element of each pixel, a vertical light-shielding barrier is further provided in the row and column directions. Deploy. These vertical light blocking barriers prevent incident light from entering the adjacent pixels and reduce the crosstalk phenomenon.

Japanese Patent Publication No. 2758504 JP 2004-104203 A

  In the above-mentioned Patent Document 1, the power supply lines are arranged in a mesh shape. However, the arrangement position of the local power supply line is the sense amplifier band in which the sense amplifier is arranged and the word line backing region. In the word line backing region, the polysilicon gate wiring constituting the gate of the memory cell transistor and the upper metal wiring are electrically connected. The sense amplifier band extends in the row direction, and the word line backing region extends in the column direction. No memory cell is arranged in any region. Therefore, a plurality of memory cells are arranged between adjacent local power supply lines of the mesh-shaped power supply structure of Patent Document 1 in both row and column directions, and the pitch of the power supply lines is relatively large.

  On the other hand, in an imaging apparatus, a power supply line is conventionally arranged corresponding to each pixel column. Control signal lines for transmitting data selection, readout and transfer control signals are arranged for the pixel columns and pixel rows. Therefore, when the mesh-like power supply structure of Patent Document 1 having a sufficient wiring pitch is applied to the conventional power supply wiring structure of the imaging apparatus, a problem of collision between the control signal line and the power supply line occurs. In Patent Document 1, the local power supply line of the mesh power supply wiring is merely arranged in a region where the control signal line is not arranged or arranged in a wiring layer different from the control signal line. No consideration is given to a configuration in which a local power supply line is arranged corresponding to each memory cell column as in the imaging device.

  In the configuration disclosed in Patent Document 2, a vertical light shielding barrier is arranged for each pixel corresponding to two sides of the photodiode, separately from the horizontal light shielding film on the upper layer of the photodiode. It is necessary to further arrange a dedicated light shielding film for light shielding. The vertical light shielding barrier includes a dummy metal wiring in the same layer as the metal wiring extending in the row direction, and is disposed between the control signal lines. Therefore, there arises a problem that the pitch of the control signal line is increased due to the light blocking barrier, and it is difficult to reduce the area of the pixel. Patent Document 2 only discloses a structure in which a dedicated light blocking barrier is provided to prevent incident light from entering adjacent pixels, and does not consider the power supply wiring structure.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an imaging apparatus that can stably supply a predetermined operating voltage and avoid the entrance of incident light to adjacent pixels.

  In one embodiment, an imaging apparatus according to the present invention includes a plurality of pixel units arranged in a matrix and a voltage supply line that supplies a predetermined voltage to each pixel unit. The plurality of pixel units convert received light signals into electrical signals. The voltage supply line is arranged in a mesh shape so as to surround each pixel portion.

  A voltage supply line is arranged in a mesh shape for each pixel. Therefore, even if a failure occurs in the voltage supply line for one pixel, the operation voltage at the same level as the voltage supply line in the adjacent pixel column can be supplied, and the voltage failure can be avoided.

  Further, by arranging the mesh in correspondence with each pixel, at least the voltage supply line can be used as a light shielding film, and the crosstalk phenomenon between adjacent pixels can be reliably performed without using an extra structure. Can be prevented.

It is a figure which shows roughly the whole structure of the imaging device according to Embodiment 1 of this invention. It is a figure which shows concretely the structure of the imaging unit shown in FIG. FIG. 3 is a timing diagram illustrating an operation of the imaging device illustrated in FIGS. 1 and 2. It is a figure which shows roughly the layout of the power wire of the imaging device according to Embodiment 1 of this invention. FIG. 5 is a diagram more specifically showing a layout of power supply wirings shown in FIG. 4. It is a figure which shows roughly the cross-section of the pixel part according to Embodiment 1 of this invention. FIG. 7 is a diagram schematically showing a layout of first metal wiring in the pixel portion shown in FIG. 6. FIG. 7 is a diagram schematically showing a wiring layout of a second metal wiring layer of the pixel shown in FIG. 6. FIG. 7 is a diagram schematically showing a wiring layout of a third metal wiring layer of the pixel shown in FIG. 6. FIG. 11 schematically shows a wiring layout of a third metal wiring layer according to the first embodiment of the present invention. It is a figure explaining the wiring layout of the imaging device according to Embodiment 1 of this invention in detail. It is a figure which shows the planar layout of the pixel before 1st metal wiring formation of the imaging device according to Embodiment 1 of this invention. FIG. 13 is a diagram schematically showing a cross-sectional structure taken along line L13-L13 shown in FIG. It is a figure which shows roughly the wiring layout of the pixel after 1st metal wiring formation. FIG. 15 schematically shows a cross-sectional structure taken along line L15-L15 shown in FIG. It is a figure which shows roughly the wiring layout after 1 via formation of the pixel apparatus of the imaging device according to Embodiment 1 of this invention. FIG. 17 schematically shows a cross-sectional structure taken along line L17-L17 shown in FIG. It is a figure which shows roughly the wiring layout after the 2nd metal wiring formation of the pixel of the imaging device according to Embodiment 1 of this invention. It is a figure which shows roughly the cross-sectional structure along line L19-L19 shown in FIG. FIG. 19 is a diagram schematically showing a cross-sectional structure along a line L20-L20 shown in FIG. It is a figure which shows roughly the cross-section of the pixel of the modification 1 of Embodiment 1 of this invention. It is a figure which shows the electrical equivalent circuit of the pixel of the modification 2 of Embodiment 1 of this invention.

[Embodiment 1]
FIG. 1 schematically shows an overall configuration of an imaging apparatus according to the first embodiment of the present invention. In FIG. 1, the imaging apparatus includes a pixel array ARY in which a plurality of imaging units PDU each having two pixel portions (P) are arranged, and a horizontal scanning circuit 22 that controls accumulation and readout of pixel data of the imaging unit PDU. And a vertical scanning + reading control circuit 24 for transmitting an output signal from the image pickup unit PDU and transferring a pixel signal to the outside of the image pickup apparatus, and a constant current source 20 for controlling a voltage level of read contents at the time of data reading.

  In the pixel array ARY, the imaging unit PDU is composed of two adjacent pixel portions (P) arranged in the vertical direction (first direction). The arrangement relationship between the imaging units PDUs adjacent in the horizontal direction is different from each other. That is, in FIG. 1, the imaging unit PDUs are arranged in a staggered manner so that the positions of the imaging unit PDUs adjacent in the horizontal direction are shifted by one pixel unit. With this pixel arrangement, an output difference is suppressed due to a characteristic difference between layout patterns of adjacent imaging units PDUs. That is, it is difficult for a large difference in output to occur when the intensity of incident light is the same, and uncomfortable feelings to human eyes can be reduced.

  The horizontal scanning circuit 22 outputs a transfer control signal tx, a reset control signal rst, and a control voltage Vref. In FIG. 1, the control signals tx (m−1) −tx (m + 1) and rst (m−1) to rst (m + 1) in the (m−1) th to (m + 1) th rows (m is a natural number of 2 or more). ), A signal line supplying control voltage Vref (m−1) to Vref (m + 1), and a read line transmitting the output of internal read voltage Vout (n) to Vout (n + 2) are shown as an example.

  In the following description, the pixel portion of x rows and y columns is expressed as P (x, y). Hereinafter, the pixel portions P (m−1, n), P (m, n), P (m + 1, n), P (m, n + 1), and P (m + 1, n + 1) will be described in focus. Pixel units P (m−1, n) and P (m, n) constitute one imaging unit PDU, and pixel units P (m, n + 1) and P (m + 1, n + 1) constitute one imaging unit PDU. To do.

  The pixel portion P (m−1, n) receives the transfer control signal ts (m−1), the reset control signal rst (m−1) and the control voltage Vref (m−1) at the control terminals 7, 8 and 9. Receive each. The pixel portion P (m, n) receives the transfer control signal tx (m) and the control voltage Vref (m) at the control terminals 10 and 11, respectively. An output voltage Vout (m) is output from the output terminal 12 of the imaging unit to the readout line. In one imaging unit PDU, pixel data from the two pixel portions P (m−1, n) and P (m, n) are sequentially output from the common output terminal 12.

  The pixel portion P (m + 1, n) receives the transfer control signal tx (m + 1), the reset control signal rst (m + 1), and the control voltage Vref (m + 2) at each of the control terminals 7-9. The pixel portion P (m, n + 1) receives the transfer control signal tx (m), the reset control signal rst (m), and the control voltage Vref (m) at each of the control terminals 7-9. The pixel portion P (m + 1, n + 1) receives the transfer control signal tx (m + 1) and the control voltage Vref (m + 1) at the control terminals 10 and 11, respectively. An output voltage Vout (m + 1) is output from the output terminal 12 to the readout line. The transfer control signal tx, the reset control signal res, and the control voltage Vref are supplied in a similar manner to the other pixel portions arranged in the pixel array ARY. That is, in the row of the imaging unit PDU, the upper pixel portion and the lower pixel portion are alternately arranged to receive the same control signal and control voltage.

  In the pixel array ARY, local power supply lines 30a to 30d extending in the vertical direction are arranged corresponding to the columns of the pixel portions, and second local power supply lines 32a to 32c are corresponding to the rows of the pixel portions. Be placed. These local power supply lines are interconnected at a portion not shown, and are arranged in a mesh shape in the pixel array ARY. Local power supply lines 30a-30d and 32a-32e may be power supply lines that transmit high-side power supply voltage VDD, or power supply lines that transmit low-side power supply voltage GND. The power supply arrangement for the pixel portion (P) will be described in detail later.

  The vertical scanning + reading control circuit 24 sequentially transfers the read pixel signals in a predetermined sequence. The constant current driven by the constant current source 20 prevents the pixel signal output from the output terminal 12 to the readout line from exceeding a predetermined maximum value and causing local halation in the image.

  FIG. 2 is a diagram illustrating an example of the configuration of the imaging unit PDU illustrated in FIG. FIG. 2 representatively shows the configuration of two imaging units PDUa and PDUb in adjacent rows. In FIG. 2, the imaging unit PDUa includes pixel portions P (m-1, n) and P (m, n), and the imaging unit PDUb includes pixel portions P (m, n + 1) and P (m + 1, n + 1). Including.

  Each of the upper pixel portions P (m−1, n) and P (m, n + 1) of the imaging units PDUa and PDUb is accumulated in a photodiode (photoelectric conversion element) 1 having a photoelectric conversion function and the photodiode 1. A transfer transistor 2 that transmits the optical carrier to the floating diffusion FD, and a reset transistor 3 that resets the potential of the floating diffusion FD.

  Each of the lower pixel portions P (m, n) and P (m + 1, n + 1) of the imaging units PDUa and PDUb is a floating diffusion for the photodiode 4 having a photoelectric conversion function and the optical carrier accumulated in the photodiode 4. It includes a transfer transistor 5 for transferring to the FD and an amplifying transistor 6 for amplifying and outputting the signal transmitted to the floating diffusion FD. In each of the imaging units PDUa and PDUb, the upper pixel portions P (m−1, n) and P (m, n + 1) are respectively connected to the lower pixel portions P (m, n) and P (m + 1, n + 1). Are electrically coupled to each other by a floating diffusion FD.

  In the pixel portion P (m−1, n) of the imaging unit PDUa, the photodiode 1 and the transfer transistor 2 are connected in series between a fixed voltage (low-side power supply voltage) GND and a floating diffusion FD. The gate of the transfer transistor 2 is electrically connected to the control terminal 7 to which the control signal tx (m−1) is input. The reset transistor 3 is connected between a floating diffusion FD and a control terminal 9 to which a control voltage Vref (m−1) is applied, and a gate thereof has a control terminal 8 to which a reset control signal rst (m−1) is input. And electrically connected.

  In the pixel portion (m, n), the photodiode 4 and the transfer transistor 5 are connected in series between the fixed voltage GND and the floating diffusion FD. The gate of the transfer transistor 5 is electrically connected to the control terminal 10 to which the control signal tx (m) is input. The amplification transistor 6 is connected between a control terminal 11 to which a control voltage Vref (m) is applied and an output terminal 12 that outputs an amplification signal Vout (n), and its gate is electrically connected to the floating diffusion FD. The

  In the pixel portion P (m, n + 1) of the imaging unit PDUb, the photodiode 1 and the transfer transistor 2 are connected in series between the fixed voltage GND and the floating diffusion FD. The gate of the transfer transistor 2 receives a control signal tx (m) via the control terminal 7. The reset transistor 3 is connected between the floating diffusion FD and the control terminal 9 to which the control voltage Vref (m) is applied, and receives a reset control signal rst (m) via the control terminal 8 at its gate.

  In the pixel portion (m + 1, n + 1), the photodiode 4 and the transfer transistor 5 are connected in series between the fixed voltage GND and the floating diffusion FD. The gate of the transfer transistor 5 receives the transfer control signal tx (m + 1) via the control terminal 10. The amplification transistor 6 is connected between a control terminal 11 to which a control voltage Vref (m) is applied and an output terminal 12 that outputs an amplification signal Vout (n + 1), and its gate is electrically connected to the floating diffusion FD. The

  The pixel portion P (m + 1, n) aligned in the horizontal direction with the pixel portion P (m + 1, n + 1) is included in the imaging unit PDUc, and is connected to the control signals tx (m + 1), rst ( m + 1) and control voltage Vref (m + 1). The internal configuration of the pixel unit P (m + 1, n) is the same as the configuration of the pixel units P (m−1, n) and P (m, n + 1) above the imaging units PDUa and PDUb.

  As shown in FIG. 2, two pixel portions are provided in the imaging unit PDU, and the reset transistors 3 and 6 are shared by these two pixel portions. Thereby, the number of components of the pixel unit is reduced, and the layout area of the imaging unit PDU is reduced.

  FIG. 3 is a timing chart for explaining a series of reading operations of the pixel portion P (m, n) and the pixel portion P (m, n + 1) arranged on the pixel array ARY shown in FIGS. Hereinafter, the data read operation of the pixel array shown in FIGS. 1 and 2 will be described with reference to FIG. In the following operation, the horizontal scanning circuit 22 performs a shift operation according to a clock signal (not shown) to generate a control signal for each pixel row.

  At time t10, the control voltage Vref (m−1) is set to the “H” level (logic high level). Reset control signals rst (m−1) and rst (m) are maintained at H level, and transfer control signal tx (m) is set at H level.

  In this state, the reset transistor 3 is in the on state in the pixel portion P (m−1, n), and the control voltage Vref (m−1) at the H level is transmitted to the floating diffusion FD. The transfer transistor 2 is in an off state, and the photodiode 1 and the floating diffusion FD are separated.

  On the other hand, in the pixel portion P (m, n), the transfer transistor 5 is turned on, the H level voltage on the floating diffusion FD is transmitted to the cathode of the photodiode 4, and the photo of the pixel portion P (m, n) is transmitted. The diode 4 is reset.

  Further, the control voltage Vref (m) is at the H level, the control signal rst (m) is at the H level, the transfer control signal tx (m) is at the H level, and the reset transistor 3 in the pixel portion P (m, n + 1). Is in the on state, and the transfer transistor 2 is in the on state. Therefore, the H level control voltage Vref (m) applied to the control terminal 9 is transmitted to the cathode of the photodiode 1 and the photodiode 1 is reset.

  At time t11, the control signal tx (m) and the control voltage Vref (m) for the pixel portions P (m, n) and P (m, n + 1) are both at the L level, and the transfer transistor 2 is in the off state. The reset control signals rst (m) and rst (m−1) are at the H level, and the floating diffusion FD is reset to the L level in the pixel portions P (m, n) and P (m, n + 1). Pixel data is stored by the photodiodes 4 and 1.

  At time t12, transfer control voltage Vref (m−1) is set to H level, and reset control signal rst (m−1) is maintained at H level. As a result, in the pixel portion P (m, n), the control voltage Vref (m−1) at the H level is transferred to the floating diffusion FD, and the floating diffusion FD is reset (FD reset). Accordingly, amplification transistor 6 is turned on, and the voltage level of read voltage Vout (n) rises according to H level control voltage Vref (m).

  Similarly, the control voltage Vref (m) is set to H level, and the reset control signal rst (m) is maintained at H level. Accordingly, the reset transistor 3 is turned on in the pixel portion P (m, n + 1), and the corresponding floating diffusion FD is reset by the control voltage Vref (m) at the H level.

  At time t13, reset control signal rst (m) -rst (m + 1) is set to L level, and control voltages Vref (m) and Vref (m + 1) are set to H level. Accordingly, the reset transistor 3 is turned off in the pixel portions P (m−1, n), P (m, n + 1), and P (m + 1, n). As a result, the gate voltage of the amplification transistor 6 (the voltage of the corresponding floating diffusion FD) for outputting the readout signal of the pixel portion P (m, n + 1) arranged in the pixel portion P (m + 1, n + 1) is at the H level. Further, the drain voltage is set to H level by the control voltage Vref (m + 1). Therefore, output voltage Vr (m, n + 1) corresponding to the reset potential (H level) of floating diffusion FD is output from the corresponding output terminal 12 to the read line that transmits output voltage Vout (n + 1).

  Similarly, the drain potential of the amplification transistor 6 in the pixel portion P (m, n) is set to the H level according to the control voltage Vref (m). An output voltage Vr (m, n) corresponding to the reset potential of the corresponding floating diffusion FD is output from the corresponding output terminal 12 to the readout line that transmits the output voltage Vout (n). With these series of operations, preparation for the read operation (precharge of the read line) of the pixel portions P (m, n) and P (m, n + 1) is completed.

  At time t14, the transfer control signal tx (m) is set to the H level. Accordingly, both the transfer transistors 5 and 2 are turned on in the pixel portion P (m, n) and the pixel portion P (m, n + 1), and the charges accumulated in the cathodes of the corresponding photodiodes 4 and 1 correspond to each other. To the floating diffusion FD. Accordingly, the potential of the floating diffusion FD of the pixel part P (m, n) and the pixel part P (m, n + 1) is lowered.

  At time t15, the voltages Vs (m, n) and Vs (m, n + 1) corresponding to the voltage of the floating diffusion FD after charge transfer are output via the amplifier transistor 6 to the output voltages Vout (n) and Vout (n + 1). As a result, the read line of the corresponding column is output.

  Further, a data signal proportional to the amount of charge accumulated in the photodiode 4 of the pixel portion P (m, n) by detecting the voltage difference Vr (m, n) −Vs (m, n) in the subsequent circuit. Can be detected. Similarly, by detecting the voltage difference Vr (m, n + 1) −Vs (m, n + 1), a data signal proportional to the amount of charge accumulated in the photodiode 1 of the pixel portion P (m, n + 1) is detected. be able to.

  The pixel accumulation period for accumulating photoelectric charges is a period from time t10 to time t14 in the pixel portions P (m, n) and P (m, n + 1). By applying the above-described row unit operation to all rows while shifting by a constant interval, it is possible to detect a data signal as pixel information.

  FIG. 4 schematically shows a layout of wiring for transmitting the operating voltage of the imaging apparatus according to the first embodiment of the present invention. In FIG. 4, in the pixel array ARY, pixel portions (photodiodes PD) are arranged in a matrix and aligned in the horizontal direction and the vertical direction. Here, the pixel portion includes a photodiode (PD) for photoelectric conversion and a transistor for internal reset and readout. FIG. 4 shows the arrangement of the photodiode PD in order to simplify the drawing.

  From the power supplies 40a and 40b arranged on both sides of the pixel array ARY in the vertical direction, for example, the power line 30 of the first metal wiring is arranged linearly corresponding to each pixel column. Here, the pixel column is composed of pixel portions (photodiodes PD) arranged in the vertical direction, and the pixel row is composed of photodiodes PD arranged in the horizontal direction.

  The power supply wiring 30 includes a branch portion 34 extending in the horizontal direction at the boundary portion of the pixel row. Each branch portion is coupled to a power supply wiring 30 in an adjacent column by a jumper wiring 36 formed of an upper layer, for example, a second metal wiring. Accordingly, in the horizontal direction, for example, the adjacent power supply wiring 30 is interconnected in the horizontal direction by the branch portion 34 formed of the first metal wiring and the jumper wiring 36 formed of the second metal wiring, and the horizontal protrusion 34 and the jumper wiring 36 form the power supply lines 32a-32e shown in FIG. The power supply wiring 30 may transmit either the high-side power supply voltage (VDD) or the low-side power supply voltage (GND).

  As shown in FIG. 4, the power supply lines can be strengthened by arranging the power supply lines in a mesh shape corresponding to the pixel portions PD of the pixel array ARY. That is, even when a local defect exists in the power supply wiring, the operating voltage can be supplied from the surrounding power supply wiring, and the influence of the defect can be suppressed. Thereby, a predetermined level of voltage can be stably supplied to each pixel unit. In addition, the power supply wiring is arranged so as to surround the photodiode for each pixel, and it can also have a function of a light shielding wall for preventing incident light from entering the adjacent pixel portion. Crosstalk between adjacent pixels can be suppressed without providing a wall structure. Further, by using the jumper wiring, even when the control signal line or the like is formed in the same wiring layer as the power wiring 30, the adjacent power wiring can be connected without causing a wiring collision.

  In addition, in the power supplies 40a and 40b, a filter or the like that removes noise or the like of external voltage is disposed to generate a stable internal voltage. When the voltage transmitted through power supply line 30 is an internal voltage having a level different from that of an external voltage, an internal voltage generation circuit for generating a voltage of a required voltage level in these power supplies 40a and 40b is arranged. . The power supplies 40a and 40b may be configured by a wide main power supply line (metal wiring) that receives an external voltage directly via a terminal.

  FIG. 5 is a diagram showing an example of a specific arrangement of the power supply wiring 30, the branching section 34, and the jumper wiring 36 in the array unit ARY shown in FIG. In FIG. 5, in the boundary region along the horizontal direction of the pixel portion (photodiode PD), the power supply wiring 30 and the output wiring (readout line) 42 are continuously extended in the vertical direction in parallel and adjacent to each other. Present. The power supply wiring 30 and the output line 42 are composed of, for example, a first metal wiring and are wiring of the same metal wiring layer. Therefore, the branch portion of the power supply wiring 30 cannot be disposed so as to extend beyond the output wiring 42 with respect to the adjacent power supply wiring. Therefore, as shown in FIG. 5, when the output wiring 42 is arranged between the power supply wiring 30 and the pixel portion (photodiode PD), the output line is connected between the pixel portion (photodiode PD) and the power supply wiring 30. A branch portion 34 </ b> A is formed for the power supply wiring 30 in a region where 42 is not disposed. The branch portion 34A is disposed in a boundary region in the vertical direction of the pixel portion (photodiode PD). The branch portion 34A is electrically connected to a jumper wiring 36A formed in the second metal wiring layer through a contact 40b. The jumper wiring 36A is coupled to the power supply wiring 30 in the adjacent column via a contact 44a at the other end.

  As described above, the jumper wiring 36 </ b> A is, for example, a second metal wiring, and is an upper layer wiring of the output wiring 42. Therefore, the branching portion 34A of the power supply wiring 30 (30b) can be coupled to the power supply wiring 30 (30a) adjacent in the horizontal direction without affecting the arrangement of the output wiring 42. Therefore, the region where the branch portion 34A is arranged is provided in consideration of the transistor arrangement region and the wiring arrangement region in the pixel portion. By forming the jumper wiring 36A in a key shape, the adjacent power supply line 30 (30a) and the jumper wiring 46A can be electrically connected to each other in an appropriate region without affecting the wiring region of the transistor in the pixel portion. Can be connected to.

  It should be noted that whether the branch portion 34A extends from right to left or from left to right in the horizontal direction of FIG. 5 can be appropriately determined according to the arrangement of the output wiring 42 and the wiring of the peripheral transistors. Good.

  The power supply wiring 30 is, for example, a wiring that transmits the ground voltage GND, and is connected to the substrate region and the anode region of the photodiode (1, 4; PD), and the substrate region (back gate) of the transfer transistor, the reset transistor, and the amplification transistor. A voltage of a predetermined level can be accurately supplied. The output wiring 42 is a readout line and transfers the output voltage Vout.

  6 schematically shows a cross-sectional structure taken along line L6-L6 shown in FIG. In FIG. 6, the pixel portion PX includes a photodiode PD and a transfer transistor XTR (2, 5). The photodiode PD includes a charge storage impurity region 52 formed on the surface of the P-type semiconductor substrate region 50 and an antireflection film 56 formed on the impurity region 52. When the impurity region 52 is irradiated with light, electron / hole pairs are generated. The generated electrons are accumulated in the impurity region 52, and the holes are emitted to the substrate region 50 biased to the ground voltage (low-side power supply voltage). As a result, an amount of electric charge corresponding to the energy of the incident light is accumulated in the impurity region 52.

  An N-type impurity region 58 is formed on the surface of semiconductor substrate region 50 so as to face charge storage impurity region 52 with respect to gate electrode wiring 60. A P-type impurity region 62 is formed adjacent to the N-type impurity region 58. Transfer transistor XTR (transfer transistors 2 and 5 in FIG. 2) is formed by gate electrode interconnection 60, impurity region 58, and impurity region 52.

  The periphery of the pixel portion PX is surrounded by an element isolation region, and adjacent pixel portions are separated from each other by the element isolation region.

  In the first metal wiring layer (M1), an output signal wiring 64 transmitting the output voltage Vout and a ground wiring 66 transmitting the ground voltage GND are arranged. First metal ground wiring 66 corresponds to power supply wiring 30 shown in FIG. 5 and is coupled to impurity region 62 through plug 67. By this first metal ground wiring 66, ground voltage GND is transmitted to substrate region 50 through P-type impurity region 62. As a result, the ground voltage GND is applied to the back gate of each transistor formed in the pixel portion, and the ground voltage GND is applied to the anode of the photodiode PD.

  In the first metal wiring layer M1, the ground wiring is disposed adjacent to the output signal wiring 64. However, in FIG. 6, the ground wiring adjacent to the output signal wiring is not shown in order to simplify the drawing. Not shown.

  In the second metal wiring layer (M2), a second metal control wiring 70 constituting a control wiring for transmitting a control signal and a second metal ground wiring 68 for transmitting a ground voltage GND are arranged. The second metal control wiring 70 is a wiring for transmitting a transfer control signal tx and the like, as will be described in detail later. The second metal ground wiring 68 corresponds to the jumper wiring 36A shown in FIG.

  In the third metal wiring layer (M3), third metal power supply wirings 72a and 72b for transmitting the high-side power supply voltage Vdd are provided. The third metal power supply lines 72 and 72b are configured in a mesh shape so as to surround the photodiode PD in each pixel region, and define the path of incident light. The effect of the arrangement of the third metal power supply wirings 72a and 72b will be described in detail later. Here, the incident light is reflected by the power supply wiring and the lower layer wiring as shown by arrows in the figure, and the antireflection film. It is transferred to the impurity region 52 through 56. Therefore, it is possible to prevent the incident light from entering the adjacent pixel portion and to suppress the crosstalk phenomenon. In this case, the power supply wirings 72a and 72b and other control signal wirings are merely used, and it is not necessary to provide a special oblique light protection wall, and the structure of the pixel portion is simplified.

  In order to effectively suppress this intrusion light, the wiring interval is gradually increased slightly toward the lower metal layer toward the third metal wiring layer M3, the second metal wiring layer M2, and the first metal wiring layer M1. . In FIG. 6, the positional relationship between these wirings is indicated by a broken line extending downward from each wiring end. This wiring interval may be the same in each wiring layer, but in that case, the amount of incident light may be reduced, and the lower layer wiring is made wider so that incident oblique light is reflected as much as possible to be incident on the photodiode. .

  FIG. 7 is a diagram showing a planar layout of the first metal wiring of the pixel portion shown in FIG. 5 together with the photodiode PD. In FIG. 7, the sectional lines L6-L6 shown in FIG. 5 are also shown. In FIG. 7, the first metal ground wiring 66 is disposed so as to surround the light incident region of the photodiode PD in a U-shape.

  A first metal output signal wiring 64 is disposed in an open portion of the first metal ground wiring 66 surrounding three sides of the light incident region of the photodiode PD. A first metal ground wiring 30 is disposed adjacent to the first metal output signal wiring 64.

  Therefore, the light incident area of the photodiode PD is surrounded by the first metal ground wiring 66 and the first metal output signal wiring 64, and the intrusion of incident light into the adjacent pixel portion is blocked.

  The U-shaped first metal ground wiring 66 is provided for the photodiode PD. Therefore, as shown in FIG. 5, the ground wiring 30 has a branch portion 34A in the boundary region of each pixel row. It becomes composition.

  FIG. 8 schematically shows a wiring layout of the second metal wiring layer in the pixel arrangement shown in FIG. FIG. 8 also shows the arrangement of the photodiode PD and the cross-sectional lines L6-L6.

  In the second metal wiring layer M2, the second metal control wires 76a and 76b constituting the control line are arranged in parallel, respectively. The second metal control wiring 76b has a protruding portion 70 extending along the photodiode PD, and the protruding portion 70 corresponds to the second metal control wiring 70 shown in FIG. The protruding second metal control wiring 70 controls the on / off state of the transfer transistor that transfers the charge accumulated in the photodiode PD.

  Between these second metal control wires 76a and 76b, key-shaped second metal jumper wires 74a and 74b are arranged on both sides of the photodiode PD. These second metal jumper wirings 74a and 74b correspond to jumper line 36A shown in FIG. 5, and are electrically connected to the lower first metal power supply wiring via contacts 44a and 44b.

  The arrangement positions of these jumper wirings 74a and 74b are affected by the arrangement of read and transfer transistors formed therebelow. The second metal jumper wirings 74a and 74b are arranged without adversely affecting the arrangement of the transistors in the pixel portion.

  FIG. 9 is a diagram schematically showing the wiring arrangement of the third metal wiring layer M3 of the pixel array shown in FIG. 9 also shows the cross-sectional line L6-L6 shown in FIG.

  In FIG. 9, in the third metal wiring layer M3, the third metal power supply wiring 72 is disposed so as to surround the light incident region of the photodiode PD. The third metal wiring 72 corresponds to the third metal power supply wirings 72a and 72b shown in FIG. By disposing the third metal power supply wiring 72 so as to surround the light incident region of the photodiode PD, as shown in FIG. 6, even if incident light enters in an oblique direction, it is reflected by this wiring and is reflected in the photodiode PD. It is possible to reach the light receiving region, and it is possible to suppress the obliquely incident light from entering the adjacent pixels. The power supply wiring, the output signal wiring, and the control signal wiring are simply arranged, and no special light shielding structure is required.

  FIG. 10 is a diagram schematically showing an example of the arrangement of the third metal power supply wiring in the entire pixel array. In FIG. 10, a wide main power supply wiring 82 for supplying the power supply voltage Vdd from the power supply terminal 80 is arranged so as to surround the outer periphery of the photodiode PD array. The external main power supply wiring 82 is constituted by a third metal wiring as an example. Second local metal power supply wires 84 and 86 are arranged corresponding to each row and column of photodiode PD so as to extend from third metal main power supply wire 82 in the vertical and horizontal directions. The rectangular wiring surrounded by the third metal local power wirings 84 and 86 corresponds to the third metal power wiring 72 shown in FIG. Therefore, in this case, the power supply wiring of the main power supply line 82 can be strengthened, and the light receiving area of each photodiode PD can be defined, so that light incident from an oblique direction is prevented from entering the adjacent pixels. And the crosstalk phenomenon can be reliably prevented.

  FIG. 11 is a diagram more specifically showing the wiring layout of the imaging apparatus according to the first embodiment of the present invention. FIG. 11 representatively shows the configuration of the pixel portion arranged in 4 rows and 4 columns, and shows the arrangement of the control signal lines for the pixels arranged in 2 rows together with the arrangement of the transistors of the pixels. However, in FIG. 11, a reference number is assigned to the selected pixel portion in order to prevent the drawing from becoming complicated.

  In FIG. 11, the pixel portion includes a photodiode PD, a reset transistor RTR and a selection (amplification) transistor STR arranged in a region adjacent in the vertical direction to the formation region of the photodiode PD, and a horizontal direction in the photodiode PD formation region. Includes a transfer transistor XTR disposed in a region in contact with.

  Reset transistor RTR and select transistor STR are formed on active region 88 and each include gate electrode wirings 89a and 89b receiving a corresponding control signal. Transfer transistor XTR includes a gate electrode wiring 89c that receives a corresponding transfer control signal. Floating diffusion wiring that interconnects the transfer transistors XTR of the two pixel portions that constitute the imaging unit is not shown in order to simplify the drawing.

  Corresponding to each column of the pixel portion, a first metal ground wiring 30a and first metal output signal wirings 42a to 42c formed in the first metal wiring layer are arranged. The first metal ground wirings 30a-30c supply a substrate bias voltage (ground voltage GND) to the substrate region via an active region 90 disposed corresponding to the lower portion thereof.

  First metal ground wirings 30a-30c include branch portions 91b and 91a corresponding to the respective pixel portions. The branch part 90b extends in the horizontal direction to the gate electrode of the reset transistor (RTR), and the branch part 90a extends in the vertical direction to the gate electrode (89a) of the reset transistor (RTR). In FIG. 11, branching portions 91a and 91b are shown provided for first metal ground wirings 30b and 30c. However, the branch portions 91a and 91b are similarly provided for the first metal ground wiring 30a. The branch portion 91a is coupled to a jumper wiring 74 having a key shape through a contact 44b. The jumper wiring 74 is coupled to the first metal ground wiring in the adjacent column through the contact 44a. In FIG. 11, the first metal ground wiring 30b is connected to the first metal ground wiring 30a in the adjacent column via the branch portions 91b and 91a and the jumper line 74. Similarly, the first metal ground wiring 30c is adjacent to the first metal ground wiring 30a. It is shown that it is connected to the first metal ground wiring 30b in the column via a branch portion and a jumper wiring.

  Control signal lines 95x, 95s, and 95r extending in the horizontal direction are arranged in the boundary region of each pixel row. FIG. 11 representatively shows control signal lines arranged for the pixel portions arranged in two rows.

  The control signal line 95x is a signal line for transferring a transfer control signal for controlling on / off of the transfer transistor XTR, and is coupled to the gate electrode line 89c of the transfer transistor XTR by the branch portion 96. The control signal wiring 95s is a signal line for transferring a control signal for controlling the conduction of the selection transistor STR, and is coupled to the gate electrode wiring 89b of the selection transistor STR (a contact is not shown). The control signal wiring 95r is a signal line for transferring a reset control signal for controlling the reset transistor RTR, and is electrically connected to the gate electrode wiring 89a of the reset transistor RTR.

  A branch portion 97 is formed from the control signal wiring 95r to the upper portion of the gate electrode wiring 89c in the downward direction. The branch portion 97 is not connected to the gate electrode wiring 89c. It is provided to surround the light incident area of the photodiode PD by the control signal wiring.

  In FIG. 11, the upper control signal line 95r and the lower control signal line 95x correspond to the control signal lines 75a and 76b shown in FIG. 8, respectively. These control signal wirings 95x, 95s and 95r are each formed by the wiring of the second metal wiring layer M2. The jumper wiring 74 is also a second metal wiring. Therefore, the arrangement area of the jumper wiring 74 is set so as not to collide with the arrangement area of the control signal lines 95x, 95s, and 95r, and not to overlap with the opening of the photodiode PD as much as possible. Here, the branch portions 91a and 91b of the first metal ground wiring 40 are also arranged so as not to adversely affect the electrical connection (contact) between the control signal lines 95x, 95s and 95r and the gate electrode wiring of the corresponding transistor. There is a need.

  In FIG. 11, the signal line for transmitting the control voltage Vref is not shown, but similarly, the signal line for transmitting the control voltage Vref is arranged in the wiring of the second metal wiring layer.

  On this upper portion, the power supply wiring 100 is arranged in a mesh shape by using the wiring of the third metal wiring layer (M3) in the portion excluding the opening of the photodiode PD. In FIG. 11, the mesh-like third metal power supply wiring 100 having openings for the photodiodes PD arranged in two rows is indicated by hatching in order to simplify the drawing.

  As shown in FIG. 11, ground voltage GND is formed by using the wiring of the first metal wiring layer in the lower layer in order to control the voltage of the substrate region and the anode electrode of the photodiode. Wiring for transmitting Vdd is formed in a mesh shape to define the opening region of the photodiode PD. Further, the power supply voltage Vdd is stably supplied. Further, the periphery of the photodiode PD is surrounded by the first metal wiring, the second metal wiring, and the third metal wiring, and these peripheral wirings constitute an oblique light protection wall, thereby preventing the crosstalk phenomenon of incident light. Suppress.

  Note that the power supply voltage Vdd is not used in the configuration of the pixel portion shown in FIG. The power supply voltage Vdd may be used in peripheral circuits such as a horizontal scanning circuit and a vertical scanning + reading control circuit. Further, as will be described later, when the power supply voltage Vdd is used as in the configuration of the pixel portion of another embodiment, the transistor of each pixel portion is formed using the power supply wiring 100 of the upper third metal wiring layer. Supply the necessary voltage.

  12 to 16 are diagrams schematically showing a manufacturing process of the wiring structure of the pixel array shown in FIG. Hereinafter, the manufacturing process of the wiring structure shown in FIG. 11 will be described with reference to FIGS.

  FIG. 12 is a diagram schematically showing a planar layout of the pixel portion in the starting manufacturing process used for explaining the manufacturing process of the imaging device. In FIG. 12, a photodiode PD is formed, and an impurity region (52) for charge accumulation is formed. This charge accumulation impurity region (52) is not clearly shown in FIG. A gate electrode wiring 89c is formed so as to partially overlap the formation region of the photodiode PD and adjacent to the impurity region (52) for charge storage. An impurity region 102 for charge reading is formed in a self-aligned manner with respect to the gate electrode wiring 89c. Thereafter, contact 103 for transmitting a control signal to gate electrode 89c is formed. These are formed using normal processes such as an impurity implantation process, a photomechanical etching process, and generation and patterning of gate wiring.

  FIG. 13 schematically shows a cross-sectional structure along line L13-L13 shown in FIG. In FIG. 13, an impurity region 102 is formed on the surface of the semiconductor substrate region 50. An antireflection film 56 is formed on the impurity region that constitutes the anode of the photodiode on the surface of the substrate region 50. Further, an N-type impurity region 52 is formed on the surface of the semiconductor substrate region 50 below the antireflection film 56. N-type impurity region 52 corresponds to the cathode region of photodiode PD. The region of the photodiode PD corresponds to a region where the antireflection film 56 is formed. A gate electrode wiring 89 c is formed on the substrate region between the formation region of the photodiode PD and the impurity region 102. The gate electrode wiring 89c corresponds to the gate electrode wiring 60 shown in FIG. In the portion shown in FIG. 13, the contact 103 shown in FIG. 12 is not shown.

  FIG. 14 is a diagram schematically showing a planar layout of the pixel portion after the first metal wiring is formed following the manufacturing process shown in FIG. In FIG. 14, first metal ground wirings 30A and 30B are arranged outside the formation region of the photodiode PD, and continuously extend in the vertical direction between the first metal ground wiring 30A and the photodiode PD formation region. A first metal output signal wiring 42 is provided. First metal ground wiring 30B is disposed adjacent to and above active region 102, and has branch portions 91b and 91a. The branch portion 91a extends almost to the vicinity of the formation region of the photodiode PD.

  FIG. 15 schematically shows a sectional structure taken along line L15-L15 shown in FIG. 15, parts corresponding to those in the cross-sectional view shown in FIG. 13 are denoted by the same reference numerals, and detailed description thereof is omitted. In first metal wiring layer M1, first metal ground wirings 30A and 30B transmitting ground voltage GND are arranged on the element isolation film region outside the photodiode formation region. Similarly, a first metal output signal line 42 that transmits the output voltage Vout is disposed on the element isolation film adjacent to the first metal ground line 30A.

  FIG. 16 is a diagram schematically showing a planar layout of the main part after the formation of the first via in the step subsequent to the manufacturing step shown in FIG. In FIG. 16, the first via 104a is formed so as to overlap the contact 102 of the gate electrode wiring 89c, and the first via 104b is disposed at the joint between the branch portions 91b and 91a. The first via 104c for connecting the jumper wiring is also provided in the first metal ground wiring 30A.

  The first vias 104a-104c are provided for electrical connection with the upper second metal wiring. Aluminum wiring is assumed as wiring. When copper wiring is used as the metal wiring, the first via formation process is not provided, and the second metal wiring and the first via may be simultaneously formed in parallel by a damascene process.

  FIG. 17 schematically shows a sectional structure taken along line L17-L17 shown in FIG. In FIG. 17, parts corresponding to those shown in FIG. 15 are given the same reference numerals, and detailed descriptions thereof are omitted.

  In FIG. 17, a contact 103 is provided for the gate electrode wiring 89c, and a first via 104a is formed so as to be aligned with and electrically connected to the contact 103.

  FIG. 18 is a diagram schematically showing a planar layout of the pixel portion after the metal wiring arrangement of the second metal wiring layer after the manufacturing process of FIG. In FIG. 18, the same reference numerals are given to the portions corresponding to the components shown in FIG. 16, and detailed description thereof will be omitted.

  In FIG. 18, second metal control wires 95r and 95x for transmitting control signals are arranged. The second metal control wiring 95x is electrically connected to the gate electrode wiring 89c through the branch portion 96 through the first via 104a and the contact. On the other hand, the second metal control wiring 95r is also provided with a branching portion 97 extending in the direction of the gate electrode wiring 89c. These branch portions 97 and 96 surround the three sides of the formation region of the photodiode PD to form an oblique light reflection film (an oblique light protection wall).

  Further, the first metal ground wirings 30A and 30B are electrically connected to each other beyond the output signal wiring 42 by the first vias 104b and 104a and the jumper wiring 74 of the second metal wiring.

  In this second metal wiring layer, the formation region of the photodiode PD is surrounded by the second metal wiring on all sides, and a protective barrier (light-shielding film) that suppresses intrusion of light incident from an oblique direction into the adjacent pixel portion. Can be formed.

  FIG. 19 schematically shows a cross-sectional structure taken along line L19-L19 shown in FIG. 19, parts corresponding to the elements of the cross-sectional structure shown in FIG. 15 are given the same reference numerals, and detailed descriptions thereof are omitted. In the second metal wiring layer, a second metal jumper wiring 74 is disposed on the first metal ground wiring 30 </ b> A and the first metal output signal wiring 42. In the region of the cross-sectional structure shown in FIG. 19, the contact with respect to the gate electrode wiring 89c and the first via are not provided.

  By forming the jumper wiring 74 using the second metal wiring, the first metal ground wiring 30B and the first metal ground wiring 30A can be connected even when the first metal wirings 30A and 42 are disposed below. The first metal output wiring 42 can be electrically connected beyond the first metal output wiring 42.

  20 schematically shows a cross-sectional structure along line L20-L20 shown in FIG. In the cross-sectional structure shown in FIG. 20, the same reference numerals are assigned to the portions corresponding to the elements of the cross-sectional structure shown in FIG. 17, and the detailed description thereof is omitted. In the cross-sectional structure shown in FIG. 20, the second metal control wiring 96 is disposed on the first via 104a, and the second metal jumper wiring 74 is disposed on the first metal output signal wiring. . The first metal ground wirings 30A and 30B can be electrically connected by the jumper wiring 74 exceeding the first metal output signal wiring 42. Further, in the second metal wiring layer and the first metal wiring layer, as shown in FIG. 18, the wiring is arranged so as to surround the formation region of the photodiode PD, and reflects the light incident in the oblique direction. Irradiation can be performed on the antireflection film 56, and incident oblique light can be prevented from entering the adjacent pixel portion.

[Modification 1]
FIG. 21 schematically shows a sectional structure of a modification of the pixel portion according to the first embodiment of the present invention. The pixel portion shown in FIG. 21 is different in configuration from the pixel portion shown in FIG. 6 in the following points. That is, the first metal output signal wiring 64A and the first metal ground wiring 66A are arranged on both sides of the formation region of the photodiode PD so as to face the first metal wiring layer M1.

  In the second metal wiring layer M2, the second metal ground wiring 68A (jumper wiring 74) and the second metal control wiring 70A constituting the control line are arranged facing both sides of the photodiode formation region. In the third metal wiring layer M3, third metal power supply wirings 72A and 72B transmitting the power supply voltage Vdd are arranged on both sides of the photodiode formation region. The ground wirings 68A and 66A are interconnected by a jumper wiring in a region not shown. Third metal power supply lines 72A and 72B are arranged in a mesh shape so as to have an opening only in the photodiode formation region. The other components of the pixel portion shown in FIG. 21 are the same as the components shown in FIG. 6, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  The wirings arranged from the first metal wiring layer M1 to the third metal wiring layer M3 are arranged from the third metal wiring layer M3 to the first metal so that the cross section thereof has a cross-shaped shape 120 as shown by a broken line arrow. The wiring interval is increased toward the metal wiring layer M1. Therefore, the distance between the third metal power supply lines 72A and 72B is larger than the distance between the second metal ground line 68A and the second metal control line 70A, and the first metal output line 64A and the first metal ground line. It is made smaller than the interval between 66A.

  When the wiring is arranged so that the wiring interval is set in such a C-shaped cross-sectional shape or a trapezoidal cross-sectional shape 120, the incident light with a low incident angle out of the oblique incident light is surely ensured by the wiring. Can be reliably reflected, can be reliably prevented from entering the adjacent pixel portion, and the crosstalk phenomenon can be further suppressed.

[Modification 2]
FIG. 22 is a diagram showing an electrical equivalent circuit of the pixel portion PX according to a modification of the first embodiment of the present invention. 22 includes a transfer transistor 130 connected between the photodiode PD and the floating diffusion FD, a reset transistor 132 connected between the node receiving the power supply voltage Vdd and the floating diffusion FD, and a floating diffusion. An amplifying transistor 134 that amplifies the potential on the FD and a selection transistor 136 that outputs the voltage amplified by the amplifying transistor 134 as a read voltage Vout are included.

  These transistors 130, 132, 134, and 136 are N-channel MOS transistors (insulated gate field effect transistors), and receive a low-side power supply voltage (ground voltage) GND at their back gates (substrate regions). The transfer transistor 130 transfers the charge accumulated at the cathode of the photodiode PD to the floating diffusion FD in accordance with the transfer control signal Tx. The reset transistor 132 transmits the high-side power supply voltage (power supply voltage) Vdd to the floating diffusion FD according to the reset signal RST. The amplification transistor 134 receives the voltage of the floating diffusion FD at the gate, operates in a linear region (non-saturated region), and amplifies the signal voltage on the floating diffusion FD. The selection transistor 136 is turned on in accordance with the selection signal SEL, and transmits the signal amplified by the amplification transistor 134 onto the readout line as the output voltage Vout.

  In the configuration of the pixel portion PX shown in FIG. 22, the selection signal SEL gives the data read timing of the pixel portion PX, and the selection signal SEL is used as the control voltage of the pixel portion shown in FIGS. Thus, similarly, diffusion reset, charge accumulation, reference voltage output, and pixel data transfer can be executed.

  In the pixel unit PX shown in FIG. 22, the memory voltage Vdd is used as a pixel reset voltage instead of the control voltage Vref. Therefore, with respect to the configuration of the pixel portion PX as shown in FIG. 22, the ground voltage GND of the pixel is arranged in a mesh shape, and the power supply wiring for transmitting the power supply voltage Vdd is arranged in a mesh shape. High-side and low-side power supply voltages Vdd and GND can be stably supplied to PX.

  In the above description, the low-side power supply voltage (ground voltage) GND is transmitted through the first metal wiring, and the high-side power supply voltage (power supply voltage) Vdd is transmitted to the third metal wiring. This is because the ground voltage is transmitted to the substrate region. However, even when the high-side power supply voltage Vdd is transmitted by the first metal wiring and the low-side power supply voltage GND is transmitted by the third metal wiring, they are similarly arranged in a wiring mesh shape for transmitting the power supply voltages Vdd and GND. Thus, the high-side and low-side power supply voltages can be stably supplied, and the occurrence of the crosstalk phenomenon in each pixel portion can be suppressed (due to the light shielding effect).

  As described above, according to the first embodiment of the present invention, the power supply line for transmitting the operating voltage (high and low side power supply voltages) is formed in a mesh shape in the pixel portion. As a result, the operating voltage can be stably supplied, and the crosstalk phenomenon between adjacent pixels can be suppressed by the light shielding effect due to the mesh shape.

  In general, the present invention is applied to a CMOS image sensor so that an operating voltage can be stably supplied, a crosstalk phenomenon between adjacent pixels can be suppressed, and a high-quality image can be taken. An image sensor can be realized. By applying to a single-lens reflex camera, a compact digital camera, and a mobile phone camera equipped with such a CMOS image sensor, it is possible to reduce defects in the entire product due to the CMOS image sensor defect, and improve the product yield accordingly. be able to.

  ARY pixel array, 30a-30d, 32a-32e power supply wiring, PD photodiode, 34 branching section, 36 jumper wiring, 42 first metal output signal wiring, 46A second metal jumper wiring, 64 first metal output signal wiring, 66 First metal ground wiring, 68 Second metal ground wiring, 70 Second metal control signal wiring, 72a, 72b Third metal power wiring, 84, 86 Power wiring, 82 Main power wiring, 95x, 95s, 95r Control signal wiring, 42a-42c 1st metal control signal wiring, 100 3rd metal power supply wiring, 120 wiring arrangement cross-sectional shape.

Claims (4)

A plurality of pixel units arranged in a matrix, each of which converts received light signals into electrical signals, and a predetermined voltage is supplied to each pixel unit and arranged in a mesh shape so as to surround each pixel unit An imaging device comprising a voltage supply line to be operated. The voltage supply line is
It is arranged corresponding to the boundary area of the column of each pixel part and is arranged extending continuously in the column direction, and is arranged corresponding to the boundary area of each pixel row and is arranged along the corresponding pixel part. A plurality of power supply wirings having branch portions arranged extending in the direction;
2. A jumper wiring that is arranged corresponding to each of the branching portions and that is higher than the power supply wiring that electrically connects the corresponding branching portion and a power supply wiring arranged in a boundary region of an adjacent column. The imaging device described.   A second voltage supply wiring that is disposed above the voltage supply line and transmits a second voltage is provided, and the second voltage supply wiring has an opening in a region corresponding to the photoelectric conversion unit of each pixel unit. The imaging device according to claim 1, comprising wirings of the same wiring layer arranged in a mesh shape. Each of the pixels includes a photoelectric conversion element that converts the light reception signal into an electric signal, and a transfer unit that reads out the electric signal converted by the photoelectric conversion element according to a control signal,
A wiring for transferring the control signal is disposed under the voltage supply line,
2. The imaging device according to claim 1, wherein in the photoelectric conversion element portion, the voltage supply line and the wiring are arranged so that a lower portion of the cross-sectional structure has a taper shape in which a wiring interval is wider than an upper portion.

Images