JP2010272921A - High speed multiplexing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high speed multiplexing circuit which can improve output waveform quality at a time of high speed operation. <P>SOLUTION: The high speed multiplexing circuit is provided with: first transistors Q1P, Q1N, Q2P, Q2N which are installed for each data signal series (D1P, D1N), (D2P, D2N), and selectively output the input data signal series to a signal output terminal connected in common; second transistors Q3, Q4 which makes ON either one of a differential pair composed of the transistors Q1P, Q1N or a differential pair composed of the transistors Q2P, Q2N according to clock signals CK1, CK2; third transistors Q6, Q7 which become a current source flowing collector currents to the transistors Q1P, Q1N, Q2P, Q2N, Q3, Q4; and a capacitor C1 inserted between collectors of the third transistors Q6, Q7 and power source voltage VEE of emitter sides. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention provides a circuit configuration for improving output waveform quality during high-speed operation in a multiplexing circuit that converts a plurality of data signal sequences into a single data signal sequence by time division multiplexing.

  As an example of a high-speed multiplexing circuit, a circuit configuration shown in FIG. 3 is known. The circuit configuration of FIG. 3 is disclosed in Non-Patent Document 1. In FIG. 3, Q1P and Q1N are transistors that constitute a differential pair, Q2P and Q2N are transistors that also constitute a differential pair, Q3 and Q4 are transistors that constitute a differential switch, Q5 is a current source transistor, and R1P and R1N Is a load resistor, R2 is a resistor constituting a current source, VCC and VEE are power supply voltages, VCS is a bias voltage of the current source, D1P and D1N are differential input data signals, and D2P and D2N are different from D1P and D1N. Input data signals, QP and QN are differential output signals after time division multiplexing, and CK1 and CK2 are clock signals of the differential switch. The resistance values of the resistors R1P and R1N are 50Ω.

  In the high-speed multiplexing circuit of FIG. 3, when the bias voltage VCS is supplied to the transistor Q5, the current source composed of the transistor Q5 and the resistor R2 is turned on, and the circuit starts operating. Here, when the clock signal CK1 is at a high level and the clock signal CK2 is at a low level, in the differential switch composed of the transistors Q3 and Q4, the transistor Q3 is turned on and the transistor Q4 is turned off. As a result, the differential pair constituted by the transistors Q1P and Q1N is turned on, and the differential pair constituted by the transistors Q2P and Q2N is turned off, so that the data signals D1P and D1N are amplified and the differential output signals QP and QN are amplified. Is output as

On the other hand, when the clock signal CK2 is at a high level and the clock signal CK1 is at a low level, in the differential switch composed of the transistors Q3 and Q4, the transistor Q4 is turned on and the transistor Q3 is turned off. As a result, the differential pair composed of the transistors Q1P and Q1N is turned off, and the differential pair composed of the transistors Q2P and Q2N is turned on, so that the data signals D2P and D2N are amplified and the differential output signals QP and QN Is output as
Thus, by alternately turning on the transistors Q3 and Q4 of the differential switch by the clock signals CK1 and CK2, two data signal sequences (D1P, D1N) and (D2P, D2N) are time-division multiplexed to form a single It can be converted into a data signal sequence.

  In the high-speed multiplexing circuit shown in FIG. 3, the transistors Q1P, Q1N, Q2P, Q2N, and Q3-Q5 have excellent high-frequency characteristics of fT (current cutoff frequency) = 270 GHz in order to realize a high-speed operation of 100 Gbit / s. Heterojunction bipolar transistor is used. The high-speed multiplexing circuit shown in FIG. 3 is called a selector core, and a circuit portion that performs a multiplexing logic operation is directly connected to an external 50Ω load.

Kimikazu Sano et al., “Over-100-Gbit / s Multiplexing Operation of InP DHBT Selector IC Designed with High Collector-Current Density”, 2004 International Conference on Solid State Devices and Materials (2004 SSDM), p.312-313, 2004

  However, in the conventional circuit configuration shown in FIG. 3, the waveform quality of the output waveform deteriorates, such as ringing in which the high and low levels of the output waveform undulate, and a double trace that causes a time difference in the level transition trace of the output waveform. There was a problem that it was easy to get up. FIG. 4 shows an output waveform of the high speed multiplexing circuit shown in FIG. FIG. 4 shows output waveforms when simulating a 100 Gbit / s multiplexing operation with the circuit configuration shown in FIG. 3 using InP heterojunction bipolar transistors of fT = 300 GHz as the transistors Q1P, Q1N, Q2P, Q2N, and Q3 to Q5. is there. In FIG. 4, 210 indicates ringing and 211 indicates a double trace.

  Thus, it can be seen that ringing or double tracing occurs in the output waveform shown in FIG. These ringing and double trace are generally regarded as deterioration of waveform quality because they reduce a threshold voltage and timing margin for determining the high level and low level of a digital signal.

  Causes of ringing and double trace are the transient current (switching noise) generated when the transistors Q1P, Q1N, Q2P, Q2N, Q3, and Q4 are turned on / off, and the collector potential of the current source transistor Q5 is transient. Change in the amount of current source current due to fluctuation. The transient current is a current component other than the current that should be turned on / off, that is, a current component other than the current flowing in the current source, and is caused by the parasitic capacitance of the transistor. Further, in the circuit configuration shown in FIG. 3, since the ringing generated in the selector core is directly output to the outside of the circuit without shaping the waveform, the circuit configuration in which the selector core is directly connected to the external 50Ω load also deteriorates the waveform quality. It is cited as a factor.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a high-speed multiplexing circuit that can improve the output waveform quality during high-speed operation.

The high-speed multiplexing circuit of the present invention is provided for each data signal string, and a plurality of first transistors for selectively outputting the input data signal string to a signal output terminal connected in common, and the plurality of first transistors A plurality of first transistors which are inserted in series with respect to each of the paths through which the collector current or drain current of one transistor flows, and serve as switches that turn on one of the plurality of first transistors in response to a clock signal. 2 transistors, a third transistor serving as a current source for supplying a collector current or a drain current to the first and second transistors, a power supply voltage terminal on the collector or drain and emitter or source side of the third transistor, And a capacitor inserted between the two.
In addition, one configuration example of the high-speed multiplexing circuit of the present invention is further characterized by further comprising a plurality of resistors inserted in series with respect to each of the emitters of the plurality of first transistors.
In addition, one configuration example of the high-speed multiplexing circuit according to the present invention further includes a plurality of resistors inserted in series with respect to each of the emitters of the plurality of second transistors.
Also, one configuration example of the high-speed multiplexing circuit of the present invention is characterized by further comprising an output buffer that receives the time-division multiplexed signal output from the signal output terminal.
In one configuration example of the high-speed multiplexing circuit of the present invention, the first, second, and third transistors and the transistors included in the output buffer are bipolar transistors.

  According to the present invention, by inserting a capacitor between the collector or drain of the third transistor constituting the current source and the power supply voltage terminal on the emitter or source side, in the high-speed multiplexing circuit, ringing, double tracing, etc. Thus, an output waveform having good waveform quality can be obtained.

  In the present invention, an output waveform having good waveform quality can be obtained by inserting a resistor in series with each of the emitters of the plurality of first transistors to which the data signal string is input.

  In the present invention, an output waveform having good waveform quality can be obtained by inserting a resistor in series with each of the emitters of the plurality of second transistors to which the clock signal is input.

  Further, in the present invention, an output waveform having good waveform quality can be obtained by providing an output buffer that receives the time-division multiplexed signal output from the signal output terminal.

1 is a circuit diagram showing a configuration of a high-speed multiplexing circuit according to an embodiment of the present invention. It is a figure which shows the output waveform of the high-speed multiplexing circuit which concerns on embodiment of this invention. It is a circuit diagram which shows the structure of the conventional high-speed multiplexing circuit. It is a figure which shows the output waveform of the conventional high-speed multiplexing circuit.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a high-speed multiplexing circuit according to an embodiment of the present invention.
The high-speed multiplexing circuit according to the present embodiment has an output buffer 101 connected to the subsequent stage of the selector core 100.

  The selector core 100 is differentially configured such that data signals D1P and D1N are input to a base, and transistors Q1P and Q1N forming a differential pair, and data signals D2P and D2N different from the data signals D1P and D1N are input to a base. Transistors Q2P and Q2N forming a pair, transistors Q3 and Q4 forming a differential switch to which clock signals CK1 and CK2 are input to the base, current source transistors Q6 and Q7 to which a bias voltage VCS is input to the base, The power supply voltage VCC is supplied to one end, the load resistor R1P is connected to the collectors of the transistors Q1P and Q2P at the other end, the power supply voltage VCC is supplied to one end, and the other end is connected to the collectors of the transistors Q1N and Q2N. The load resistor R1N and one end are connected to the emitters of the transistors Q1P and Q1N, Resistors R3P and R3N having one end connected to the collector of the transistor Q3, one end connected to the emitter of the transistor Q2P and Q2N, the other end connected to the collector of the transistor Q4, and one end connected to the transistor Q3 Resistors R5 and R6 having the other end connected to the emitters of Q4 and the other ends connected to the collectors of the transistors Q6 and Q7, and one end connected to the emitters of the transistors Q6 and Q7 and the other end being a resistor R7 to which the power supply voltage VEE is supplied , R8, and a capacitor C1 having one end connected to the collectors of the transistors Q6 and Q7 and the other end supplied with the power supply voltage VEE.

In FIG. 1, reference numeral 102 denotes a normal phase signal output terminal of the selector core 100, and reference numeral 103 denotes a negative phase signal output terminal. The collectors of the first transistors Q1N and Q2N are commonly connected to the positive phase signal output terminal 102, and the collectors of the first transistors Q1P and Q2P are also commonly connected to the negative phase signal output terminal 103. The
The second transistors Q3 and Q4 turn on either the differential pair composed of the transistors Q1P and Q1N or the differential pair composed of the transistors Q2P and Q2N according to the clock signals CK1 and CK2. .
The third transistors Q6 and Q7 cause a collector current to flow through the transistors Q1P, Q1N, Q2P, Q2N, Q3, and Q4.

  The output buffer 101 receives a time-division multiplexed post-phase signal output from the terminal 102 at the base, the transistor Q8P to which the power supply voltage VCC is supplied to the collector, and the time-division multiplexing output from the terminal 103 to the base. Transistor Q8N, to which the power supply voltage VCC is supplied to the collector, transistors Q9P and Q9N whose bases and collectors are connected to the emitters of transistors Q8P and Q8N, and bases and collectors are transistors Transistors Q10P, Q10N connected to the emitters of Q9P, Q9N, bias voltage VCS is supplied to the base, current source transistors Q11P, Q11N are connected to the emitters of the transistors Q10P, Q10N, and output from the transistor Q8P is the base Input positive phase signal Transistor Q12P, a transistor Q12N to which a reverse phase signal output from the transistor Q8N is input to the base, transistors Q13P and Q13N, a bias voltage VCS is supplied to the base, and a collector is connected to the emitters of the transistors Q13P and Q13N Current source transistors Q14P and Q14N, one end of which is connected to the emitters of the transistors Q11P and Q11N, the other end is supplied with the power supply voltage VEE, and the other end is supplied with the power supply voltage VCC. Load resistors R10P, R10N connected to the collectors of the transistors Q12P, Q12N, and resistors R11P, R connected at one end to the emitters of the transistors Q12P, Q12N and at the other end to the bases and collectors of the transistors Q13P, Q13N Has a 1N, one end transistor Q14P, is connected to the emitter of Q14N, resistance R12P the power supply voltage VEE is supplied to the other end, and R12N.

  Next, the operation of the high speed multiplexing circuit of this embodiment will be described. In this high-speed multiplexing circuit, when the bias voltage VCS is supplied to the transistors Q6 and Q7, the current source of the selector core 100 including the transistors Q6 and Q7 and the resistors R7 and R8 is turned on. Similarly, when a bias voltage VCS is supplied to the transistors Q11P, Q11N, Q14P, and Q14N, the current source of the output buffer 101 includes the transistors Q11P, Q11N, Q14P, and Q14N and resistors R9P, R9N, R12P, and R12N. Is turned on.

  Here, when the clock signal CK1 is at a high level and the clock signal CK2 is at a low level, in the differential switch composed of the transistors Q3 and Q4, the transistor Q3 is turned on and the transistor Q4 is turned off. As a result, the differential pair composed of the transistors Q1P and Q1N is turned on, and the differential pair composed of the transistors Q2P and Q2N is turned off, so that the data signals D1P and D1N are amplified and the differential signal is output to the output buffer 101. Is output.

On the other hand, when the clock signal CK2 is at a high level and the clock signal CK1 is at a low level, in the differential switch composed of the transistors Q3 and Q4, the transistor Q4 is turned on and the transistor Q3 is turned off. As a result, the differential pair composed of the transistors Q1P and Q1N is turned off, and the differential pair composed of the transistors Q2P and Q2N is turned on. Therefore, the data signals D2P and D2N are amplified, and the differential signal is output to the output buffer 101. Is output.
The output buffer 101 outputs the differential signal input from the selector core 100 as the differential output signals QP and QN.

The circuit configuration differs from the conventional high-speed multiplexing circuit shown in FIG. 3 in the following four points.
(1) The capacitor C1 is inserted between the collectors of the current source transistors Q6 and Q7 and the power supply voltage VEE.
(2) The resistors R3P, R3N, R4P, and R4N are inserted in series with the emitters of the transistors Q1P, Q1N, Q2P, and Q2N constituting the differential pair to which the data signals D1P, D1N, D2P, and D2N are input. .
(3) The resistors R5 and R6 are inserted in series with the emitters of the transistors Q3 and Q4 constituting the differential switch to which the clock signals CK1 and CK2 are input.
(4) The output buffer 101 is connected to the subsequent stage of the selector core 100.

  The effect of improving the output waveform quality due to the above differences will be described. First, in the present embodiment, as described in (1) above, by inserting the capacitor C1 between the collectors of the current source transistors Q6 and Q7 of the selector core 100 and the power supply voltage VEE, the current source transistors Q6 and Q6 are inserted. The fluctuation of the current source current amount due to the transient fluctuation of the collector potential of Q7 can be suppressed by the capacitor C1, and as a result, the waveform quality of the differential signal output from the selector core 100 can be improved.

  Note that the fluctuations in the collector potentials of the current source transistors Q6 and Q7 originate from the on / off of the clock signals CK1 and CK2. For this reason, the insertion of the capacitor C1 is effective in improving ringing, double tracing, etc. that occur only when the clock signals CK1 and CK2 are turned on / off regardless of the data pattern.

  In the present embodiment, as described in (2) above, in series with the emitters of the transistors Q1P, Q1N, Q2P, Q2N constituting the differential pair to which the data signals D1P, D1N, D2P, D2N are input. By inserting the resistors R3P, R3N, R4P, and R4N, an additional transient current (switching noise) generated in the differential pair composed of the transistors Q1P and Q1N and the differential pair composed of the transistors Q2P and Q2N is generated. As a result, the waveform quality of the differential signal output from the selector core 100 can be improved.

  Such a transient current suppression effect is a negative feedback effect on the base-emitter voltages of the transistors Q1P, Q1N, Q2P, and Q2N in which the emitter resistors R3P, R3N, R4P, and R4N are the inputs of the differential pair ( This is because it has a function of suppressing a sudden change by adding a certain suppression to the rise in the base-emitter voltage.

  In this embodiment, as described in (3) above, resistors R5 and R6 are inserted in series with the emitters of the transistors Q3 and Q4 constituting the differential switch to which the clock signals CK1 and CK2 are input. Thus, an additional transient current (switching noise) generated in the differential switch can be suppressed, and as a result, the waveform quality of the differential signal output from the selector core 100 can be improved.

  The mechanism for suppressing the switching noise is the same as (2) above. Since the on / off of the clock signals CK1 and CK2 occurs regardless of the data pattern, the insertion of the resistors R5 and R6 is ringing that occurs only when the clock signals CK1 and CK2 are on / off regardless of the data pattern. It has the effect of improving the double trace and the like.

  In the present embodiment, as described in (4) above, by connecting the output buffer 101 to the subsequent stage of the selector core 100, the output waveform of the selector core 100 can be shaped by the output buffer 101. As a result, the output waveform quality can be improved. Since the output buffer 101 has a certain amount of gain and limits the output amplitude, the output waveform can be shaped so that the undulation (ringing) between the high level and the low level is particularly constant.

  The output waveform of the high-speed multiplexing circuit of this embodiment is shown in FIG. 2 shows transistors Q1P, Q1N, Q2P, Q2N, Q3, Q4, Q6, Q7, Q8P, Q8N, Q9P, Q9N, Q10P, Q10N, Q11P, Q11N, Q12P, Q12N, Q13P, Q13N, Q14P, Q14N as fT = It is an output waveform when a 100 Gbit / s multiplexing operation is simulated using the circuit configuration shown in FIG. 1 using a 300 GHz InP heterojunction bipolar transistor. Comparing the output waveform of FIG. 2 with the conventional output waveform shown in FIG. 4, it can be seen that ring waveform and double trace are reduced in this embodiment, and the output waveform quality is improved.

  In this embodiment, an InP heterojunction bipolar transistor is used for each of the selector core 100 and the output buffer 101, but other bipolar transistors such as a SiGe heterojunction bipolar transistor, a GaAs heterojunction bipolar transistor, Si The same effect can be obtained by using a bipolar transistor or the like.

  Furthermore, even if a field effect transistor is used, the same effect can be obtained although there is a difference in effect. In this case, it goes without saying that in each transistor of FIG. 1, the base is replaced with the gate of the field effect transistor, the emitter is replaced with the source of the field effect transistor, and the collector is replaced with the drain of the field effect transistor. However, when the selector core is directly connected to an external 50Ω load as in the conventional high-speed multiplexing circuit, it is easier to secure a band by using a field effect transistor. However, as in this embodiment, the selector core When the output buffer 101 is connected to the subsequent stage of 100, it is more preferable to use a bipolar transistor in terms of securing a band.

  The present invention can be applied to a high-speed multiplexing circuit.

  DESCRIPTION OF SYMBOLS 100 ... Selector core, 101 ... Output buffer, 102 ... Positive phase signal output terminal, 103 ... Negative phase signal output terminal, Q1P, Q1N, Q2P, Q2N, Q3, Q4, Q6, Q7, Q8P, Q8N, Q9P, Q9N, Q10P, Q10N, Q11P, Q11N, Q12P, Q12N, Q13P, Q13N, Q14P, Q14N ... transistor, R1P, R1N, R3P, R3N, R4P, R4N, R5 to R8, R9P, R9N, R10P, R10N, R11P, R11N, R12P, R12N: resistors, CK1, CK2 ... clock signals, D1P, D1N, D2P, D2N ... data signals, QP, QN ... output signals, VCC, VEE ... power supply voltage, VCS ... bias voltage.

Claims (5)

A plurality of first transistors that are provided for each data signal sequence and selectively output the input data signal sequence to a commonly connected signal output terminal;
A switch that is inserted in series with respect to each of the paths through which collector currents or drain currents of the plurality of first transistors flow, and that turns on one of the plurality of first transistors in response to a clock signal; A plurality of second transistors,
A third transistor serving as a current source for supplying a collector current or a drain current to the first and second transistors;
A high-speed multiplexing circuit comprising a capacitor inserted between the collector or drain of the third transistor and a power supply voltage terminal on the emitter or source side. The high speed multiplexing circuit according to claim 1, wherein
The high-speed multiplexing circuit further comprises a plurality of resistors inserted in series with respect to each of the emitters of the plurality of first transistors. The high speed multiplexing circuit according to claim 1, wherein
The high-speed multiplexing circuit further comprises a plurality of resistors inserted in series with respect to each of the emitters of the plurality of second transistors. The high speed multiplexing circuit according to claim 1, wherein
The high-speed multiplexing circuit further comprises an output buffer for receiving the time-division multiplexed signal output from the signal output terminal. The high-speed multiplexing circuit according to claim 4,
The high-speed multiplexing circuit, wherein the first, second, and third transistors and the transistors included in the output buffer are bipolar transistors.

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