JPH10256890A - Logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a selector circuit in which a duty ratio of an output is not fluctuated even when DC offset levels of biphase input clock signals are deviated from each other. SOLUTION: Transistors(TRs) Q5, Q6 switch a current between differential pair TRs Q1, Q2 and differential pair TRs Q3, Q4 by using biphase clock signals CK, inverse of CK. A DC cut-off capacitor Cx is connected between sources of the TRs Q5, Q6 and the sources TRs Q5, Q6 are separated in terms of DC. Thus, a current flowing by two current source TRs Q10, Q11 is completely independent. Since the sources of the TRs Q5, Q6 are connected in terms of AC, a current switching function by the clock signal is active. Then even when the amplitude center of the biphase clock signals CK, inverse of CK is deviated, the duty ratio of an output signal of the selector circuit is not fluctuated thereby.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit for inputting and outputting digital signals using a differential circuit, and more particularly to a high-speed logic circuit used in a multiplexed communication system such as an optical communication system.

[0002]

2. Description of the Related Art In an optical communication system, multi-bit input data is time-division multiplexed to transmit the input data as serial data having a high bit rate.
On the receiving side, a method of separating the data into multi-bit data is used.

FIG. 9 shows a conventional example of a circuit (multiplexer) for time-division multiplexing multi-bit data D1 to D8. The multiplexer shown in FIG. 9 performs an 8: 1 parallel-serial conversion, and the main circuit section is configured by connecting two stages of a 2: 1 multiplexer (MUX) in a tree-like configuration as shown. . Each 2: 1 multiplexer has a master-slave flip-flop (M
S-FF), a tri-stage flip-flop (TS-FF) having three stages of latch circuits, and a selector circuit (SEL). In addition, the frequencies of f0 / 8, f0 / 4, f0 / 4,
Clock signal CK divided by f0 / 2 is applied.
Here, f0 is the frequency of the external clock CK and is equal to the frequency of the data rate of the output data Dout. (That is, if the output data rate is 10 Gb / s, f0
Is 10 GHz. Each clock signal needs to be supplied to the main circuit at an appropriate timing. For this reason, a buffer chain is provided between the main circuit and the counter circuit that generates the internal clock signals having the frequencies f0 / 8, f0 / 4, and f0 / 2, respectively, to provide an appropriate delay.

Meanwhile, an optical communication system is required to have a high speed approaching the limit of transistor performance. The multiplexer is basically composed of a flip-flop and a selector as described above, but in order to realize these high speeds, most of the circuits in the multiplexer shown in FIG. 9 are realized using differential circuits. The reason is that when a differential circuit is used, only one logic circuit is required to realize the latch function or the data selection function, and therefore, high-speed operation can be realized. Therefore, hereinafter, the discussion will proceed on the premise that a differential circuit is used.

In a multiplexer having a configuration as shown in FIG.
It is necessary to give the largest delay time to the internal clock signal having the frequency of f0 / 2. In the design example by the inventors, the number of stages of the buffer chain for the internal clock signal is 11 stages. If each buffer of the buffer chain having such a large number of stages is constituted by a differential circuit, the two-phase clock signals CK, CK￣
In this case, the internal clock signals CK and CK # input to the 2: 1 multiplexer are input and output.
A problem arises that the amplitude center, that is, the DC offset level is shifted from each other. The deviation of the DC offset level between the internal clock signals CK and CK # is caused by the pairing between the CK output source follower transistor and the CK # output source follower transistor provided at the output stage of each stage of the differential circuit. This is caused by misalignment. Therefore, as the number of stages in the buffer chain increases, the shift amount of the DC offset level between internal clock signals CK and CK # also increases.

A clock signal C having a frequency as high as 10 GHz
Since the waveform of K is actually a sine wave, the duty ratio of the internal clock signals CK and CK # becomes 50% of the ideal value when the amplitude centers match, but if there is a deviation in the DC offset level, Since the two amplitude centers are different from each other, the duty ratio of the internal clock signals CK and CK # deviates from 50% of the ideal value. Since the duty ratio of the internal clock signal appears directly in the duty ratio of the output signal of the selector circuit, deviation of the duty ratio of the internal clock signal poses a serious problem.

Further, such a shift in the duty ratio of the internal clock signal may cause a malfunction in the flip-flop circuit constituting the main circuit portion of the multiplexer. Specifically, the deterioration of the duty ratio of the internal clock signal causes the deterioration of the phase margin between the data input timing and the data holding timing of the flip-flop and the deterioration of the output waveform, resulting in malfunction.

[0008]

As described above, in the prior art, the duty ratio of the output signal of the selector circuit fluctuates due to the shift of the duty ratio due to the shift of the offset level of the internal clock signal, or the phase of the flip-flop circuit is changed. There was a problem that the margin and the output waveform deteriorated.

The present invention has been made in consideration of the above circumstances, and has as its object to provide a logic circuit capable of guaranteeing a stable operation irrespective of a shift in a duty ratio of an internal clock signal. .

[0010]

SUMMARY OF THE INVENTION A logic circuit according to the present invention has first logic circuits each operating in response to an input digital signal.
And a second pair of differential transistors, first and second current sources, and a common source or common emitter of the first differential transistor pair and the first current source; First operation controlled by input clock signal
A transistor, a second transistor inserted between a common source or common emitter of the second differential transistor pair and the second current source, the operation of which is controlled by an inverted signal of the input clock signal; A capacitor connected between the current source terminal of the transistor and the current source terminal of the second transistor.

This logic circuit is a high-speed digital logic circuit for inputting and outputting digital signals by using a differential circuit. The logic circuit is provided between a current source terminal of a first transistor and a current source terminal of the second transistor. That is, the sources or emitters of these transistors are connected by a DC cut capacitor. With this DC cut capacitor, the source (or emitter) between the first and second transistors receiving the clock signals of both phases is separated in terms of DC. Therefore, the current flow of the first differential transistor pair and the current flow of the second differential transistor pair are completely independent. Therefore, the value of the current flowing through each of the first and second differential transistor pairs is determined only by the first and second current sources. If these current sources are ideal, the first differential transistor pair And the current flowing therethrough during the operation of the second differential transistor pair are equal irrespective of the potential at the amplitude center of each of the two-phase clock signals.

On the other hand, in terms of AC, the source (or emitter) between the first and second transistors receiving the clock signals of both phases is connected, and the clock signals of both phases have a high frequency. Therefore, a current flows through the first differential transistor pair during a period when the input clock signal has a higher potential than the center of the amplitude (a period when the inverted clock signal has a lower potential than the center of the amplitude), and the input clock signal has the center of the amplitude. A current switching function using a two-phase clock signal having an opposite phase relationship, in which a current flows through the second differential transistor pair during a period with a lower potential (the inverted clock signal has a higher potential than the center of its amplitude). Works fine.

Therefore, it is possible to guarantee the normal operation of a logic circuit such as a selector circuit or a flip-flop which operates using two pairs of differential transistors, regardless of the difference in the DC offset level between the two-phase clock signals. It becomes possible.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a selector circuit as a logic circuit according to the first embodiment of the present invention. This selector circuit is incorporated in an IC as an element of a circuit requiring high-speed operation, such as the multiplexer of FIG. Hereinafter, GaAs ME is used as a transistor.
The configuration will be described using an example in which an SFET is used.

The selector circuit shown in FIG. 1 comprises a first differential transistor pair Q1 and Q2 and a second differential transistor pair Q
3 and Q4, and an output circuit section including source follower transistors Q7 and Q8 provided as output stages thereof.

In the logic circuit section, the sources of the first differential transistor pair Q1 and Q2 are commonly connected as shown, and the gates of the transistors Q1 and Q2 are connected to the first two-phase digital input signal. Da, Da} are input. The drains of the transistors Q1 and Q2 are commonly connected via resistors R2 and R3 to one end of a resistor R1 whose one end is grounded. Transistor Q
The drains of Q1 and Q2 serve as output signals of the differential circuit, which are connected to the gates of source follower transistors Q7 and Q8, respectively.

The transistors Q5 and Q5 are connected between the common source of the differential transistor pair Q1 and Q2 and the low power supply terminal Vss.
Q10 and a resistor R4 are connected in series. Transistor Q5 is for controlling the current flowing through differential transistor pair Q1, Q2, and has its gate receiving one of input clock signals CK, CK # of both phases, ie, CK. The input clock signals CK and CK # are high-frequency signals near the operating limit of the transistor, and have a sine wave waveform. Transistor Q10 is a differential transistor pair Q
It functions as a current source for Q1 and Q2, and a fixed potential Vb is input to its gate.

The sources of the second differential transistor pair Q3, Q4 are connected in common as shown, and the gates of the transistors Q3, Q4 receive the second two-phase digital input signals Db, Db #, respectively. You. Transistor Q
3 and Q4 are connected to the differential transistor pair Q1, Q2
In order to share the load with the resistor R1, the resistor R2 and the resistor R3 are commonly connected to the other end of the resistor R1. The drains of the transistors Q3 and Q4 serve as output signals of the differential circuit, and these are source follower transistors Q7 and Q8.
Are connected to the respective gates.

The transistors Q6 and Q4 are connected between the common source of the differential transistor pair Q3 and Q4 and the low power supply terminal VSS.
Q11 and a resistor R5 are connected in series. Transistor Q6 controls the current flowing through differential transistor pair Q3, Q4, and has the gate to which the other of input clock signals CK, CK # of the two phases, that is, CK #, is input. Transistor Q11 is a differential transistor pair Q
3 and 4 function as current sources, and the gate thereof is supplied with the same fixed potential Vb as that of the transistor Q10.

A DC cut capacitor Cx is connected between the sources of the transistors Q5 and Q6 to which the two-phase clock signals CK and CK # are input. Further, the output circuit section includes a first source follower circuit for outputting the digital input signal Da or Db, and a digital input signal Da.
Alternatively, it comprises a second source follower circuit for outputting Db.

The first source follower circuit has a ground terminal and V
It comprises a transistor Q7, a diode D1, a transistor Q12, and a resistor R6 connected in series with the ss terminal. The fixed potential Vb is input to the gate of the transistor Q12, and functions as a current source of the first source follower circuit. Diode D1 and transistor Q
The potential at the connection point 12 is used as a digital signal OUT for selectively outputting the digital input signals Da and Db.

The second source follower circuit has a ground terminal and V
It is composed of a transistor Q8, a diode D2, a transistor Q13 and a resistor R7 connected in series with the ss terminal. The fixed potential Vb is input to the gate of the transistor Q13, and the transistor Q13 functions as a current source of the second source follower circuit. Diode D2 and transistor Q
13 are connected to the digital input signals Da￣, Db
￣ is output as a digital signal OUT￣ composed of a selection output.

In this selector circuit, transistors Q5, Q6 receiving bi-phase clock signals CK, CK #
, Current flows alternately between the differential transistor pair Q1, Q2 and the differential transistor pair Q3, Q4, whereby the digital input signals Da, Da # and Db, Db #
Are alternately selected.

Now, in the selector circuit of FIG.
Transistors Q5 receiving clock signals CK, CK #
It is important that the sources of Q6 are not directly connected but connected via a capacitor Cx.

In order to clarify the effect of this embodiment, the operation characteristics of these circuits are compared with a circuit (see FIG. 2) in which the capacitors Cx are removed from the circuit of FIG. 1 and the sources of the transistors Q5 and Q6 are connected DC (see FIG. 2). explain.

The present inventors performed circuit simulation by SPICE for each of the circuits shown in FIGS. The results are shown below. First, FIG. 3 shows a simulation result of the circuit of FIG. In this simulation, the following data patterns are given as two input data D1 and D2.

D1: 01010101101... D2: 0011001100... At this time, the expected value of the output data Dout is as follows.

Dout: 001001100100
1110... The result of FIG. 3 shows that the expected value of the above output pattern is obtained and that the operation is normal. In this simulation, a selector circuit at the last stage of an 8: 1 multiplexer that outputs a 10 Gb / s data signal is assumed, and the frequency of a clock supplied to the selector circuit is 5
GHz and the bit rate of input data are 5 Gb / s.

FIG. 4 is a slightly modified version of the result of FIG. 3 for examining the duty ratio of the output waveform. That is, FIG.
3 is a simple eye pattern in which the output waveform of FIG. Here, it is assumed that there is no offset level shift between the two-phase clock signals CK and CK #. In this case, it is understood that the output duty ratio is normal.

Next, a simulation result in the case where there is a deviation in the offset level of the two-phase clock signal will be described. FIG. 5 is an eye pattern of an output waveform of the selector circuit of FIG. 2 having no capacitor Cx. It can be seen that the duty ratio of the output waveform is shifted with the shift of the duty ratio of the clock signal.

FIG. 6 shows a simulation result for the selector circuit of FIG. Similar to the case of FIG. 5, it can be seen that an almost ideal duty ratio is obtained despite the difference between the offset levels of the two-phase clock signals.

The transistors used in the simulation are as follows. An MESFET formed by using tungsten nitride in which an active layer is formed on a semi-insulating GaAs substrate by selective ion implantation of Si and tungsten is laminated on a gate, and has a gate length of 0.5 μm and a P layer embedding process. It was formed. The threshold voltage is -0.2V.

The main circuit parameters used in this simulation are as follows. The gate width of the differential transistor pair in the logic circuit section is 18 μm, the gate width of each transistor operating as a current source in the logic circuit section is 9 μm, and the gate width of all transistors in the source follower circuit section is 36 μm. The capacitance value of the capacitor Cx is 10
0 fF.

The low power supply voltage Vss is -5.2 V, and the fixed potential bias voltage Vb is -4.5 V. The gate-source voltage of all current source transistors is 0.3
The value of each resistance value is set so that 5 V and the logic amplitude are 0.9 V.

As described above, in the selector circuit according to the first embodiment, the source between the transistors Q5 and Q6 receiving the clock signals CK and CK # of both phases is separated in terms of DC by the DC cut capacitor Cx. Therefore, the current flows through the two current source transistors Q10 and Q11, that is, the current flows through the differential transistor pairs Q1 and Q2 and the current flows through the differential transistor pairs Q3 and Q4 become completely independent. Therefore, the current values flowing through the differential transistor pairs Q1, Q2 and the differential transistor pairs Q3, Q4 are determined only by the current source transistors Q10, Q11. If these current sources are ideal, The current flowing during the operation of the differential transistor pair Q1 and Q2 and the differential transistor pair Q3
The current flowing therethrough during the operation of Q4 is equal regardless of the potential at the amplitude center of each of the two-phase clock signals CK and CK #.

On the other hand, in terms of AC, the clock signals of both phases are C
The sources between the transistors Q5 and Q6 that receive K and CK # are connected, and the two-phase clock signals CK and CK # have a high frequency. Therefore, the circuit operates in exactly the same way as the circuit of FIG. 2 in terms of AC, and the current switching function using the clock signals CK and CK # of both phases having the opposite phase relationship functions normally.

Therefore, even if the DC offset levels between the two-phase clock signals CK and CK # deviate from each other, it is possible to realize a selector circuit in which the output duty ratio does not fluctuate from the ideal value.

The case where the GaAs MESFET is used has been described above. In this embodiment, the compound type HBT and SiM
SiE using OSFET and bipolar transistor
It can also be realized by using other electronic devices such as CL.

FIG. 7 shows a configuration example of a flip-flop as a logic circuit according to the second embodiment of the present invention. This flip-flop circuit has the same configuration as that of FIG. 1 except that the gates of the differential transistor pair Q3 and Q4 of FIG. 1 are connected to the output terminals OUT and OUT # of the source follower circuit.

That is, in this flip-flop circuit, the differential transistor pair Q1, Q2 operates as an input differential circuit for inputting digital data D, D #, and the differential transistor pair Q3, Q4 outputs the output data. It operates as a holding differential circuit. The operation timings of the input differential circuit and the data holding differential circuit are alternately switched by the transistors Q5 and Q6 under the control of the two-phase clock signals CK and CK #.

Also in this flip-flop circuit, the input differential circuit and the data holding circuit can be used in accordance with the same principle as that of the selector circuit shown in FIG. 1 regardless of the shift of the DC offset level between the two-phase clock signals CK and CK #. Operation timing of the differential circuit can be defined normally.

To clarify the effect of the second embodiment, a circuit in which the capacitor Cx is removed from the circuit of FIG. 7 and the sources of the transistors Q5 and Q6 are DC-connected (FIG. 8)
) Will be described as a comparative example.

The present inventors performed circuit simulations by SPICE for the circuits shown in FIGS. 7 and 8, respectively. The results are shown below. In the simulation, the phase margin of a master-slave flip-flop configured using two stages of the flip-flop of FIG. 7 or 8 was examined. The input data rate at that time is 10 Gb /
s, the clock frequency was 10 GHz, and the input amplitude was 0.9 Vpp.

As a result of the simulation, the phase margin in an ideal case where there is no deviation in the offset levels of the two-phase clock signals CK and CK # is 250 degrees in both FIGS. However, when a simulation was performed in which the offset level was shifted by 400 mV, the phase margin of the circuit of FIG. 8 having no capacitor Cx was deteriorated to 140 degrees.
Further, even within the phase margin, the output amplitude deteriorated. On the other hand, in the circuit of FIG. 7, even when the variation of the offset level becomes 900 mV, which is the same magnitude as the input amplitude, the phase margin is the same as that when there is no offset level shift 2.
It was 50 degrees. Also, the output waveform did not deteriorate.
Therefore, according to the second embodiment, it is possible to realize a flip-flop circuit in which the phase margin and the output waveform are not deteriorated even if the DC offset levels of the two-phase clock signals are shifted from each other.

The transistors used in the simulation are as follows. An MESFET formed by using tungsten nitride in which an active layer is formed on a semi-insulating GaAs substrate by selective ion implantation of Si and tungsten is laminated on a gate, and has a gate length of 0.5 μm and a P layer embedding process. It was formed. The threshold voltage is -0.2V.

The main circuit parameters used in the simulation for the second embodiment are as follows.
The gate width of the FET pair in the logic circuit section is 18 μm, the current source FET in the logic circuit section is 9 μm, and the FET width of the source follower is 36 μm. The capacitance value of the capacitor Cx is 1
00fF.

The power supply voltage Vss is -5.2 V, and the fixed potential bias voltage Vb is -4.5 V. The values of the respective resistances are set so that the gate-source voltages of all current source FETs are 0.35 V and the logic amplitude is 0.9 V.

Although an example using a GaAs MESFET has been described above, the present embodiment is directed to a compound-based HBT,
Si EC using SFET and bipolar transistor
L and other electronic devices.

[0049]

As described above, according to the present invention, it is possible to provide a logic circuit which can guarantee a stable operation irrespective of the deviation of the duty ratio of the internal clock signal.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a selector circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a normal selector circuit used as a comparative example for explaining the operation of the selector circuit of the first embodiment.

FIG. 3 is a view showing a simulation result of the selector circuit of the first embodiment.

FIG. 4 is a view showing a clock waveform and an eye pattern of an output in the selector circuit of the first embodiment.

5 is a diagram showing a clock waveform when an offset level of a two-phase clock signal is shifted and an eye pattern of an output of the selector circuit in FIG. 2 at that time.

FIG. 6 is a view showing a clock waveform when an offset level of a two-phase clock signal is shifted and an eye pattern of an output of the selector circuit according to the first embodiment at that time.

FIG. 7 is a circuit diagram showing a configuration of a flip-flop according to a second embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of a normal flip-flop circuit used as a comparative example for explaining the operation of the flip-flop circuit of the second embodiment.

FIG. 9 is a diagram showing a configuration example of an 8: 1 multiplexer to which a selector circuit and a flip-flop according to the present invention are applied;

[Explanation of symbols]

 Q1, Q2: Differential transistor pair Q2, Q3: Differential transistor pair Q5, Q6: Current switching transistor Q10, Q11: Current source transistor MUX: Multiplexer TS-FF: Tri-stage flip-flop MS-FF: Master slave Flip-flop SEL ... Selector circuit CK ... Clock signal f0 ... External clock frequency D1-D8 ... Digital input data Dout ... Output data Vss ... Power supply potential Vb ... Bias potential

Claims (3)

[Claims] 1. A first and a second current source, each of which operates in response to an input digital signal, a first and a second current source, and a common of the first differential transistor pair A first transistor inserted between a source or a common emitter and the first current source and controlled in operation by an input clock signal; a common source or a common emitter of the second differential transistor pair; and the second current source A second transistor inserted between the first and second transistors, the operation of which is controlled by an inverted signal of the input clock signal; and a second transistor connected between a current source side terminal of the first transistor and a current source side terminal of the second transistor. A logic circuit comprising: a capacitor; 2. A first differential transistor pair provided with a first two-phase digital input signal as a differential input signal, and a second difference transistor provided with a second two-phase digital input signal as a differential input signal. And a current switching circuit that selectively supplies current to the first and second two pairs of differential transistors in response to an input clock signal. A logic circuit that operates as a selector circuit that outputs one of the first and second two-phase digital input signals by selectively operating two differential transistor pairs. And a second current source, and the input clock signal inserted between a common source or a common emitter of the first differential transistor pair and the first current source. A first transistor, the operation of which is controlled between the first transistor and a common source or common emitter of the second differential transistor pair and the second current source, the operation of which is controlled by an inverted signal of the input clock signal. A logic circuit comprising: two transistors; and a capacitor connected between a current source side terminal of the first transistor and a current source side terminal of the second transistor. 3. A first differential transistor pair for inputting a two-phase digital signal, a second differential transistor pair for holding a two-phase digital signal, and the first differential transistor pair according to an input clock signal.
And a current switching circuit that selectively supplies current to the two pairs of differential transistors, and operates as a data holding circuit that captures a digital input signal in response to the input clock signal. A switching circuit is inserted between first and second current sources, a common source or a common emitter of the first differential transistor pair, and the first current source, and is operation-controlled by the input clock signal. A first transistor, a second transistor inserted between a common source or common emitter of the second differential transistor pair and the second current source, the operation of which is controlled by an inverted signal of the input clock signal; A capacitor connected between the current source terminal of the first transistor and the current source terminal of the second transistor. Logic circuit according to claim and.