JP2010267881A - Field-effect transistor and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field-effect transistor of a vertical channel structure which can reduce a leak current at a gate voltage 0V and realize a sufficient normally-off operation, and to provide a method of manufacturing the same. <P>SOLUTION: The field effect transistor has a high concentration n-type GaN layer 102; an n-type GaN layer 103 which is formed on the high concentration n-type GaN layer 102 and have flattened part 124 and projecting part 122 on a surface with a carrier concentration lower than the carrier concentration of the high concentration n-type GaN layer 102; a WSi source electrode 105 formed on an upper surface of the projecting part 122; a Ti/Al drain electrode 109 electrically connected to the high concentration n-type GaN layer 102; a p-type ZnO layer 106 formed on the flattened part 124 to come into contact with a side surface of the projecting part 122; and an Ni/Au gate electrode 107 formed on the p-type ZnO layer 106. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a field effect transistor using a nitride semiconductor that can be applied to a power transistor used in, for example, a power supply circuit of a consumer device, and a manufacturing method thereof.

  Group III nitride semiconductors typified by gallium nitride (GaN) are wide gap semiconductors such as gallium nitride (GaN) and aluminum nitride (AlN), which have large forbidden band widths of 3.4 eV and 6.2 eV, respectively, at room temperature. In addition, the dielectric breakdown electric field is large and the electron saturation speed is higher than that of a compound semiconductor such as gallium arsenide (GaAs) or silicon (Si). Thus, research and development of field effect transistors (FETs) using GaN-based nitride semiconductor materials are being actively conducted as high-frequency electronic devices or high-power electronic devices.

  Further, in the AlGaN / GaN heterostructure on the (0001) plane, high concentration carriers generated by spontaneous polarization and piezoelectric polarization are generated at the interface even when no impurity is doped. Therefore, a depletion type (normally on type) field effect transistor having a low on-resistance lateral channel structure using a nitride semiconductor heterojunction has been reported (see Non-Patent Document 1).

  By the way, in order to improve the breakdown voltage in a field effect transistor having such a lateral channel structure, it is necessary to increase the distance between the gate electrode and the drain electrode. To achieve a high breakdown voltage field effect transistor, the device size increases. There is a problem.

  On the other hand, as a field effect transistor capable of realizing a high breakdown voltage with a smaller device size, there are field effect transistors having a vertical channel structure called SIT (Static Induction Transistor) or PBT (Permable Base Transistor). . A field effect transistor having a vertical channel structure is configured by forming a convex portion on the surface of a semiconductor layer, forming a source electrode and a drain electrode above and below the convex portion, and forming a gate electrode on the side wall of the convex portion. Is done. In general, the current flowing through the channel is controlled by the gate voltage applied to the gate electrode.

M.Hikita et al. IEDM Tech Digest 2004, p.803

  However, in the conventional field effect transistor having a vertical channel structure, a leak current is large when no voltage is applied to the gate electrode (gate voltage 0 V), and a sufficiently normally-off operation is not realized.

  In view of the above problems, an object of the present invention is to provide a field effect transistor having a vertical channel structure capable of reducing a leakage current at a gate voltage of 0 V and realizing a sufficient normally-off operation, and a manufacturing method thereof.

  In order to achieve the above object, a nitride semiconductor field effect transistor according to the present invention is formed on a first conductivity type first nitride semiconductor layer, the first nitride semiconductor layer, a flat portion, and A first conductivity type second nitride semiconductor layer having a convex portion provided on the surface and having a carrier concentration lower than the carrier concentration of the first nitride semiconductor layer, and a source formed above the convex portion An electrode, a drain electrode electrically connected to the first nitride semiconductor layer, and a second conductivity type third semiconductor layer formed on the flat portion so as to be in contact with a side surface of the convex portion And a gate electrode formed on the third semiconductor layer.

  According to this configuration, the built-in potential generated by the junction of the first conductivity type second nitride semiconductor layer and the second conductivity type third semiconductor layer reduces the potential energy of the second nitride semiconductor layer. Change. Therefore, a depletion layer is formed so as to cross the convex portion of the second nitride semiconductor layer, and the channel is divided by the depletion layer. As a result, no current flows when no gate voltage is applied, so that a leakage current at a gate voltage of 0 V is reduced, and a sufficiently normally off operation is possible in a field effect transistor having a vertical channel structure.

  In addition, since a pn junction having a larger built-in potential than a Schottky junction that is a junction between a metal and a semiconductor is used, the rising voltage of the gate can be increased and a large drain current can be obtained. At the same time, even if a positive gate voltage is applied, the gate leakage current can be kept small.

  Here, the field effect transistor of the present invention is characterized in that the third semiconductor layer contains oxygen or sulfur as a constituent element.

  According to this configuration, a wide band gap semiconductor having oxygen or sulfur as a constituent element can be used for the third semiconductor layer, and a large built-in potential can be obtained.

  The field effect transistor of the present invention is characterized in that the third semiconductor layer has a crystal structure of any one of a delafossite structure, a chalcogenide structure, a rock salt structure, and a wurtzite structure.

  The field effect transistor of the present invention is characterized in that the third semiconductor layer is a nitride semiconductor layer.

  In the field effect transistor of the present invention, the first nitride semiconductor layer and the second nitride semiconductor layer are each an n-type semiconductor layer, and the third semiconductor layer is a p-type semiconductor layer. It is characterized by.

  The field effect transistor of the present invention further includes a semiconductor layer formed above the source electrode and made of the same material as the third semiconductor layer, and the gate electrode formed above the source electrode. It is characterized by comprising at least one of electrodes made of the same material.

  According to this configuration, the third semiconductor layer and the gate electrode can be formed by a self-align process using the source electrode as a mask, and a field effect transistor having a vertical channel with a smaller chip area can be realized. It becomes.

  According to the present invention, a step of forming a first conductivity type first nitride semiconductor layer on a substrate, a flat portion and a convex portion are provided on the surface of the first nitride semiconductor layer, Forming a first conductivity type second nitride semiconductor layer having a carrier concentration lower than the carrier concentration of the first nitride semiconductor layer, and forming a source electrode above the second nitride semiconductor layer A step of forming a drain electrode electrically connected to the first nitride semiconductor layer, and a second conductive type third electrode on the flat portion so as to contact a side surface of the convex portion. It can also be set as the manufacturing method of a field effect transistor including the process of forming a semiconductor layer, and the process of forming a gate electrode on the said 3rd semiconductor layer.

  According to the field effect transistor and the method of manufacturing the same of the present invention, it is possible to realize a normally-off and large current vertical channel structure field effect transistor using a nitride semiconductor having a high off breakdown voltage.

1 is a cross-sectional view of a field effect transistor having a vertical channel structure according to a first embodiment of the present invention. It is sectional drawing which shows the manufacturing method of the field effect transistor which concerns on the same embodiment. It is sectional drawing of the field effect transistor of the vertical channel structure which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the field effect transistor which concerns on the same embodiment. It is sectional drawing of the field effect transistor of the vertical channel structure which concerns on the 3rd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the field effect transistor which concerns on the same embodiment.

(First embodiment)
A vertical channel structure field effect transistor according to a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a field effect transistor having a vertical channel structure according to the present embodiment.
As shown in FIG. 1, the field effect transistor includes an n-type GaN substrate 101, a high-concentration n-type GaN layer 102, an n-type GaN layer 103, a high-concentration n-type InAlGaN layer 104, a tungsten silicide (WSi) source electrode 105, A p-type zinc oxide (ZnO) layer 106, a p-type ZnO layer 117, a nickel (Ni) / gold (Au) gate electrode 107, a titanium (Ti) / aluminum (Al) drain electrode 109, and a Ni / Au electrode 108 are provided. .

  In the field effect transistor, a high-concentration n-type GaN layer 102, an n-type GaN layer 103, and a high-concentration n-type InAlGaN layer are formed on the main surface of an n-type GaN substrate 101 whose plane orientation is (0001). 104 are sequentially epitaxially grown.

  The n-type GaN layer 103 is formed on the high-concentration n-type GaN layer 102, has a flat portion 124 and a convex portion 122 on the surface, and has a carrier concentration lower than the carrier concentration of the high-concentration n-type GaN layer 102. It is a semiconductor layer.

The high concentration n-type InAlGaN layer 104 is selectively formed on the upper surface of the convex portion 122. The high-concentration n-type InAlGaN layer 104 is made of, for example, In _0.02 Al _0.38 Ga _0.60 N, and is formed so as to lattice match with the n-type GaN layer 103. A part of the n-type GaN layer 103 and the high-concentration n-type InAlGaN layer 104 is selectively removed, and a notch 121 having a depth of, for example, 250 nm is formed from the surface of the high-concentration n-type InAlGaN layer 104.

  The Ni / Au gate electrode 107 is made of Ni / Au, the Ti / Al drain electrode 109 is made of Ti / Al, and the Ni / Au electrode 108 is made of Ni / Au.

  The p-type ZnO layer 106 is an oxide semiconductor layer containing oxygen as a constituent element, and is formed on the flat portion 124 so as to be in contact with the side surface of the convex portion 122. The Ni / Au gate electrode 107 is formed on the p-type ZnO layer 106.

  The WSi source electrode 105 is made of WSi, is formed on the high concentration n-type InAlGaN layer 104 (above the convex portion 122 of the n-type GaN layer 103), and is formed in ohmic contact with the high concentration n-type InAlGaN layer 104. Has been. Using this WSi source electrode 105 as a mask, a p-type ZnO layer 106 and a Ni / Au gate electrode 107 are formed by a so-called self-alignment process. The Ni / Au electrode 108 located above the WSi source electrode 105 functions as a part of the source electrode. On the back surface of the n-type GaN substrate 101, a Ti / Al drain electrode 109 is formed in ohmic contact with the n-type GaN substrate 101.

  Here, the p-type ZnO layer 117 formed above the WSi source electrode 105 is a semiconductor layer made of the same material as the p-type ZnO layer 106 formed on the flat portion 124 of the n-type GaN layer 103. Similarly, the Ni / Au electrode 108 formed above the WSi source electrode 105 is an electrode made of the same material as the Ni / Au gate electrode 107 formed on the p-type ZnO layer 106.

For example, the width of the convex portion 122 of the n-type GaN layer 103 is 0.6 μm, the carrier concentration of the n-type GaN layer 103 is 1 × 10 ¹⁷ cm ⁻³ , and the carrier concentration of the p-type ZnO layer 106 is 1 × 10 ¹⁸ cm ^{−. 3} is desirable.

  In the field effect transistor having the above structure, the potential energy of the n-type GaN layer 103 is increased by the built-in potential generated by the junction of the n-type GaN layer 103 and the p-type ZnO layer 106. As a result, a depletion layer is formed in the n-type GaN layer 103 so as to cross the convex portion 122 of the n-type GaN layer 103 even when no gate voltage is applied (gate voltage 0 V), and the channel is formed by the depletion layer. Divided. Therefore, no current flows when no gate voltage is applied, and a so-called normally-off operation can be realized.

  Next, an example of the manufacturing method of the field effect transistor according to the present embodiment will be described. FIG. 2 is a cross-sectional view showing the method for manufacturing the same field effect transistor.

  First, a high concentration n-type GaN layer 102 having a thickness of 500 nm, an n-type GaN layer 103 having a thickness of 2 μm, and a thickness of 20 nm are formed on the main surface of the n-type GaN substrate 101 by MOCVD (Metal Organic Chemical Vapor Deposition). The high concentration n-type InAlGaN layer 104 is epitaxially grown sequentially (FIG. 2A).

  Subsequently, WSi is deposited on the high-concentration n-type InAlGaN layer 104 by sputtering or the like, for example, and then partially removed by dry etching to form the WSi source electrode 105 (FIG. 2B and FIG. FIG. 2 (c)).

  Subsequently, using the WSi source electrode 105 as a mask, part of the high-concentration n-type InAlGaN layer 104 and the n-type GaN layer 103 is removed by dry etching such as ICP (Inductively Coupled Plasma), for example, and a convex structure (convex portion 122). ) Is formed (FIG. 2D).

  Subsequently, after the p-type ZnO layer 106 is deposited on the flat portion 124 of the n-type GaN layer 103 by, for example, PLD (Pulsed Laser Deposition) or the like by a self-alignment process using the WSi source electrode 105 as a mask, the p-type ZnO layer 106 is deposited. A Ni / Au gate electrode 107 is deposited on the ZnO layer 106. In the formation of the p-type ZnO layer 106 and the Ni / Au gate electrode 107, the p-type ZnO layer 117 and the Ni / Au electrode 108 are formed on the WSi source electrode 105.

  Finally, a Ti / Al drain electrode 109 is formed on the back surface of the n-type GaN substrate 101 (FIG. 2 (e)).

  As described above, since the field effect transistor of this embodiment has a vertical channel structure, a high withstand voltage field effect transistor can be realized even with a small device area.

  Further, in the field effect transistor of this embodiment, the GaN layer located on the Ti / Al drain electrode 109 side from the p-type ZnO layer 106 is not exposed, so there is a problem in the field effect transistor having a lateral channel structure using GaN. Thus, a highly reliable field effect transistor can be realized without causing the current collapse phenomenon.

  In the transistor of this embodiment, the gate length can be controlled by the thickness of the p-type ZnO layer 106. Therefore, it is possible to realize a gate length of 50 nm or less, which has been difficult with a conventional field effect transistor having a lateral channel structure, without using a high-cost / low-throughput process step such as electron beam lithography. It is possible to realize a field effect transistor.

(Second Embodiment)
A field effect transistor having a vertical channel structure according to a second embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a sectional view of a field effect transistor having a vertical channel structure according to the present embodiment.
As shown in FIG. 3, the field effect transistor includes a sapphire substrate 110, an AlN buffer layer 111, a high-concentration n-type GaN layer 102, an n-type GaN layer 103, a high-concentration n-type InAlGaN layer 104, a WSi source electrode 105, p A type nickel oxide (NiO) layer 112, a Ni / Au gate electrode 107, a Ti / Al drain electrode 109, a p-type NiO layer 113, and a Ni / Au electrode 108 are provided.

  In the same field effect transistor, an AlN buffer layer 111, a high-concentration n-type GaN layer 102, an n-type GaN layer 103, and a high-concentration are formed on the main surface of the sapphire substrate 110 whose plane orientation is (0001). The n-type InAlGaN layer 104 is sequentially epitaxially grown.

  The n-type GaN layer 103 is formed on the high-concentration n-type GaN layer 102, has a flat portion 124 and a convex portion 122 on the surface, and has a carrier concentration lower than that of the high-concentration n-type GaN layer 102. It is a semiconductor layer.

The high concentration n-type InAlGaN layer 104 is selectively formed on the upper surface of the convex portion 122. The high-concentration n-type InAlGaN layer 104 is made of, for example, In _0.02 Al _0.38 Ga _0.60 N, and is formed so as to lattice match with the n-type GaN layer 103. A part of the n-type GaN layer 103 and the high-concentration n-type InAlGaN layer 104 is selectively removed, and a notch 121 having a depth of, for example, 250 nm is formed from the surface of the high-concentration n-type InAlGaN layer 104. Furthermore, a part of the n-type GaN layer 103 and the high-concentration n-type GaN layer 102 is selectively removed, and a notch 123 is formed.

  The p-type NiO layer 112 is an oxide semiconductor layer containing oxygen as a constituent element, and is formed on the flat portion 124 so as to be in contact with the side surface of the convex portion 122. The Ni / Au gate electrode 107 is formed on the p-type NiO layer 112.

  The WSi source electrode 105 is formed on the high-concentration n-type InAlGaN layer 104 (above the convex portion 122) and is in ohmic contact with the high-concentration n-type InAlGaN layer 104. Using this WSi source electrode 105 as a mask, the p-type NiO layer 112 and the Ni / Au gate electrode 107 are formed by a so-called self-alignment process. The Ni / Au electrode 108 located above the WSi source electrode 105 functions as a part of the source electrode. A Ti / Al drain electrode 109 is formed in ohmic contact with the high-concentration n-type GaN layer 102 at a portion where the notch 123 of the high-concentration n-type GaN layer 102 is formed. The Ti / Al drain electrode 109 is electrically connected to the high concentration n-type GaN layer 102.

  Here, the p-type NiO layer 113 formed above the WSi source electrode 105 is a semiconductor layer made of the same material as the p-type NiO layer 112 formed on the flat portion 124 of the n-type GaN layer 103. Similarly, the Ni / Au electrode 108 formed above the WSi source electrode 105 is an electrode made of the same material as the Ni / Au gate electrode 107 formed on the p-type NiO layer 112.

For example, the width of the protrusion 122 of the n-type GaN layer 103 is 0.6 μm, the carrier concentration of the n-type GaN layer 103 is 1 × 10 ¹⁷ cm ⁻³ , and the carrier concentration of the p-type NiO layer 112 is 1 × 10 ¹⁸ cm ^{−. 3} is desirable.

  In the field effect transistor having the above structure, the potential energy of the n-type GaN layer 103 is increased by the built-in potential generated by the junction of the n-type GaN layer 103 and the p-type NiO layer 112. As a result, a depletion layer is formed in the n-type GaN layer 103 so as to cross the convex portion 122 of the n-type GaN layer 103 even when no gate voltage is applied (gate voltage 0 V), and the channel is formed by the depletion layer. Divided. Therefore, no current flows when no gate voltage is applied, and a so-called normally-off operation can be realized.

  Next, an example of a method for manufacturing the field effect transistor according to this embodiment will be described. FIG. 4 is a cross-sectional view showing the method for manufacturing the same field effect transistor.

  First, by MOCVD, an AlN buffer layer 111 with a thickness of 30 nm, a high-concentration n-type GaN layer 102 with a thickness of 500 nm, an n-type GaN layer 103 with a thickness of 2 μm, and a thickness of 20 nm are formed on the main surface of the sapphire substrate 110. The high concentration n-type InAlGaN layer 104 is epitaxially grown sequentially.

  Subsequently, WSi is deposited on the high-concentration n-type InAlGaN layer 104 by sputtering or the like, for example, and then partially removed by dry etching to form the WSi source electrode 105 (FIG. 4A). .

  Subsequently, using the WSi source electrode 105 as a mask, part of the high-concentration n-type InAlGaN layer 104 and the n-type GaN layer 103 is removed by dry etching such as ICP to form a convex structure (convex portion 122). . Further, the n-type GaN layer 103 and a part of the high-concentration n-type GaN layer 102 are removed by etching (FIG. 4B).

  Subsequently, after the p-type NiO layer 112 is deposited on the flat portion 124 of the n-type GaN layer 103 by, for example, PLD or the like by a self-alignment process using the WSi source electrode 105 as a mask, Then, a Ni / Au gate electrode 107 is deposited (FIG. 4C). In forming the p-type NiO layer 112 and the Ni / Au gate electrode 107, the p-type NiO layer 113 and the Ni / Au electrode 108 are formed on the WSi source electrode 105.

  Finally, a Ti / Al drain electrode 109 is formed on the high-concentration n-type GaN layer 102 (FIG. 4D).

  As described above, since the field effect transistor of this embodiment has a vertical channel structure, a high withstand voltage field effect transistor can be realized even with a small device area.

(Third embodiment)
A field effect transistor having a vertical channel structure according to a third embodiment of the present invention will be described with reference to the drawings.

FIG. 5 is a sectional view of a field effect transistor having a vertical channel structure according to the present embodiment.
As shown in FIG. 5, this field effect transistor includes an n-type GaN substrate 101, a high-concentration n-type GaN layer 102, an n-type GaN layer 103, a high-concentration n-type InAlGaN layer 104, a WSi source electrode 105, a p-type GaN layer. 114, a Ni / Au gate electrode 107, a Ti / Al drain electrode 109, and a Ni / Au electrode 108.

  In the field effect transistor, a high-concentration n-type GaN layer 102, an n-type GaN layer 103, and a high-concentration n-type InAlGaN layer are formed on the main surface of an n-type GaN substrate 101 whose plane orientation is (0001). 104 are sequentially epitaxially grown. Further, a p-type GaN layer 114 is epitaxially grown on the n-type GaN layer 103.

  The n-type GaN layer 103 is formed on the high-concentration n-type GaN layer 102, has a flat portion 124 and a convex portion 122 on the surface, and has a carrier concentration lower than that of the high-concentration n-type GaN layer 102. It is a semiconductor layer.

The high concentration n-type InAlGaN layer 104 is selectively formed on the upper surface of the convex portion 122. The high-concentration n-type InAlGaN layer 104 is made of, for example, In _0.02 Al _0.38 Ga _0.60 N, and is formed so as to lattice match with the n-type GaN layer 103.

  The p-type GaN layer 114 is formed on the flat portion 124 so as to contact the side surface of the convex portion 122. The Ni / Au gate electrode 107 is formed on the p-type GaN layer 114.

  The WSi source electrode 105 is formed on the high-concentration n-type InAlGaN layer 104 (above the convex portion 122) and is in ohmic contact with the high-concentration n-type InAlGaN layer 104. Using this WSi source electrode 105 as a mask, a Ni / Au gate electrode 107 is formed by a so-called self-alignment process. The Ni / Au electrode 108 located above the WSi source electrode 105 functions as a part of the source electrode. A Ti / Al drain electrode 109 is formed on the back surface of the n-type GaN substrate 101 in ohmic contact with the n-type GaN substrate 101. The Ti / Al drain electrode 109 is electrically connected to the high concentration n-type GaN layer 102.

  Here, the Ni / Au electrode 108 formed above the WSi source electrode 105 is an electrode made of the same material as the Ni / Au gate electrode 107 formed on the p-type GaN layer 114.

For example, the width of the convex portion 122 of the n-type GaN layer 103 is 0.6 μm, the carrier concentration of the n-type GaN layer 103 is 1 × 10 ¹⁷ cm ⁻³ , and the carrier concentration of the p-type GaN layer 114 is 1 × 10 ¹⁸ cm ^{−. 3} is desirable.

  In the field effect transistor having the above structure, the potential energy of the n-type GaN layer 103 is increased by the built-in potential generated by the junction of the n-type GaN layer 103 and the p-type GaN layer 114. As a result, a depletion layer is formed in the n-type GaN layer 103 so as to cross the convex portion 122 of the n-type GaN layer 103 even when no gate voltage is applied (gate voltage 0 V), and the channel is formed by the depletion layer. Divided. Therefore, no current flows when no gate voltage is applied, and a so-called normally-off operation can be realized.

  Next, an example of the manufacturing method of the field effect transistor according to the present embodiment will be described. FIG. 6 is a cross-sectional view showing a method for manufacturing the same field effect transistor.

  First, a high-concentration n-type GaN layer 102 having a thickness of 500 nm, an n-type GaN layer 103 having a thickness of 200 nm, and a p-type GaN layer 114 having a thickness of 200 nm are formed on the main surface of the n-type GaN substrate 101 by MOCVD. Sequentially epitaxial growth is performed (FIG. 6A).

Subsequently, a part of the p-type GaN layer 114 is selectively removed by dry etching such as ICP, specifically, dry etching mainly containing chlorine (Cl ₂ ), and the opening 130 is formed. The surface of the n-type GaN layer 103 is exposed from the opening 130 (FIG. 6B).

  Subsequently, an n-type GaN layer 103 having a thickness of 2 μm and a high-concentration n-type InAlGaN layer 104 having a thickness of 20 nm are sequentially epitaxially grown by MOCVD. Further, after WSi is deposited on the high-concentration n-type InAlGaN layer 104 by sputtering or the like, for example, the WSi is partially removed by dry etching, and the WSi source electrode 105 is formed.

  Subsequently, using the WSi source electrode 105 as a mask, part of the high-concentration n-type InAlGaN layer 104 and the n-type GaN layer 103 is removed by dry etching such as ICP until the surface of the p-type GaN layer 114 is exposed. (FIG. 6C).

  Subsequently, the Ni / Au gate electrode 107 is formed on the p-type GaN layer 114 by a self-alignment process using the WSi source electrode 105 as a mask. In forming the Ni / Au gate electrode 107, the Ni / Au electrode 108 is formed above the WSi source electrode 105.

  Finally, a Ti / Al drain electrode 109 is formed on the back surface of the n-type GaN substrate 101 (FIG. 6D).

  As described above, since the field effect transistor of this embodiment has a vertical channel structure, a high withstand voltage field effect transistor can be realized even with a small device area.

  The field effect transistor and the method for manufacturing the same according to the present invention have been described above based on the embodiment. However, the present invention is not limited to this embodiment. The present invention includes various modifications made by those skilled in the art without departing from the scope of the present invention.

For example, in the above embodiment, instead of the p-type ZnO layer 106 or the p-type NiO layer 112 having a rock salt structure as the third semiconductor layer of the present invention, the constituent element contains oxygen or sulfur, and the delafossite structure or chalcogenide structure Alternatively, a semiconductor layer having a crystal structure of any one of a rock salt structure and a wurtzite structure may be used. For example, p-type copper aluminum oxide (CuAl ₂ O ₂ ), p-type strontium copper oxide (SrCu ₂ O ₂ ), p-type lanthanum copper oxide, p-type lanthanum copper selenium oxide (LaCuOSe), or p-type lanthanum A semiconductor layer made of copper sulfide (LaCuS) or the like may be used. In particular, CuAl ₂ O ₂ is a particularly preferable material because a high hole concentration (1 × 10 ¹⁸ cm ⁻³ or more) can be obtained. At this time, a semiconductor such as ZnO can be formed by a relatively simple apparatus such as a pulse laser deposition method. Furthermore, semiconductors such as ZnO can be processed by a wet etching process using acid, alkali, or the like. By using such a material, damage to the semiconductor layer due to the dry etching process can be avoided.

  In the third embodiment, the p-type GaN layer 114 is exemplified as the third semiconductor layer of the present invention, but a nitride semiconductor layer other than the GaN layer may be used.

  Moreover, in the said embodiment, although the high concentration n-type GaN layer 102 was illustrated as a 1st nitride semiconductor layer of this invention, nitride semiconductor layers other than a GaN layer may be used. In addition, although the n-type GaN layer 103 is illustrated as the second nitride semiconductor layer of the present invention, a nitride semiconductor layer having a carrier concentration lower than the carrier concentration of the first nitride semiconductor layer other than the GaN layer is used. May be.

  Moreover, in the said embodiment, although the n type was illustrated as a 1st conductivity type of this invention and a p type was illustrated as a 2nd conductivity type of this invention, each may become a reverse conductivity type. That is, the n-type GaN layer 103 and the high-concentration n-type GaN layer 102 are each an n-type semiconductor layer, and the p-type GaN layer 114 is a p-type semiconductor layer, but each has an opposite conductivity type. Also good.

  INDUSTRIAL APPLICABILITY The present invention is useful for a field effect transistor and a method for manufacturing the same, and particularly useful for a power transistor used for a power supply circuit for a consumer device and the method for manufacturing the same.

101 n-type GaN substrate 102 high-concentration n-type GaN layer 103 n-type GaN layer 104 high-concentration n-type InAlGaN layer 105 WSi source electrode 106, 117 p-type ZnO layer 107 Ni / Au gate electrode 108 Ni / Au electrode 109 Ti / Al Drain electrode 110 Sapphire substrate 111 AlN buffer layer 112, 113 p-type NiO layer 114 p-type GaN layer 121, 123 Notch 122 Projection 124 Flat part 130 Opening

Claims (7)

A first nitride semiconductor layer of a first conductivity type;
A first conductivity type second layer formed on the first nitride semiconductor layer, provided with a flat portion and a convex portion on the surface, and having a carrier concentration lower than that of the first nitride semiconductor layer. A nitride semiconductor layer of
A source electrode formed above the convex portion;
A drain electrode electrically connected to the first nitride semiconductor layer;
A third semiconductor layer of the second conductivity type formed on the flat portion so as to be in contact with the side surface of the convex portion;
A field effect transistor comprising: a gate electrode formed on the third semiconductor layer. The field effect transistor according to claim 1, wherein the third semiconductor layer contains oxygen or sulfur as a constituent element. The field effect transistor according to claim 2, wherein the third semiconductor layer has a crystal structure of any one of a delafossite structure, a chalcogenide structure, a rock salt structure, and a wurtzite structure. The field effect transistor according to claim 1, wherein the third semiconductor layer is a nitride semiconductor layer. Each of the first nitride semiconductor layer and the second nitride semiconductor layer is an n-type semiconductor layer;
The field effect transistor according to claim 1, wherein the third semiconductor layer is a p-type semiconductor layer. The field effect transistor further includes a semiconductor layer formed above the source electrode and made of the same material as the third semiconductor layer, and an electrode made of the same material as the gate electrode formed above the source electrode. The field effect transistor according to claim 1, comprising at least one of the following. Forming a first conductivity type first nitride semiconductor layer on a substrate;
A first conductivity type second nitridation having a flat portion and a convex portion provided on the surface of the first nitride semiconductor layer and having a carrier concentration lower than that of the first nitride semiconductor layer. Forming a physical semiconductor layer;
Forming a source electrode above the second nitride semiconductor layer;
Forming a drain electrode electrically connected to the first nitride semiconductor layer;
Forming a second semiconductor layer of the second conductivity type on the flat portion so as to be in contact with the side surface of the convex portion;
Forming a gate electrode on the third semiconductor layer. A method of manufacturing a field effect transistor.

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