JP2010263579A - Differential amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce an offset voltage of two transistors in an output couple, caused by increase in variation of relative precision. <P>SOLUTION: A differential amplifier circuit includes: a first Nch transistor MN1 in which an input signal INa is input to its gate; an Nch transistor MN2 in which an input signal INb is input to its gate; an Nch transistor MN3 which becomes a current source by connecting sources of the Nch transistors MN1 and MN2; a Pch transistor MP4 in which a drain of the Nch transistor MN1 and a back gate of a Pch transistor MP5 are connected to its source, and an output signal OUTb is output from its drain; and the Pch transistor MP5 in which a drain of the Nch transistor MN2 and a back gate of the Pch transistor MP4 are connected to its source, and an output signal OUTa is output from its drain. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a differential amplifier circuit, and more particularly to a cascode type differential amplifier circuit in which a grounded-gate amplifier circuit is stacked on a common-source amplifier circuit.

  In the differential amplifier circuit, if the threshold values of the two MOS transistors in a pair are not aligned, the drain voltages of both transistors are not the same, and an offset voltage is generated at the output. A differential amplifier for reducing such an offset voltage is disclosed in Patent Document 1. This differential amplifier adjusts the threshold voltage of the active load transistor of the differential amplifier circuit by the threshold voltage adjusting circuit to adjust the offset voltage. The threshold voltage adjustment circuit includes one or more resistors, one or more fuses for adjusting a combination state of the resistors, and a second current source for supplying a current to the combined resistors. Thus, a common connection point between the combined resistor and the second current source is connected to the back gate.

  Further, Patent Document 2 describes an input buffer circuit having a function of canceling an offset voltage. FIG. 4 is a circuit diagram of this input buffer circuit. Here, only the main part will be schematically described. The output signal OUTB is input to the first low-pass filter circuit, and the first low-pass filter circuit integrates the output signal OUTB for a predetermined period. The integration result is stored in the capacitor 4s as the voltage value V2a. Similarly, the output signal OUT is input to the second low-pass filter circuit, and the second low-pass filter circuit integrates the output signal OUT for the predetermined period. The integration result is stored in the capacitor 4t as the voltage value V2b. The differential amplifier circuit 5 generates and outputs appropriate voltages V3a and V3b in accordance with the design specifications of the transistors 1x and 1y by amplifying the voltage values V2a and V2b. The voltages V3a and V3b are applied to the back gates of the transistors 1x and 1y, respectively.

JP 11-31930 A JP 2004-343277 A

  The following analysis is given in the present invention.

  In the differential amplifier described in Patent Document 1, the offset voltage is adjusted by the threshold voltage adjustment circuit. However, adjustment must be performed for each differential amplifier one by one, resulting in poor productivity.

  On the other hand, although the input buffer circuit described in Patent Document 2 does not require the adjustment as described above, the offset voltage can be reduced only in a state of operating at a constant frequency. That is, although the offset voltage can be reduced for a circuit used as a clock signal, the effect of reducing the offset voltage is reduced for an input waveform whose frequency changes. The reason for this is to cancel the offset voltage after integrating the output signal that is toggled at a constant frequency for a predetermined period and storing the result in the capacitor.

  The mechanism for reducing the offset will be described in detail with reference to FIG. FIG. 5 is a diagram showing how the offset voltage is reduced in a conventional input buffer circuit. IN and INB indicate input waveforms, OUT and OUTB indicate output waveforms, and CRP and CRN indicate cross points where OUT and OUTB intersect. As shown in FIG. 5, in the data section in which IN and INB are toggled at a constant frequency in the period T1, the offset voltage cancellation functions and the two output cross points CRP and CRN become close to each other.

  On the other hand, in the input where the high frequency and the low frequency are mixed as in the period T2, the difference in the high level period or the low level period of the output waveforms OUT and OUTB is different, so the effect of reducing the offset voltage is diminished. The reason for this is that the common mode voltage of the output signals OUT and OUTB for a predetermined period (the center voltage values of the high level and the low level when the OUT and OUTB are swinging with the same minute amplitude in both the positive and negative directions) ) Is stored in the capacitors 4s and 4t as voltage values V2a and V2b, and the difference between the voltage value V2a and the voltage value V2b is reflected in the offset voltage. Therefore, if the difference between the high level period or the low level period is different for a certain time, the potential difference between V2a and V2b becomes one of the high level and the other becomes the low level voltage, and the common mode voltage of OUT and OUTB is detected. The offset voltage cannot be stored in the capacitor. For this reason, the offset voltage cannot be reduced, and the two output waveforms OUT and OUTB have a deviation in amplitude due to the offset voltage. In other words, in the conventional example, it can be applied to a clock signal that always operates at a constant frequency, but in the case of data in which high frequency and low frequency are mixed, there occurs a time during which the offset voltage cannot be reduced, resulting in a deviation between the two output amplitudes. Cross points CRP and CRN are shifted, and jitter (delay difference) increases.

  A differential amplifier circuit according to one aspect (side surface) of the present invention is a cascode type, and each transistor includes an output pair that connects a source and a back gate to each other in an output stage.

  According to the present invention, it is possible to reduce the offset voltage of the two transistors of the output pair caused by an increase in relative accuracy variation.

1 is a circuit diagram of a differential amplifier circuit according to a first example of the present invention. FIG. FIG. 6 is a circuit diagram of a differential amplifier circuit according to a second example of the present invention. FIG. 6 is a circuit diagram of a differential amplifier circuit according to a third example of the present invention. It is a circuit diagram of the conventional input buffer circuit. It is a figure which shows a mode that an offset voltage is reduced in the conventional input buffer circuit.

  The differential amplifier circuit according to the embodiment of the present invention is a cascode type, and each of the transistors (MP4 and MP5 in FIG. 1) includes an output pair in which the source and the back gate are connected to each other in the output stage.

  In the differential amplifier circuit, the input stage may be a folded type.

  In the differential amplifier circuit, the differential pair (MN1, MN2 in FIG. 1) in the input stage may be configured by Nch transistors, and the output pair (MP4, MP5 in FIG. 1) may be configured by Pch transistors.

  In the differential amplifier circuit, the differential pair at the input stage (MP1 and MP2 in FIG. 2) may be configured by Pch transistors, and the output pair (MN4 and MN5 in FIG. 2) may be configured by Nch transistors.

  In the differential amplifier circuit, the first differential pair (MN1, MN2 in FIG. 3) whose input stage is composed of Nch transistors and the second differential pair (MP1, MP2 in FIG. 3) composed of Pch transistors. The output stage is composed of an Nch transistor, and is composed of a first output pair (MN4, MN5 in FIG. 3) connected to the second differential pair, and a Pch transistor, and the first differential pair And a second output pair (MP4 and MP5 in FIG. 3) connected to each other.

  More specifically, the differential amplifier circuit includes a first transistor (MN1 in FIG. 1) that inputs a first input signal to the gate, and a second transistor (FIG. 1) that inputs a second input signal to the gate. MN2), a third transistor (MN3 in FIG. 1) that serves as a current source by connecting the sources of the first and second transistors, a drain of the first transistor, and a back gate of the fifth transistor A fourth transistor (MP4 in FIG. 1) that is connected to the source and outputs a second output signal from the drain, and a drain of the second transistor and a back gate of the fourth transistor are connected to the source and connected from the drain. And a fifth transistor (MP5 in FIG. 1) that outputs a first output signal, wherein the first, second, and third transistors and the fourth and fifth transistors have opposite conductivity types. Rukoto is preferable.

  According to the differential amplifier circuit as described above, each transistor of the output pair connects (crosses) the source and the back gate of each other, so that the output pair generated due to the increase in relative accuracy variation The offset voltage (Vt offset) of the two transistors can be reduced. Further, it is not necessary to adjust each differential amplifier circuit, and the productivity is excellent.

  Hereinafter, it will be described in detail with reference to the drawings in accordance with embodiments.

  FIG. 1 is a circuit diagram of a differential amplifier circuit according to a first embodiment of the present invention. In FIG. 1, the differential amplifier circuit includes Nch transistors MN1, MN2, and MN3, Pch transistors MP4 and MP5, and resistance elements R1 to R4.

  The Nch transistor MN1 has a drain connected to the node N1, a source connected to the drain of the Nch transistor MN3, and an input signal INa input to the gate. The Nch transistor MN2 has a drain connected to the node N2, a source connected to the drain of the Nch transistor MN3, and an input signal INb input to the gate. The Nch transistor MN3 grounds the source, applies a bias voltage Vb1 to the gate, and functions as a current source for the Nch transistors MN1 and MN2.

  In the Pch transistor MP4, the source which is the node N1 is connected to the power supply VDD via the resistor element R3, the drain is connected to the output terminal of the output signal OUTb and grounded via the resistor element R1, and the back gate is connected to the node N2. The bias voltage Vb2 is applied to the gate. In the Pch transistor MP5, the source which is the node N2 is connected to the power supply VDD via the resistor element R4, the drain is connected to the output terminal of the output signal OUTa and grounded via the resistor element R2, and the back gate is connected to the node N1. The bias voltage Vb2 is applied to the gate.

  The differential amplifier circuit configured as described above is configured as a folded (folded) cascode circuit, amplifies the input signal INa, and outputs it as an in-phase output signal OUTa. The input signal INb is amplified and output as an in-phase output signal OUTb.

  In the Pch transistors MP4 and MP5 which are output pairs of such a folded cascode circuit, when a difference occurs in the current drive capability of the transistors due to relative accuracy, an offset voltage due to a change in threshold voltage The action of suppressing (Vt offset) works.

  For example, it is assumed that the threshold of the Pch transistor MP4 is lowered and the threshold of the Pch transistor MP5 is raised. In this case, the drive capability of the Pch transistor MP4 is relatively higher than that of the Pch transistor MP5, and the potential of the source (node N1) of the Pch transistor MP4 is lower than that of the Pch transistor MP5 (node N2). Simply in this state, the difference in delay between the rising edge and the falling edge of the signal at the output terminal also becomes large due to the difference in driving capability between the Pch transistors MP4 and MP5.

  On the other hand, in the differential amplifier circuit of FIG. 1, the back gate of the Pch transistor MP4 and the source of the paired Pch transistor MP5 are connected. When the driving capability of the Pch transistor MP4 increases, the equivalent resistance of the Pch transistor MP4 decreases, so that a large amount of current flows and the potential of the source (node N1) of the Pch transistor MP4 is higher than that of the source of the Pch transistor MP5 (node N2). Also lower. Since the node N1 having a relatively low potential compared to the node N2 is connected to the back gate of the Pch transistor MP5 having a low driving capability, the Pch transistor MP5 has a low substrate bias voltage, and a channel is easily formed. Become. Therefore, the threshold voltage of the Pch transistor MP5 decreases, and the drive capability of the Pch transistor MP5 becomes relatively large.

  On the other hand, since the Pch transistor MP4 having a large driving capability connects the node N2 having a relatively high potential to the back gate, the substrate bias voltage of the Pch transistor MP4 becomes high and it is difficult to form a channel. Therefore, the threshold voltage of the Pch transistor MP4 increases, and the drive capability of the Pch transistor MP4 decreases.

  In this way, when there is a relative difference in driving capability due to the difference in threshold voltage between the Pch transistors MP4 and MP5, control is performed so that the difference in driving capability between the Pch transistors MP4 and MP5 is reduced by connecting the back gate and the source. Is done. As a result, the delay difference (jitter) between the rise and fall of the signal at the output end is reduced.

  That is, the folded cascode circuit of the present embodiment is configured such that the back gate of the output transistor of the differential output section is connected to the source of the transistor paired with the cross, so that the capacitive element (integrator circuit) and the differential AMP are connected. The potential difference caused by the relative accuracy is instantaneously fed back to the back gate without going through. Therefore, even when the output frequency described in the conventional example is high and low, the relative capability difference is instantaneously reduced between the differential pair of transistors, and the transistor offset voltage is reduced. Can be reduced. As a result, the potential difference between the high and low levels at the outputs of the two transistors is reduced, and the delay difference between the rise and fall is reduced, so that the jitter characteristics are improved.

  FIG. 2 is a circuit diagram of a differential amplifier circuit according to a second embodiment of the present invention. In FIG. 2, the differential amplifier circuit includes Pch transistors MP1, MP2, and MP3, Nch transistors MN4 and MN5, and resistance elements R5 to R8. The differential amplifier circuit of this embodiment includes Nch transistors MN1, MN2, MN3, Pch transistors MP4, MP5, and resistance elements R1 to R4 in the differential amplifier circuit of FIG. 1, and Pch transistors MP1, MP2, MP3, Nch transistors, respectively. It is replaced with MN4, MN5 and resistance elements R5 to R8, and the power supply VDD and ground are replaced. That is, the differential amplifier circuit of this embodiment is a folded cascode circuit in which the input stage is configured by a Pch transistor pair and the output stage is configured by an Nch transistor pair. On the other hand, the conductivity type of the transistor is inverted. The operation is the same as in the first embodiment, and the offset voltages of the paired Nch transistors MN4 and MN5 are reduced.

  The differential amplifier circuit of this embodiment is effective when the amplitude center voltage of the input signals INa and INb is low because the Pch transistor is used in the first stage for inputting the input signals INa and INb.

  FIG. 3 is a circuit diagram of a differential amplifier circuit according to a third embodiment of the present invention. The differential amplifier circuit of the third embodiment is a folded cascode circuit including an Nch transistor pair and a Pch transistor pair whose output stages are vertically stacked. 3, the same reference numerals as those in FIGS. 1 and 2 represent the same items, and the description thereof is omitted.

  The input signal INa is supplied in common to the gates of the Pch transistor MP1 and the Nch transistor MN1. The input signal INb is supplied in common to the gates of the Pch transistor MP2 and the Nch transistor MN2. The drains of the Pch transistor MP4 and the Nch transistor MN4 are connected in common and output an output signal OUTb. The drains of the Pch transistor MP5 and the Nch transistor MN5 are connected in common and output the output signal OUTa.

  Similar to the first and second embodiments, the differential amplifier circuit having such a configuration has a pair of Pch transistors MP5, MP4, and Nch transistor MN5 that are paired with each of the back gates of the Pch transistors MP4 and MP5 and Nch transistors MN4 and MN5. By cross-connecting with the source of MN4, the substrate of the transistor is biased forward or backward to increase or decrease the driving capability of the transistor. Therefore, it is possible to relatively reduce the driving capability difference in the transistors forming the output pair, and to reduce the offset voltage in the transistors.

  According to the differential amplifier circuit of the third embodiment, when the amplitude center voltage of the input signal is low (near ground) in the first stage that receives the input signal, the Pch transistors MP1 and MP2 function, When the amplitude center voltage is high (in the vicinity of VDD), the Nch transistors MN1 and MN2 function. Therefore, the input signal operates satisfactorily over a wide operation range from a low voltage to a high voltage.

  In the differential amplifier circuits of the first to third embodiments, the resistance element may be configured by a current source such as a current mirror.

  According to the differential amplifier circuits of the first to third embodiments as described above, the respective back gates of the transistors forming the pair of the differential output sections are connected to the sources of the respective transistors forming a pair. Thus, the drive capability difference in the transistor can be relatively reduced. Therefore, the offset voltage that increases due to the variation in relative accuracy can be reduced in the output of the folded cascode circuit.

  It should be noted that the disclosures of the aforementioned patent documents and the like are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

MN1-MN5 Nch transistors MP1-MP5 Pch transistors N1-N4 Nodes R1-R8 Resistance elements

Claims (6)

Cascode type,
A differential amplifier circuit comprising: an output stage including an output pair in which each transistor connects a source and a back gate to each other.   2. The differential amplifier circuit according to claim 1, wherein the input stage is a folded type.   3. The differential amplifier circuit according to claim 2, wherein the differential pair of the input stage is composed of an Nch transistor and the output pair is composed of a Pch transistor.   3. The differential amplifier circuit according to claim 2, wherein the differential pair of the input stage is composed of a Pch transistor and the output pair is composed of an Nch transistor. The input stage comprises a first differential pair composed of Nch transistors and a second differential pair composed of Pch transistors,
The output stage includes an Nch transistor and includes a first output pair connected to the second differential pair, and a second output pair configured of a Pch transistor and connected to the first differential pair. The differential amplifier circuit according to claim 2. A first transistor for inputting a first input signal to a gate;
A second transistor for inputting a second input signal to the gate;
A third transistor that serves as a current source by connecting the sources of the first and second transistors;
A fourth transistor that connects a drain of the first transistor and a back gate of the fifth transistor to a source and outputs a second output signal from the drain;
A fifth transistor that connects a drain of the second transistor and a back gate of the fourth transistor to a source and outputs a first output signal from the drain;
With
6. The differential amplifier circuit according to claim 3, wherein the first, second, and third transistors and the fourth and fifth transistors have opposite conductivity types.

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