JP2010263169A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device allowing a small gate length to be processed. <P>SOLUTION: One form of this method of manufacturing a semiconductor device includes the steps of: forming a silicon oxide film 34 on a silicon substrate 2; forming a polycrystalline silicon film 35a having a predetermined width T1 on the oxide film 34; oxidizing at least both sides of the polycrystalline silicon film 35a; etching the oxide film 34 along with the oxidized parts of the polycrystalline silicon film 35a to leave a part of the oxide film 34 having a width smaller than the predetermined width T1 under the polycrystalline silicon film 35a; implanting ions of impurities in the parts of the silicon substrate 2 on both sides of the polycrystalline silicon film 35a by using, as a mask, the polycrystalline silicon film 35a with the oxidized parts etched to form sidewall insulation films 14 on both sides of the polycrystalline silicon film 35a; and implanting ions of impurities in the parts of the silicon substrate 2 on both side of the polycrystalline silicon film 35a by using, as a mask, the polycrystalline silicon film 35a with the sidewall insulation films 14 formed thereon. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Conventionally, a semiconductor device is manufactured using a fine processing technique. The miniaturization of a semiconductor device is used, for example, for the purpose of improving the operation speed or reducing power consumption.

  The lower limit of the fine processing is determined mainly by the resolving power of the exposure apparatus used. Therefore, the lower limit of fine processing can be further reduced by newly introducing an exposure apparatus having a higher resolving power.

  On the other hand, a technique for reducing the length of the gate oxide film by reducing the gate oxide film of the MOS transistor by etching without depending on the resolution of the exposure apparatus is disclosed (Patent Document 2). Also disclosed is a technique for reducing the gate length by etching the gate oxide film and reducing the length of the gate oxide film, and then etching the silicon in the gate electrode and the source / drain region (Patent Document 1).

  When the gate length of the MOS transistor is reduced, the on-resistance is reduced together with the amount of charge necessary for driving the transistor, so that side effects caused by driving the transistor at high speed can be suppressed.

Japanese Patent Laid-Open No. 3-16266 Japanese Patent Laid-Open No. 8-32055

  However, in the conventional technique in which the gate oxide film of the transistor is reduced by etching and the gate oxide film is miniaturized, even if the length of the gate oxide film is reduced, the space between the source region and the drain region is not reduced. In some cases, the gate length, which is the distance between the source region and the drain region, is not reduced. In addition, when etching the gate oxide film to reduce the length of the gate oxide film and then etching the silicon in the gate electrode and the source / drain region to reduce the gate tone, there is no etching stop material (selective etching process). However, because it is a time-controlled etching process, fluctuations in the gate length dimension are likely to increase, and since the silicon in the source / drain region is etched, fluctuations in the effective channel length are also likely to increase. In some cases, it was difficult to apply to the device process.

  It is an object of the present specification to provide a method of manufacturing a semiconductor device that enables processing with a short gate length without depending on the resolution of an exposure apparatus and has a small gate length dimensional fluctuation.

  In order to solve the above problems, according to one embodiment of a method for manufacturing a semiconductor device disclosed in this specification, a step of forming an oxide film on a substrate, and polycrystalline silicon having a predetermined width on the oxide film Forming a film; oxidizing the substrate surface to oxidize at least a side portion of the polycrystalline silicon film; and a portion of the oxide film having a width smaller than the predetermined width. Etching the oxide film together with the oxidized portion of the polycrystalline silicon film so as to remain under the polycrystalline silicon film.

  According to one embodiment of the semiconductor device manufacturing method described above, a short gate length can be processed without depending on the resolving power of the exposure apparatus.

  The objects and advantages of the invention will be realized and obtained by means of the elements and combinations particularly pointed out in the appended claims.

  Both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention as claimed. Further, the technical scope of the present invention is not limited to the embodiments described later, but extends to the invention described in the claims and equivalents thereof.

It is sectional drawing which shows one Embodiment of the semiconductor device disclosed to this specification. FIG. 2 is an enlarged cross-sectional view of the P-channel MOS transistor of FIG. It is FIG. (1) explaining the process of the manufacturing method of the semiconductor device disclosed to this specification. It is FIG. (2) explaining the process of the manufacturing method of the semiconductor device disclosed to this specification. It is FIG. (The 3) explaining the process of the manufacturing method of the semiconductor device disclosed to this specification. FIG. 6 is a diagram (part 4) for explaining a process of the method of manufacturing a semiconductor device disclosed in this specification. It is FIG. (5) explaining the process of the manufacturing method of the semiconductor device disclosed to this specification. It is FIG. (6) explaining the process of the manufacturing method of the semiconductor device disclosed to this specification. It is FIG. (7) explaining the process of the manufacturing method of the semiconductor device disclosed to this specification. It is FIG. (8) explaining the process of the manufacturing method of the semiconductor device disclosed to this specification. It is FIG. (9) explaining the process of the manufacturing method of the semiconductor device disclosed to this specification. It is FIG. (10) explaining the process of the manufacturing method of the semiconductor device disclosed to this specification. It is FIG. (The 11) explaining the process of the manufacturing method of the semiconductor device disclosed to this specification. It is FIG. (12) explaining the process of the manufacturing method of the semiconductor device disclosed to this specification. It is FIG. (13) explaining the process of the manufacturing method of the semiconductor device disclosed to this specification. It is FIG. (14) explaining the process of the manufacturing method of the semiconductor device disclosed to this specification. It is FIG. (15) explaining the process of the manufacturing method of the semiconductor device disclosed to this specification. FIG. 16 is an enlarged cross-sectional view of a main part in the steps of FIGS. It is sectional drawing which shows the P channel transistor of the modified example of embodiment of the semiconductor device disclosed to this specification. It is a figure which shows the relationship between the oxidation time of a polycrystalline silicon film, and an oxide film thickness. It is a figure which shows the relationship between the etching time of an oxide film, and the etching amount. It is a figure which shows the relationship between the thermal oxidation time of a polycrystalline-silicon film, and the gate reduction length of an oxide film.

  Hereinafter, a preferred embodiment (hereinafter also referred to as this embodiment) of a semiconductor device disclosed in this specification will be described with reference to FIGS.

  FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device disclosed in this specification. FIG. 2 is an enlarged cross-sectional view of the P-channel MOS transistor of FIG.

  The semiconductor device 1 of this embodiment includes a p-type silicon substrate 2, an N well 3 formed by diffusing n-type impurities on the silicon substrate 2, and a P well 4 formed by diffusing p-type impurities. Have Each of the N well 3 and the P well 4 is surrounded by an element isolation insulating film 32.

  A buried diffusion region 5 in which n-type impurities are diffused is formed around the N well 3 so as to surround the N well 3 in plan view as a channel stop region. Similarly, a buried diffusion region 6 in which p-type impurities are diffused is formed around the P well 4 so as to surround the P well 4 in plan view.

  In N well 3, a P channel MOS transistor 10 is arranged.

  As shown in FIG. 2, the P-channel MOS transistor 10 includes a gate insulating film 11, a gate 12, a source / drain extension region 13 in which a p-type impurity is diffused at a low concentration, a sidewall insulating film 14, and a p-type. And a source / drain region 14 in which impurities are diffused.

  As shown in FIG. 2, the gate 12 is formed on the gate insulating film 11. The gate 12 extends outwardly from the bonding surface with the gate oxide film 11 toward the opposite surface of the bonding surface, and then has a constant width, and both sides are undercut. This undercut portion is curved in a concave shape toward the outside. The gate 12 has a width T1. The width T1 is a dimension of a portion where the gate width is constant.

  The gate insulating film 11 has a width T2 that is narrower than the width T1.

  A silicide layer 16b functioning as a gate electrode is disposed on the gate 12.

  The source / drain extension region 13 is formed on the surface portion of the silicon substrate 2 outside the gate insulating film 11.

  Sidewall insulating film 14 is formed so as to cover the side walls of gate 12 and gate oxide film 11.

  The source / drain region 15 is formed on the surface portion of the silicon substrate 2 outside the sidewall insulating film 14. A silicide layer 16a functioning as a source / drain electrode is disposed on the source / drain region 15.

  In N well 3, an N well contact region 17 serving as a back gate of P channel MOS transistor 10 is arranged. The contact region 17 has an N-type impurity diffusion layer 18 and a silicide layer 16c disposed thereon.

  As shown in FIG. 1, an N channel MOS transistor 20 is arranged in the P well 4. N channel MOS transistor 20 has the same structure as P channel MOS transistor 10 shown in FIG.

  Specifically, the N-channel MOS transistor 20 includes a gate insulating film 21, a gate 22, a source / drain extension region 23 in which an n-type impurity is diffused at a low concentration, a sidewall insulating film 24, and an n-type impurity. And diffused source / drain regions 25. The gate 22 has a width T1, and the gate insulating film 21 has a width T2.

  The N-channel MOS transistor 20 includes a silicide layer 26a that functions as a source electrode / drain electrode and a silicide layer 26b that functions as a gate electrode.

  P well contact region 27 serving as a back gate of N channel MOS transistor 20 is arranged in P well 4. The contact region 27 has a P-type impurity diffusion layer 28 and a silicide layer 26c disposed thereon.

  The first insulating film 37 is disposed so as to cover the P-channel MOS transistor 10, the N-channel MOS transistor 20, the contact regions 17 and 27, and the element isolation insulating film 32.

  Further, the second insulating film 38 is disposed so as to cover the first insulating film 37. Furthermore, the third insulating film 39 is disposed so as to cover the second insulating film 38. The upper surface of the third insulating film 39 is formed flat. Thereafter, the transistor is completed (not shown) through a general semiconductor integrated circuit wiring formation process.

  According to the semiconductor device 1 of the present embodiment described above, the gate length, which is the distance between the source extension region and the drain extension region, is shorter than the gate width T1. Since the transistors 10 and 20 have a short gate length, the on-resistance is reduced together with the amount of electric charge required for driving the transistors 10 and 20, so that side effects caused by driving the transistors 10 and 20 at high speed can be suppressed. Therefore, the transistors 10 and 20 can be driven at high speed.

  Next, a preferred embodiment (hereinafter also referred to as this embodiment) of the above-described method for manufacturing a semiconductor device will be described below with reference to FIGS.

  First, as shown in FIG. 3, a silicon oxide film as a protective film 30 is formed on the p-type silicon substrate 2. The protective film 30 functions to alleviate stress associated with deformation of the silicon nitride film when an element isolation insulating film described later is formed, or to prevent damage to the silicon substrate during ion implantation. Although the thickness of the protective film 30 can be set as appropriate, in this embodiment, the thickness is 5 nm.

  Then, a silicon nitride film 31 is formed on the protective film 30. The silicon nitride film 31 is used when an element isolation insulating film described later is formed. Although the thickness of the silicon nitride film 31 can be set as appropriate, in this embodiment, it is set to 100 nm.

  Next, as shown in FIG. 4, the silicon nitride film 31 and the protective film 30 are patterned by using a photolithography technique.

  Then, a silicon oxide film as the protective film 30a is formed in the portion where the silicon nitride film 31 and the protective film 30 are removed. Although the thickness of the protective film 30a can be set as appropriate, in this embodiment, the thickness is 15 nm.

  Next, a photoresist film (not shown) is formed on the entire surface by spin coating. Then, using a photolithography technique, a photoresist film (not shown) having an opening in a region for forming the N well is formed.

  Then, n-type impurities are ion-implanted into the silicon substrate 2 using the photoresist film as a mask. Thereafter, the photoresist film is removed.

In this embodiment, phosphorus is used as the n-type impurity. In this embodiment, the incident energy of phosphorus ions is 200 keV, and the ion implantation density is 4.0E12 cm ⁻² .

  Then, the silicon substrate 2 is annealed, and the implanted phosphorus atoms are diffused and activated. In this way, an N well 3 is formed as shown in FIG.

  Next, a photoresist film (not shown) is formed on the entire surface by spin coating. Then, using a photolithography technique, a photoresist film (not shown) having an opening in a region where an n-type impurity buried diffusion region is formed is formed.

  Then, n-type impurities are ion-implanted into the silicon substrate 2 using the photoresist film as a mask. Thereafter, the photoresist film is removed.

In this embodiment, phosphorus is used as the n-type impurity. In this embodiment, the incident energy of phosphorus ions is 45 keV, and the ion implantation density is 1.5E13 cm ⁻² . In this way, as shown in FIG. 6, the buried diffusion region 5 is formed around the N well 3.

Using the same process, boron ions are ion-implanted into the silicon substrate 2 to form a p-type impurity buried diffusion region 6 as shown in FIG. In this embodiment, the incident energy of boron ions is 30 keV, and the ion implantation density is 9.0E13 cm ⁻² .

  Next, as shown in FIG. 7, a silicon oxide film as the element isolation insulating film 32 is formed by thermal oxidation in the portion where the protective film 30a is formed. The protective film 30 a that is a silicon oxide film is integrated with the element isolation insulating film 32. The element isolation insulating film 32 is not selectively formed in a portion where the silicon nitride film 32 is formed. The element isolation insulating film 32 is a so-called field oxide film.

  In the present embodiment, the element isolation insulating film 32 is formed at a temperature of 1000 ° C. in an atmosphere containing oxygen. Although the thickness of the element isolation insulating film 32 can be set as appropriate, in this embodiment, the thickness is set to 400 nm. Further, the impurities in the buried diffusion region 6 are diffused by this thermal oxidation.

  Then, after the silicon nitride film 32 and the protective film 30 formed between the element isolation insulating films 32 are removed, a silicon oxide film as the protective film 33 is formed in the removed portion. In the present embodiment, the protective film 33 is formed at a temperature of 950 ° C. in an atmosphere containing oxygen. Although the thickness of the protective film 33 can be set as appropriate, in this embodiment, it is 30 nm.

  Next, a photoresist film (not shown) is formed on the entire surface by spin coating. Then, using a photolithography technique, a photoresist film (not shown) having an opening in a region for forming the P well is formed.

  Then, p-type impurities are ion-implanted into the silicon substrate 2 using the photoresist film as a mask. Thereafter, the photoresist film is removed.

In this embodiment, boron is used as the p-type impurity. In this embodiment, the incident energy of boron ions is set to 160 keV, and the ion implantation density is set to 8.0E12 cm ⁻² . In this way, as shown in FIG. 8, the P well 4 is formed in the region inside the buried diffusion region 6.

  Next, after the protective film 33 is removed, as shown in FIG. 9, a silicon oxide film 34 is formed on the silicon substrate 2 where the element isolation insulating film 32 is not formed. This silicon oxide film 34 will later constitute the gate oxide film 11.

  In the present embodiment, the silicon oxide film 34 is formed at a temperature of 1000 ° C. in an atmosphere containing oxygen. Although the thickness of the silicon oxide film 34 can be set as appropriate, in this embodiment, it is 15 nm.

  Then, a polycrystalline silicon film 35 doped with impurities is formed on the entire surface. The polycrystalline silicon film 35 forms a gate later. The thickness of the polycrystalline silicon film 35 can be set as appropriate, but is set to 300 nm in the present embodiment.

  Then, a silicon oxide film as the protective film 36 is formed so as to cover the polycrystalline silicon film 35. In the present embodiment, the protective film 36 is formed at a temperature of 950 ° C. in an atmosphere containing oxygen. Although the thickness of the protective film 36 can be set as appropriate, in this embodiment, it is 30 nm.

  Next, a photoresist film (not shown) is formed on the entire surface by spin coating. Then, using a photolithography technique, a photoresist film (not shown) having an opening in the N well 3 region is formed.

  A p-type impurity for controlling the threshold voltage of the transistor is ion-implanted into the surface region of the N well 3 using the photoresist film as a mask. Thereafter, the photoresist film is removed.

In this embodiment, boron is used as the p-type impurity. In this embodiment, the incident energy of boron ions is 110 keV, and the ion implantation density is 1.0E12 cm ⁻² . In this way, p-type impurities are implanted into the surface region of the N well 3.

  Then, as shown in FIG. 10, an oxide film is deposited on the protective film 36 to increase the film thickness. In the present embodiment, the thickness of the protective film 36 that is a silicon oxide film is increased to 150 nm.

  Next, as shown in FIGS. 11 and 18A, the protective film 36 and the polycrystalline silicon film 35 are patterned by using the photolithography technique, and the protective film 36a and the polycrystalline silicon film 35a are stacked. The body 10a is formed on the silicon oxide film 34. Both the protective film 36a and the polycrystalline silicon film 35a have a predetermined width T3. The polycrystalline silicon film 35a forms the gate 12 later.

  As shown in FIG. 18A, the polycrystalline silicon film 35a is bonded to the silicon oxide film 34 via the bonding surface J1. The polycrystalline silicon film 35a is bonded to the protective film 36a via the bonding surface J2. The joint surface J2 is a surface facing the joint surface J1.

  At the same time, a stacked body 20a in which a protective film 36b having a predetermined width T3 and a polycrystalline silicon film 35b are stacked is formed on the silicon oxide film 34. The polycrystalline silicon film 35b forms the gate 22 later.

Next, an oxidation process is performed on the surface of the silicon substrate 2. As this oxidation treatment method, a thermal oxidation method, a plasma oxidation method using O ₂ gas or O ₃ gas, a chemical oxidation method using an acidic solution, or the like can be used.

  In this embodiment, a thermal oxidation method is used. Details of this thermal oxidation method will be described later.

  Then, as shown in FIGS. 12 and 18B, both side portions of the polycrystalline silicon film 35a and the surface portion of the silicon substrate 2 are thermally oxidized. By this thermal oxidation, the silicon oxide film 34 grows so as to wrap the polycrystalline silicon film 35a from both sides.

  As shown in FIG. 18B, the side portion of the thermally oxidized polycrystalline silicon film 35a is oxidized inward with respect to the side surface before oxidation indicated by the dotted line P. In addition, on the side portion of the oxidized polycrystalline silicon film 35a, a silicon oxide film grows outward with respect to the side surface before oxidation indicated by the dotted line P.

  Further, as shown in FIG. 18B, both sides of the polycrystalline silicon film 35a are more than other parts along the silicon oxide film 34 located between the N well 3 and the polycrystalline silicon film 35a. Is also deeply oxidized inward. This is because both the supply of silicon from the polycrystalline silicon film 35a and the silicon substrate 2 and the supply of oxygen through the silicon oxide film 34 are abundant at the junction surface J1 between the polycrystalline silicon film 35a and the silicon oxide film 34. It is.

  The oxidized polycrystalline silicon film 36a extends outward from the joint surface J1 with the silicon oxide film 34 toward the facing surface J2 of the joint surface J1. As a result, the polycrystalline silicon film 36a has a shape in which both sides thereof are undercut. This undercut portion is curved in a concave shape toward the outside.

  The surface portion of the silicon substrate 2 on which the N well 3 is formed is also thermally oxidized inward with respect to the surface before oxidation indicated by the dotted line Q. On the oxidized surface portion of the silicon substrate 2, a silicon oxide film grows outward from the surface before oxidation indicated by the dotted line Q. As a result, the portion of the N well 3 facing the polycrystalline silicon film 36a has a convex shape toward the polycrystalline silicon film 36a.

  At the same time, also on the P well 4, as shown in FIG. 12, both sides of the polycrystalline silicon film 35b and the surface portion of the silicon substrate 2 are thermally oxidized.

  Next, as shown in FIGS. 13 and 18C, the silicon oxide film 34 is etched to form the gate oxide film 11 and the gate 12.

  Specifically, the silicon oxide film 34 is etched so that a portion of the silicon oxide film 34 having a width T2 narrower than the predetermined width T3 is left under the polycrystalline silicon film 35a. Further, by this etching, the oxidized portion of the polycrystalline silicon film 35a, which is a part of the oxide film 34, and the oxidized portion of the silicon substrate 2 are simultaneously etched.

  Specifically, the oxidized portion of the polycrystalline silicon film 35a is etched and extends outward from the joint surface J1 with the silicon oxide film 34 toward the facing surface J2 of the joint surface J1. After that, the width is formed constant. In this way, the gate 12 having the width T1 is formed. Here, the width T1 is a dimension of a portion where the width of the gate 12 is constant. The width T1 is adjusted by appropriately setting the oxide film thickness of the polycrystalline silicon film having the width T3 (see FIG. 11).

  The silicon oxide film 34 is etched to form the gate oxide film 11 having a width T2. The width T2 is appropriately adjusted by adjusting the etching amount of the silicon oxide film 34.

  As the etching method of the silicon oxide film 34, anisotropic etching or isotropic etching can be used. Examples of anisotropic etching include dry etching or wet etching using an alkaline solution. Examples of the isotropic etching include wet etching using an acidic solution.

  In this embodiment, isotropic etching using wet etching is used. In isotropic etching using wet etching, the oxidized portion on the side of the polycrystalline silicon film 35a and the oxidized portion on the surface of the silicon substrate 2 are etched at substantially the same etching rate. Further, since the etching solution also enters the inside of the undercut portion of the polycrystalline silicon film 35a, the gate oxide film 11 can be etched with good shape accuracy. At this time, since the polycrystalline silicon film 35a has an undercut shape, the supply of the etching solution to the portion between the silicon substrate 2 and the polycrystalline silicon film 35a and the diffusion of the etching products are improved. Therefore, the gate oxide film 11 is formed with high processing accuracy.

  Details of preferable wet etching conditions for isotropic etching will be described later.

  At the same time, the gate oxide film 21 and the gate 22 are also formed on the P well 4.

  Then, a silicon oxide film as a protective film (not shown) is formed on the entire surface. The thickness of this protective film can be set as appropriate, but in this embodiment, it is 5 nm.

  Next, a photoresist film (not shown) is formed on the entire surface by spin coating. Then, using a photolithography technique, a photoresist film (not shown) having an opening in a region for forming the P-channel MOS transistor in the N well 3 is formed.

  Then, in the opening of the photoresist film, p-type impurities are ion-implanted into portions of the silicon substrate 2 on both sides of the gate 12 using the gate 12 which is a polycrystalline silicon film etched in the oxidized portion as a mask. Thereafter, the photoresist film is removed.

In this embodiment, boron difluoride is used as the p-type impurity. In the present embodiment, the incident energy of boron difluoride ions is 20 keV, and the ion implantation density is 1.0E13 cm ⁻² .

  In this way, the source / drain extension regions 13 are formed in a self-aligned manner as shown in FIGS.

  The polycrystalline silicon film forming the gate 12 is reduced in width from the width T3 to the width T1 as the gate oxide film 11 is reduced by wet etching after thermal oxidation. The gate 12 has a shape in which both sides are undercut. Accordingly, the p-type impurity is ion-implanted to just outside the gate oxide film 11.

  Subsequently, a photoresist film (not shown) is formed on the entire surface by spin coating. Then, using a photolithography technique, a photoresist film (not shown) having an opening in the region where the N channel MOS transistor of the P well 4 is to be formed is formed.

  In the opening of the photoresist film, n-type impurities are ion-implanted into portions of the silicon substrate 2 on both sides of the gate 22 using the gate 22 which is a polycrystalline silicon film etched in the oxidized portion as a mask. Thereafter, the photoresist film is removed.

In this embodiment, phosphorus is used as the n-type impurity. In this embodiment, the incident energy of phosphorus ions is 20 keV, and the ion implantation density is 2.0E13 cm ⁻² .

  In this manner, as shown in FIGS. 14 and 18D, the source / drain extension region 23 is formed in a self-aligned manner.

  The width of the polycrystalline silicon film forming the gate 22 is reduced from the width T3 to the width T1 as the gate oxide film 21 is reduced by wet etching after thermal oxidation. Further, the gate 22 has a shape in which both sides are undercut. Therefore, the n-type impurity is also ion-implanted to just outside the gate oxide film 21.

  Next, a silicon oxide film is formed by a CVD method, and this silicon oxide film is etched to form sidewall insulating films on both sides of the gate 12 which is a polycrystalline silicon film, as shown in FIGS. 14 is formed. At the same time, sidewall insulating films 24 are formed on both sides of the gate 22.

  Then, a silicon oxide film as a protective film (not shown) is formed on the entire surface. The thickness of this protective film can be set as appropriate, but in this embodiment, it is 5 nm.

  Next, a photoresist film (not shown) is formed on the entire surface by spin coating. Then, using a photolithography technique, a photoresist film (not shown) having an opening in a region for forming the P-channel MOS transistor and the P-well contact region in the N well 3 is formed.

  Then, p-type impurities are ion-implanted into the portions of the silicon substrate 2 on both sides of the gate 12 using the gate 12 which is a polycrystalline silicon film on which the sidewall insulating film 14 is formed as a mask in the opening of the photoresist film. Thereafter, the photoresist film is removed.

In this embodiment, boron difluoride is used as the p-type impurity. In the present embodiment, the incident energy of boron difluoride ions is set to 20 keV, and the ion implantation density is set to 3.0E15 cm ⁻² .

  In this way, as shown in FIG. 16, the source / drain regions 15 are formed in a self-aligned manner. Further, an impurity diffusion layer 28 is formed.

  Subsequently, a photoresist film (not shown) is formed on the entire surface by spin coating. Then, using a photolithography technique, a photoresist film (not shown) having an opening in the region for forming the N channel MOS transistor and the N well contact region of the P well 4 is formed.

  Then, n-type impurities are ion-implanted into the portions of the silicon substrate 2 on both sides of the gate 22 using the gate 22 which is a polycrystalline silicon film on which the sidewall insulating film 24 is formed as a mask in the opening of the photoresist film. Thereafter, the photoresist film is removed.

In this embodiment, arsenic is used as the n-type impurity. In this embodiment, the incident energy of arsenic ions is 30 keV, and the ion implantation density is 1.0E15 cm ⁻² .

  In this way, as shown in FIG. 16, the source / drain regions 25 are formed in a self-aligned manner. Further, an impurity diffusion layer 18 is formed.

  Next, a titanium film (not shown) is formed on the entire surface by sputtering. Although the thickness of the titanium film can be set as appropriate, in the present embodiment, the thickness is 33 nm. Then, annealing is performed to react silicon atoms and titanium atoms on the surface of the silicon substrate 2, and then silicon atoms and unreacted titanium atoms are removed. In this embodiment, this annealing is performed at a temperature of 750 ° C. and a time of 90 seconds.

  Further, by further annealing, the silicon atoms on the surface of the source / drain region 15 are reacted with the titanium atoms of the titanium film to form the silicide layer 16a. Further, the silicon layer on the surface of the gate 12 and the titanium atom in the titanium film are reacted to form the silicide layer 16b. Further, the silicon atoms on the surface of the impurity diffusion layer 17 and the titanium atoms in the titanium film are reacted to form the silicide layer 16c. In this embodiment, this annealing is performed at a temperature of 850 ° C. and a time of 30 seconds.

  At the same time, silicon atoms on the surface of the source / drain region 25 are reacted with titanium atoms in the titanium film to form the silicide layer 26a. In addition, the silicide layer 26b is formed by reacting the silicon atoms on the surface of the gate 22 with the titanium atoms in the titanium film. Further, the silicon atoms on the surface of the impurity diffusion layer 27 are reacted with the titanium atoms of the titanium film to form the silicide layer 26c.

  Next, as shown in FIG. 1, a silicon oxynitride film as a first insulating film 37 is formed on the entire surface by CVD. The thickness of the first insulating film 37 can be set as appropriate, but in the present embodiment, it is 200 nm.

  Then, a silicon oxide film as the second insulating film 38 is formed on the first insulating film 37 by the CVD method. The thickness of the second insulating film 38 can be set as appropriate, but is set to 300 nm in the present embodiment.

  Further, a silicon oxide film as a third insulating film 39 is formed on the second insulating film 38 by a spin-on-glass (SOG) method. The thickness of the third insulating film 39 can be set as appropriate, but is set to 240 nm in the present embodiment. The third insulating film 39 is formed by heat treatment after the SOG solution is applied. The heat treatment conditions are a temperature of 450 ° C. and a time of 30 minutes.

  In this way, the semiconductor device 1 shown in FIG. 1 is formed. Thereafter, through a general semiconductor integrated circuit wiring process, the semiconductor device is completed (not shown).

  Next, details of the thermal oxidation method of FIG. 12 will be described below.

  The thermal oxidation is preferably performed at a temperature in the range of 750 ° C to 1150 ° C. When the temperature of thermal oxidation is lower than 750 ° C., the thermal oxidation rate is low, so that the throughput is deteriorated. On the other hand, if the temperature of thermal oxidation is higher than 1150 ° C., the diffusion of impurities increases and the silicon substrate 2 and the like may be damaged by heat.

  The specific temperature of thermal oxidation is appropriately set in the above range according to a preferable oxidation rate. For example, the control of the oxide film thickness may be easier because the oxidation rate is lower when the oxidation temperature is lower.

The gas used for thermal oxidation is preferably oxygen, oxygen and hydrogen, or water vapor. In addition to the above gas, N ₂ or HCl may be added.

The gas flow rate used for thermal oxidation is appropriately set according to a preferable oxidation rate. Gas flow rate, for example, may be oxygen of ^{0.845Pa · m 3 / s (5slm} ), hydrogen ^{1.69Pa · m 3 / s (10slm} ).

  The pressure used for thermal oxidation is appropriately set according to a preferable oxidation rate. As the pressure, for example, normal pressure can be used. The above is the description of the thermal oxidation method.

  In order to suppress the diffusion of impurities in the silicon substrate 2, it is preferable to use a plasma oxidation method or a chemical oxidation method in which an oxidation treatment is performed at a relatively low temperature. Also, it is preferable to use an oxidation method performed at a low temperature when it is desired to keep the oxide film thickness particularly small. The above is the description of the oxidation method.

  Next, details of preferable wet etching conditions for the isotropic etching of FIG. 13 will be described below.

  In this embodiment, wet etching for isotropic etching is performed using an etching solution containing hydrofluoric acid. Specifically, in this embodiment, an aqueous solution of hydrogen fluoride is used.

  The etching solution containing hydrofluoric acid preferably has a hydrogen fluoride concentration in the range of 0.01% by volume to 20% by volume, particularly in the range of 1% by volume to 5% by volume. When the concentration of hydrogen fluoride is lower than 0.01% by volume, the etching rate is low and the throughput is deteriorated. On the other hand, if the concentration of hydrogen fluoride is higher than 20% by volume, the etching rate becomes high, so that it may be difficult to control the etching. The specific concentration of hydrogen fluoride is appropriately set within the above range according to a preferable etching rate.

  The temperature used for wet etching is appropriately set according to a preferable etching rate. For example, room temperature can be used as the temperature.

  The wet etching time is appropriately set according to the preferable width T2 of the gate length 11. The wet etching time is preferably longer than the time during which the oxidized portion on the side of the polycrystalline silicon film 35a and the oxidized portion on the surface of the silicon substrate 2 can be removed. The above is the description of the wet etching conditions.

  According to the semiconductor device manufacturing method of the present embodiment described above, the width of the gate and the gate oxide film can be reduced, and the gate length which is the distance between the source extension region and the drain extension region can be shortened. Therefore, if this embodiment is used, fine processing exceeding the resolving power of the exposure apparatus used for manufacturing can be performed.

  Further, according to this embodiment, the gate oxide film is finely processed with high accuracy.

  Since the polycrystalline silicon films 35a and 35b are thermally oxidized and then isotropically etched using an aqueous hydrogen fluoride solution, only the oxidized portions of the polycrystalline silicon films 35a and 35b are etched. Since the control of the oxide film thickness by thermal oxidation of the polycrystalline silicon films 35a and 35b can be performed with high accuracy, the etching processing accuracy of the gate 12 is high. For example, the method of isotropically etching the polycrystalline silicon films 35a and 35b after the thermal oxidation as in the present embodiment is performed when the polycrystalline silicon films 35a and 35b are directly etched using, for example, a hydrofluoric acid aqueous solution (for example, The processing accuracy of etching is higher than that of Patent Document 1).

  Therefore, the gate 12 can be formed with high processing accuracy. Therefore, the semiconductor device can be finely processed with high accuracy.

  The MOS transistors 10 and 20 included in the semiconductor device 1 manufactured according to the present embodiment described above have a portion in which the gates 12 and 22 are undercut, and a part of the side wall insulating films 14 and 24 is formed in this portion. Embedded. Therefore, a part of the sidewall insulating films 14 and 24 embedded in the undercut portion can also be considered as a part of the gate oxide films 11 and 21.

  Therefore, the MOS transistors 10 and 20 shown in FIG. 1 are compared with the case where the gates 12 and 22 are not undercut.

  In the MOS transistors 10 and 20 shown in FIG. 1, in the portions where the gates 12 and 22 are undercut, the distance between the surface of the silicon substrate 2 and the gates 12 and 22 is larger than the portions of the gate oxide films 11 and 21. Therefore, it can be seen that the MOS transistors 10 and 20 have a smaller capacitance than the MOS transistors whose gates 12 and 22 are not undercut.

  Therefore, in the MOS transistors 10 and 20 shown in FIG. 1, the amount of charge required for driving the transistors is reduced as compared with the case of the MOS transistors in which the gates 12 and 22 are not undercut.

  Next, a modification of the semiconductor device 1 of the present embodiment described above will be described below with reference to FIG.

  FIG. 19 is a cross-sectional view showing a P-channel MOS transistor 50 according to a modification of the embodiment of the semiconductor device disclosed in this specification.

  In the P-channel MOS transistor 50 shown in FIG. 19, the undercut portion of the gate 12 is a cavity 18. The cavity 18 is a region surrounded by the gate 12, the gate oxide film 11, the source / drain region 16 a, and the sidewall insulating film 14. The cavity 18 is preferably decompressed, and is particularly preferably a vacuum.

  In the P-channel MOS transistor 50, the capacitance between the surface of the silicon substrate 2 and the gates 12 and 22 is further reduced. Therefore, the amount of charge necessary for driving the transistor is further reduced. This cavity may also be provided in the N channel MOS transistor. Other structures of the semiconductor device according to the modification are the same as those of the above-described embodiment.

  In the present invention, the above-described semiconductor device and the manufacturing method thereof disclosed in this specification can be appropriately changed without departing from the spirit of the present invention. For example, in the semiconductor device 1 shown in FIG. A CMOS may be formed by connecting P-channel MOS transistors and N-channel MOS transistors so as to complement each other.

  Next, an experimental example of the oxidation step in the method for manufacturing a semiconductor device disclosed in this specification will be described below with reference to FIGS. However, the present invention is not limited to such experimental examples.

  FIG. 20 is a diagram showing the relationship between the thermal oxidation time and the oxide film thickness of the polycrystalline silicon films 35a and 35b.

  In FIG. 20, the horizontal axis represents the oxidation time, and the vertical axis represents the oxide film thickness. Further, five levels of measurement were performed at intervals of 50 ° C. between 750 ° C. and 950 ° C. using the oxidation temperature of thermal oxidation as a parameter.

  The oxide film thickness increases as the oxidation temperature increases. Further, the oxidation rate, which is an increase amount of the oxide film thickness per unit time, increases with an increase in the oxidation temperature.

  As shown in FIG. 20, for example, when thermal oxidation is performed at an oxidation temperature of 950 ° C., the amount of increase in the oxide film thickness per 10 minutes of oxidation time is about 0.1 μm. If the oxidation temperature is lowered, the amount of increase in the oxide film thickness is further reduced. Therefore, it can be seen that the oxide film thickness can be controlled with high accuracy by thermal oxidation of the polycrystalline silicon films 35a and 35b.

  Next, an experimental example of an etching process in the method for manufacturing a semiconductor device disclosed in this specification will be described below with reference to FIGS. However, the present invention is not limited to such experimental examples.

  FIG. 21 is a diagram showing the relationship between the etching time and the etching amount of the oxide film in which the polycrystalline silicons 35a and 35b are oxidized. As an etching method, isotropic etching of an aqueous solution of hydrogen fluoride was used.

  In FIG. 21, the horizontal axis represents the etching time, and the vertical axis represents the etching amount. Further, two levels of 1% and 5% by volume were measured using the hydrogen fluoride concentration as a parameter.

  The etching amount of the oxide film increases as the hydrogen fluoride concentration increases. In addition, the etching rate, which is the amount of increase in the etching amount per unit time, increases as the hydrogen fluoride concentration increases.

  Next, an experimental example of the etching amount of the gate oxide film width in the method for manufacturing a semiconductor device disclosed in this specification will be described below with reference to FIGS. However, the present invention is not limited to such experimental examples.

  FIG. 22 is a diagram showing the relationship between the thermal oxidation time of the polycrystalline silicon film and the gate reduction length of the oxide film. Here, the etching amount of the width of the gate oxide film means a difference between the width T3 (see FIG. 11) and the width T2 (see FIG. 13). The measurement results shown in FIG. 22 are obtained by performing the etching shown in FIG. 13 after the thermal oxidation shown in FIG. 12 under the above-described thermal oxidation conditions.

  In FIG. 22, the horizontal axis represents the oxidation time, and the vertical axis represents the etching amount of the width of the gate oxide film. Further, five levels of measurement were performed at intervals of 50 ° C. between 750 ° C. and 950 ° C. using the oxidation temperature of thermal oxidation as a parameter.

  As an etching method, an aqueous solution having a hydrogen fluoride concentration of 5% by volume was used. The etching time was set to a time for removing the silicon oxide film formed on the side portion of the polycrystalline oxide film 35a shown in FIG.

  As shown in FIG. 22, for example, when thermal oxidation is performed at an oxidation temperature of 950 ° C., the etching amount of the width of the gate oxide film per 10 minutes of oxidation time is about 0.18 μm. If the oxidation temperature is lowered, the etching amount of the width of the gate oxide film is further reduced. Therefore, it can be seen that the etching amount of the width of the gate oxide film can be controlled with high accuracy.

  Further, by appropriately adjusting the etching amount of the width of the gate oxide film, by etching the silicon oxide film formed by the thermal oxidation shown in FIG. 12, only the silicon oxide film before the thermal oxidation (see FIG. 11) is used. A gate oxide film to be formed can be formed. Further, by appropriately adjusting the etching amount of the width of the gate oxide film, the gate oxide film can be formed with a part of the silicon oxide film formed by thermal oxidation shown in FIG. 12 remaining.

  All examples and conditional words mentioned herein are intended for educational purposes to help the reader deepen and understand the inventions and concepts contributed by the inventor. All examples and conditional words mentioned herein are to be construed without limitation to such specifically stated examples and conditions. Also, such exemplary mechanisms in the specification are not related to showing the superiority and inferiority of the present invention. While embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions or modifications can be made without departing from the spirit and scope of the invention.

  With respect to the above-described embodiment and its modifications, the following additional notes are disclosed.

(Appendix 1)
Forming an oxide film on the substrate;
Forming a polycrystalline silicon film having a predetermined width on the oxide film;
Oxidizing the substrate surface to oxidize at least the sides of the polycrystalline silicon film;
Etching the oxide film together with the oxidized portion of the polycrystalline silicon film so as to leave a portion of the oxide film having a width smaller than the predetermined width under the polycrystalline silicon film;
A method for manufacturing a semiconductor device comprising:

(Appendix 2)
2. The method of manufacturing a semiconductor device according to appendix 1, wherein in the oxidizing step, a side portion of the polycrystalline silicon film is oxidized deeper inward along the oxide film than other portions.

(Appendix 3)
3. The semiconductor device according to claim 2, wherein in the etching step, the polycrystalline silicon film is etched so as to extend outward from a bonding surface with the oxide film toward a surface opposite to the bonding surface. Production method.

(Appendix 4)
The method of manufacturing a semiconductor device according to any one of appendices 1 to 3, wherein the oxidizing step uses thermal oxidation.

(Appendix 5)
The semiconductor device manufacturing method according to appendix 4, wherein the oxidizing step is performed by performing thermal oxidation at a temperature in a range of 750 ° C to 1150 ° C.

(Appendix 6)
6. The method of manufacturing a semiconductor device according to appendix 4 or 5, wherein the oxidizing step performs thermal oxidation using oxygen or water vapor.

(Appendix 7)
The method for manufacturing a semiconductor device according to any one of appendices 1 to 6, wherein the etching step uses isotropic etching.

(Appendix 8)
The method for manufacturing a semiconductor device according to appendix 7, wherein the etching step performs isotropic etching using an etching solution containing hydrofluoric acid.

(Appendix 9)
The semiconductor device manufacturing method according to appendix 8, wherein the etching solution containing hydrofluoric acid has a hydrogen fluoride concentration in a range of 0.01% by volume to 20% by volume.

(Appendix 10)
After the etching step,
Implanting impurities into the portions of the substrate on both sides of the polycrystalline silicon film, using the polycrystalline silicon film with the oxidized portion etched as a mask;
Forming sidewall insulating films on both sides of the polycrystalline silicon film;
Using the polycrystalline silicon film on which the sidewall insulating film is formed as a mask, ion-implanting impurities into portions of the substrate on both sides of the polycrystalline silicon film;
The manufacturing method of the semiconductor device as described in any one of appendixes 1 to 9 which has these.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Silicon substrate 3 N well 4 P well 5 Buried diffusion region 6 Buried diffusion region 10 P channel MOS transistor 11 Gate insulating film 12 Gate 13 Source / drain extension region 14 Side wall insulating film 15 Source / drain region 16a, 16b, 16c silicide layer 17 N well contact region 18 N-well contact impurity diffusion layer 20 N channel MOS transistor 21 gate insulating film 22 gate 23 source / drain extension region 24 side wall insulating film 25 source / drain region 26a, 26b, 26c silicide layer 27 P well contact region 28 P well contact impurity diffusion layer 30 Protective film 31 Silicon nitride film 32 Element isolation insulating film 33 Protective film 34 Silicon oxide film 35 Crystalline silicon film 36 protective film 37 first insulating layer 38 second insulating layer 39 third insulating film

Claims (5)

Forming an oxide film on the substrate;
Forming a polycrystalline silicon film having a predetermined width on the oxide film;
Oxidizing the substrate surface to oxidize at least the sides of the polycrystalline silicon film;
Etching the oxide film together with the oxidized portion of the polycrystalline silicon film so as to leave a portion of the oxide film having a width smaller than the predetermined width under the polycrystalline silicon film;
A method for manufacturing a semiconductor device comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the oxidizing step, the side portion of the polycrystalline silicon film is oxidized deeper inwardly than the other portions along the oxide film.   3. The semiconductor device according to claim 2, wherein in the etching step, the polycrystalline silicon film is etched so as to extend outward from a bonding surface with the oxide film toward a surface opposite to the bonding surface. Manufacturing method.   The method for manufacturing a semiconductor device according to claim 1, wherein the oxidizing step uses thermal oxidation.   The method of manufacturing a semiconductor device according to claim 1, wherein the etching step uses isotropic etching.

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