JP2010262362A - Semiconductor device and power supply control method for the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a power supply control method of the semiconductor device for precisely predicting a period in which any access is not performed for each function block, and for controlling the power supply of the function block in a period in which any access is not performed. <P>SOLUTION: The semiconductor device includes: a basic bus; a plurality of function blocks connected to the basic bus; and a bus monitor for monitoring the basic bus, and for extracting the end address of access to the function block and an access interval until access is performed to the function block the next for each function block from data on the basic bus, and for interrupting the power source of the function block when the access is performed to the end address, and for starting the rising of the power source of the function block before the lapse of the access interval so that access is performed to the function block after the lapse of the access interval. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a power control method for the semiconductor device. In particular, the present invention relates to a method for controlling a power supply for each functional block in a semiconductor device in which a plurality of functional blocks are connected to a common bus.

  In recent years, battery-powered products such as mobile phones have increased, and the demand for power saving has increased. In the process, semiconductor devices have also responded to the demand for low voltage by miniaturizing the process. However, further power saving of products has progressed, and there has been a demand for a product that suppresses not only the consumption current during operation of the semiconductor device but also the leakage current when the operation is stopped, so that more effective power control has been required. .

  FIG. 9 is a block diagram of a semiconductor device that controls power on / off for each functional block described in FIG. 11 of Patent Document 1 to reduce power. It is described that the circuit in FIG. 9 automatically updates the length of the period from the last access (data) to the functional block until the power supply to the functional block is cut off by the learning function. In FIG. 9, the period from the last access until the power switch D1 is shut off is determined by the shutdown cycle number buffer BF, and the value of this BF is controlled by the determination circuit DCS.

  FIG. 10 is an operation flowchart showing a method for controlling the determination circuit DCS described in FIG. As shown in FIG. 10, if the cycle k from the shutdown until the next data comes is larger than the shutdown cycle n, control is performed to increase n, and in the opposite case, control is performed to decrease n.

  FIG. 11 shows the operation of turning on and off the power switch for the period with and without data when the control is performed as shown in FIG. 9 and FIG. 10 described in FIG. FIG. In Patent Document 1, learning is performed during a period during which there is an access and a period during which no access is made, and the number of clocks from when access is lost to when the power switch is turned off is switched. In FIG. 11, the number of clocks until the power switch that was initially 2 is changed to 3 by learning in the middle, and then returns to 2 by learning again. Also, since the power switch is turned on after the data comes, the power switch is turned on, and the power switch is always turned on by one clock after the data comes.

JP 2006-318513 A

  The following analysis is given by the present invention. In Patent Document 1, even if access is lost, the power switch is turned off after a certain period of time has passed without immediately turning off the power switch. Therefore, wasteful power is consumed until the power switch is turned off. Further, in Patent Document 1, since the power switch is turned on after data arrives, the power switch is turned on later than the data comes, and the processing time is delayed due to the power switch being turned off. This is because in Patent Document 1, the end time of access and the start time of the next access cannot be grasped.

  A semiconductor device according to an aspect of the present invention monitors a backbone bus, a plurality of functional blocks connected to the backbone bus, the backbone bus, and the functional block for each functional block from data on the backbone bus. The access end address and the access interval until the next access to the function block is extracted, and when the end address is accessed, the power of the function block is shut off, and the access interval A bus monitor that controls the power supply of the functional block to start up before the elapse of the access interval so that the functional block can be accessed when it elapses.

  According to another aspect of the present invention, there is provided a power control method for a semiconductor device, wherein a plurality of functional blocks that can be turned on and off independently are connected to a common bus. And, for each functional block, extracting an end address of access to the function block, an access interval until the next access to the function block, and when the end address is accessed A step of shutting off the power supply of the functional block, and a step of starting up the power supply of the functional block before the access interval elapses so that the function block can be accessed when the access interval elapses. including.

  According to the present invention, the backbone bus is monitored, and the access end address immediately before entering the period of no access and the period of no access to each functional block is detected from the data on the backbone bus. When this happens, the power of the functional block can be shut off, and the power can be turned on when the period of no access ends. Therefore, useless power consumption can be suppressed and processing delay due to power shutdown can be prevented.

1 is a block diagram of a semiconductor device according to an embodiment of the present invention. It is a block diagram of the bus monitor in the semiconductor device of one Example. It is a block diagram of the control register CR in the semiconductor device of one Example. It is a block diagram of the temporary storage table TT in the semiconductor device of one Example. It is a block diagram of the address information storage table MT in the semiconductor device of one Example. It is a power supply control flowchart in the semiconductor device of one embodiment. It is an electric power transition figure at the time of performing a power supply shutdown in the semiconductor device of one Example. It is a data exchange flow diagram of the temporary storage table TT and the address information storage table MT in the semiconductor device of one embodiment. 10 is a block diagram of a conventional semiconductor device described in Patent Document 1. FIG. FIG. 10 is an operation flow diagram of a determination circuit DCS in the conventional semiconductor device described in Patent Document 1. FIG. 10 is an operation flow diagram of turning on / off a power switch by a conventional semiconductor device described in Patent Document 1. It is a power control flowchart in the semiconductor device of another Example of this invention. It is a power transition figure at the time of performing a clock stop in the semiconductor device of another Example.

  An outline of an embodiment of the present invention will be described with reference to the drawings as necessary. In the description of the outline, the drawings and the reference numerals of the drawings are shown as examples of the embodiments, and the variations of the embodiments according to the present invention are not limited thereby.

  For example, as illustrated in FIGS. 1 and 6, the semiconductor device 50 according to the embodiment includes a backbone bus B, a plurality of functional blocks (22, 23, 24, 25) connected to the backbone bus B, and the backbone bus. B is monitored, and from the data on the main bus B, there is an access end address (MA in FIG. 5) for each functional block (22, 23, 24, 25), and then the functional block is accessed. The access interval (MS in FIG. 5) is extracted, and when the end address (MA) is accessed, the power of the functional block is shut off, and the functional block can be accessed when the access interval elapses. The bus monitor 10 controls the power supply of the functional block to start up before the access interval elapses. That is, the data of the main bus is monitored, and the end address of the access period immediately before entering the period without access to the functional blocks and the period without access is extracted. Therefore, after access to the end address, access to the functional block does not exist during the access interval, so that the power of the functional block can be shut off. In addition, since the next access time can be known from the access interval, the power supply can be turned on according to that timing. Although the functional block operation may be periodic or non-periodic, the bus monitor 10 extracts periodic ones. Therefore, unlike in Patent Document 1, useless power is not consumed until the power is shut off after the operation is completed, and the start of the next operation is not delayed. Note that after entering the power shut-off routine upon detection of the end address, the power may be turned off slowly in a stepwise manner so as not to give power noise or the like to other function blocks in operation.

  In the present specification, the basic bus refers to a bus to which a plurality of functional blocks and a bus monitor are connected. The backbone bus includes at least an address bus for designating and accessing a function block and an address in the function block. This address bus may be multiplexed with the data bus.

  In the semiconductor device 50 according to the embodiment, each functional block (22, 23, 24, 25) is provided with a power switch, and the bus monitor 10 is provided in each functional block (22, 23, 24, 25). A mode switching execution unit MJ is provided to control power supply interruption and reactivation by controlling conduction / interruption of the provided power switch. Each functional block (22, 23, 24, 25) is provided with a power switch (D1 in FIG. 9) as in Patent Document 1. The bus monitor 10 can perform power control for each functional block by controlling the power switch on and off by the power control signals D2 to D5.

  Further, referring also to FIG. 3, in the semiconductor device 50 according to the embodiment, the bus monitor 10 is configured so that the address range (SA22 to SA25) for each functional block (22, 23, 24, 25) and the power supply rise for each functional block. A control register CR that stores information including a required time (SE22 to SE25) is further provided, and the functional block in which data on the backbone bus B is from the address range (SA22 to SA25) for each functional block of the control register CR (22, 23, 24, 25) is recognized as an access to extract the periodicity of access to each functional block, and time information (SE22 to SE25) necessary for power-on for each functional block of the control register CR is used. Determine the power-on timing of the function block. If the address range (SA22 to SA25) for each functional block is set in the control register CR in advance, the bus monitor 10 can determine from the address on the main bus B and the address range for each functional block stored in the control register CR. It is possible to grasp which functional block the access on the main bus is for. Therefore, the bus monitor 10 can extract the access end address and access interval for each functional block. Furthermore, since the control register CR stores time information necessary for power on for each functional block, the power is turned on in accordance with the next access cycle based on the information and the access interval for each extracted functional block. It can be performed.

  In the semiconductor device 50 according to the embodiment, for example, as illustrated in FIGS. 2 and 5, the bus monitor 10 further includes an address information storage table MT and an address comparison unit AC, and accesses for each functional block. And the address last accessed before that function block is extracted and stored in the address information storage table MT along with the access count data as the address and access interval, and the address comparator AC stores the address information. When access to the address stored in the table MT is detected, the power to the functional block is shut off.

  Further, in the semiconductor device 50 according to the embodiment, for example, as shown in FIGS. 2, 4, and 8, the bus monitor 10 does not access the last accessed address for each functional block and the functional block. An access input interval measuring unit AM that measures an access interval that is a period; a temporary storage table TT that temporarily stores addresses and access intervals measured by the access input interval measuring unit AM; and a temporary storage table TT. When the access interval of the entered address is longer than the access interval of the address entered in the address information storage table MT, the entry in the address information storage table MT is replaced with the entry in the temporary storage register TT (FIG. 8). 207). With the above configuration, the entry of the address information storage table MT can be optimized.

  In the semiconductor device 50 according to the embodiment, for example, as illustrated in FIGS. 2 and 12, the mode switching execution unit MJ detects an access to an address stored in the address information storage table MT by the address comparison unit AC. In addition, when the number of accesses to the address stored in the address information storage table MT does not satisfy a predetermined number, or the expected time until the next access is necessary for power-on of the function block stored in the control register CR. If it is less than the time, the function block clock is stopped without shutting off the power to the function block (see 308 in FIG. 12). That is, when it is considered that the number of accesses to the entry in the address information storage table MT is small and the accuracy of the entry is low, or when the access cycle is short and the power is cut off and turned on again, the next access cycle is delayed. In this case, the power consumption of the functional block can be reduced by stopping the clock of the target functional block without shutting off the power. Hereinafter, examples will be described in more detail with reference to the drawings.

  FIG. 1 is a block diagram of a semiconductor device 50 according to the first embodiment. As shown in FIG. 1, the basic bus B on the semiconductor device 50 includes a CPU 21 and a bus A1, a ROM / RAM 22 and a bus A2, a CDROM control unit 23 and a bus A3, an HDD control unit 24 and a bus A4, and a display device control unit 25 and a bus. A5, connected to the bus monitor 10. The bus monitor 10 outputs power control signals D2, D3, D4, and D5 from the ROM / RAM 22, the CDROM control unit 23, the HDD control unit 24, and the display device control unit 25. Note that each functional block of the ROM / RAM 22, the CDROM control unit 23, the HDD control unit 24, and the display device control unit 25 is provided with a power switch (not shown), and power is supplied through the power switch. As the power switch, the power switch D1 shown in FIG. 9 can be applied to FIG. The power switches of the respective functional blocks (22, 23, 24, 25) are controlled to be turned on and off (conducted and cut off) by power control signals D2, D3, D4, and D5, respectively.

  FIG. 2 shows the configuration of the bus monitor 10. The bus monitor 10 includes an access input interval measuring unit AM that measures the address signal A of the main bus B, a temporary storage table TT and an address information storage table MT that are information tables of power control, and an address signal A and a temporary storage table of the main bus B. Address comparison unit AC that compares the values of the address information in the TT and address information storage table MT, a control register CR that holds information necessary for power control of each functional block, and the address comparison result of the address comparison unit AC And a mode switching execution unit MJ that outputs power control signals D2 to D5 based on the data in the control register CR and directly controls the power of each functional block.

  The access input interval measuring unit AM of the bus monitor 10 has accessed the last access for each functional block and the last access from the data issued in the address range for each functional block stored in the control register CR. Measure the elapsed time. When entering an idle period when there is no access to the function block, the last accessed address remains without being updated, and the next time the function block is accessed, the access end address and access interval are Will be measured. Here, the access end address is an address immediately before entering the period in which access to the functional block ends and the functional block is not accessed, and the access interval is the length of the period in which there is no access. An information table for controlling power is constructed by storing the access end address and access interval measured by the access input interval measuring unit AM in the temporary storage table TT and the address information storage table MT.

  The address comparison unit AC compares the address A issued on the main bus B with the address information registered in the temporary storage table TT and the address information storage table MT, and based on the comparison result, the mode switching execution unit MJ performs the main bus B. Controls the power supply of the function block at the corresponding address above. Further, the address comparison unit AC performs a coincidence comparison between the address measured by the access input interval measurement unit AM and the address information registered in the temporary storage table TT and the address information storage table MT, and stores the temporary storage table TT and the address information storage. It may be used when updating the table MT.

  The internal configuration of the control register CR is shown in FIG. The control register CR is the information necessary for controlling the function block power supply of the ROM / RAM 22, the CDROM control unit 23, the HDD control unit 24, and the display device control unit 25 to be turned on again. It has information on the interval RS, the power supply rise times SE22 to SE25 for each functional block, and the functional block address ranges SA22 to SA25.

  FIG. 4 shows the internal configuration of the temporary storage table TT. The temporary storage table TT has an interval TS (address to the functional block) between the address information TA (access end address to the functional block) of the address A on the trunk bus B measured by the access input interval measuring unit AM and the next access. Information on the period of no access). The temporary storage table TT stores addresses that are candidates for the power shutdown process entry address stored in the address information storage table MT described below.

  The internal configuration of the address information storage table MT is shown in FIG. The address information storage table MT has information on the address MA, the access interval MS, and the number of times of access MC to the address MA. This address MA stores an address that triggers a power-off process for each functional block. Based on the information of the access interval MS, the next access timing is determined, and the power-on timing is determined based on this information. The access occurrence count MC is a reference for the accuracy of the entry. The greater the number of times of access occurrence, the higher the information accuracy of the entry.

  FIG. 6 is an operation flowchart of power control of each functional block. When the bus monitor 10 detects access to the functional blocks of the ROM / RAM 22, the CDROM control unit 23, the HDD control unit 24, and the display device control unit 25 on the backbone bus B, the address A becomes the address information MA of the address information storage table MT. Is compared with the address comparison unit AC (step 101). If they do not match, the power supply control is not performed and the process is terminated.

  On the other hand, if the addresses match, the address comparison unit AC issues a power supply shutdown request signal (4 in FIG. 2) to the mode switching execution unit MJ, and the mode switching execution unit MJ has an address range SA22 registered in the control register CR. From SA25, the address of which functional block of the ROM / RAM 22, CDROM control unit 23, HDD control unit 24, and display device control unit 25 matches is searched (step 102). The clocks of the functional blocks of the ROM / RAM 22, the CDROM control unit 23, the HDD control unit 24, and the display device control unit 25 whose addresses match as a result of the search are stopped and the power supply is shut off (step 103).

  The power supply rises when the mode switching execution unit MJ subtracts the rise time SE22 to SE25 of the corresponding functional block set in the control register CR from the access interval MS registered in the address information storage table MT (step 104). And the power is turned on (step 105). When the power supply becomes stable, the clock is activated and access becomes possible again (step 106). Since the power supply is started in consideration of the access interval MS and the power supply rise time SE22 to SE25 of the corresponding functional block, the power supply startup is too early without delaying the time when access to the functional block is necessary. The power supply can be started up without consuming extra power.

  FIG. 7 shows the state of power transition from the power shutdown until the power is turned on again. In this embodiment, the time t3 when access to the functional blocks of the ROM / RAM 22, the CDROM control unit 23, the HDD control unit 24, and the display device control unit 25 is predicted is predicted, and the ROM / RAM 22, the CDROM control unit 23, and the HDD control are predicted. Since the time t3-t2 in which the power supply to the functional blocks of the unit 24 and the display device control unit 25 is turned on again and the power supply rises and is considered is taken into account, low power consumption can be realized without lowering the system performance.

  Next, a processing flow for updating the address information storage table MT and the temporary storage table TT will be described with reference to FIG. First, the access input interval measuring unit AM acquires the address A and the access interval TS on the trunk bus B (Step 201). This process is performed every time access to the functional block occurs. The access input interval measuring unit AM has an address (previous access end address) last accessed for the functional block as data and an access interval since the previous access. The address is compared with the address stored in the address information table MT (step 202). If the addresses match, the number MC of the matched addresses MA in the address information storage table MT is incremented (step 203).

  Next, the process proceeds to step 209. In step 209, first, the latest access interval measured by the access input interval measuring unit AM is compared with the access interval MS recorded in the address information storage table MT. If the access interval recorded in the address information storage table MT is smaller or the value is the same, nothing is done. This is usually the process. However, if the latest access interval measured by the access input interval measuring unit AM is smaller than the access interval MS recorded in the address information storage table MT, the address is stored in the address information storage table MT after accessing the address. Since it may be possible to access at an interval shorter than the registered access interval, the access interval MS recorded in the address information storage table MT is replaced with the latest access interval measured by the access input interval measuring unit AM. Thereafter, the process is terminated. In step 209, the access interval MS registered in the address information storage table MT has been verified to have no access interval shorter than that in the access interval TS of the temporary storage table (see step 210). ). Therefore, this step 209 may be omitted if unnecessary.

  On the other hand, if there is a mismatch in step 202, a match comparison is made with the address registered in the temporary storage table TT (step 204). If the address matches the address registered in the temporary storage table TT, the process proceeds to step 210. In step 210, first, the access interval TS registered in the temporary storage table TT is compared with the latest access interval measured by the access input interval measuring unit AM. If the access interval recorded in the temporary storage table TT is smaller or the value is the same, nothing is done. However, if the latest access interval measured by the access input interval measuring unit AM is smaller than the access interval TS recorded in the temporary storage table TT, it is registered in the temporary storage table TT after accessing the address. This means that the functional block may be accessed at an interval shorter than the current access interval. Therefore, the access interval TS recorded in the temporary storage table TT is replaced with the latest access interval measured by the access input interval measuring unit AM. . Thus, step 210 is completed.

  Next, the access interval TS of the address recorded in the temporary storage table TT is compared with the minimum access interval MS among the access intervals MS registered in the address information storage table MT (step 206). If the access interval TS recorded in the temporary storage table TT is smaller, nothing is done. If the access interval TS recorded in the temporary storage table TT is larger, the address MA and the access interval MS registered in the address information storage table MT are exchanged, and the number of times MC is set to the minimum value (step 207). ). Thereafter, the process is terminated.

  If the coincidence comparison with the address registered in the temporary storage table TT does not match in step 204 (if it is not registered in the temporary storage table TT), the comparison is made with the access interval TS registered in the temporary storage table TT (step 205) If the access interval is large, replacement is performed so that the address information having the larger access interval remains in the table (step 208), and the process is terminated. If the access interval is smaller than the access interval TS of the data registered in the temporary storage table TT, the process is terminated without performing replacement.

  According to the above procedure, the address A on the trunk bus B and the next access interval TS are first stored in the temporary storage table TT. When the address A is stored in the temporary storage table TT, it cannot be determined whether the access has reproducibility. Whether or not the access interval for the end address stored in the temporary storage table TT is the shortest is verified in step 210 and replaced with the shortest access interval. Accordingly, in step 210, the access interval for the end address is updated to highly accurate data. Although there are a large number of sets of end addresses and access intervals, data with the largest access interval remains in the temporary storage table TT by steps 205 and 208.

  Further, in steps 206 and 207, the data stored in the address information storage table MT is compared with the data stored in the temporary storage table TT, and data having a large access interval is registered in the address storage table MT. Become. With the above processing, data with a high access interval and a large access interval remains in the address storage table MT. Even if access interval data with low accuracy is registered in the address storage table MT, the access interval is correctly corrected in step 209. If the corrected access interval is small, then the data is replaced by data with a large access interval through step 207, so no problem occurs.

  Therefore, when it is not known whether the address A is reproducible access, the information of the address A is not used for power saving because the prediction accuracy is low. When access to the same address occurs again, it is determined that access to address A is reproducible and accuracy can be expected even when used for prediction of power control, and information is transferred to the address information storage table MT. By this procedure, only reproducible information is registered in the address information storage table MT.

  That is, when the address on the trunk bus B measured by the access input interval measuring unit AM matches the information registered in the temporary storage table TT, the access to the measured address is read by the ROM / RAM 22 and the CDROM control unit. 23, if it is determined that there is reproducibility as a trigger for setting the functional blocks of the HDD control unit 24 and the display device control unit 25 in an idle state, and the access interval TS is equal to or greater than the access occurrence count RO set in the control register CR, The address information TA and the access interval TS are passed to the access storage information table MT.

  The temporary storage table TT performs the comparison with the information of the address TA stored in the table every time an access is issued in order to perform reproducible access extraction, and the address comparison unit AC in FIG. The information of the address TA and the next access interval TS is exchanged so that information with a wide access interval remains in the table.

  As described above, the address information storage table MT registers the access information to the address determined to be reproducible from the temporary storage table TT, and performs power control. In addition, the address MA registered in the address information storage table MT is used to specify the target to be reduced in power, the access interval MS is used as an index for reducing power, and the number of accesses MC is the accuracy of prediction when the power is reduced. It is used as

  According to the first embodiment, the ROM / RAM 22, the CDROM control unit 23, the HDD control unit 24, and the function block of the display device control unit 25 are triggered by the ROM / RAM 22, the CDROM control unit 23, and the HDD control unit 24. Attention is paid to access to a fixed address such as register access of a functional block of the display device control unit 25. Addresses and access input intervals issued in accessing the functional blocks of the ROM / RAM 22, the CDROM control unit 23, the HDD control unit 24, and the display device control unit 25 are stored in the address information storage table MT. Further, learning is performed by updating the data stored in the address information storage table MT so that the access has a long idle period until the next access effective for power saving. By determining the trigger of the idle state from the contents of the address information storage table MT, the access is accurately predicted, and the power is reduced.

  In the second embodiment, the configuration of the entire semiconductor device 50 in FIG. 1, the configuration of the bus monitor 10 shown in FIG. 2, the control register CR in FIG. 3, the temporary storage table TT in FIG. 4, and the address information storage table MT in FIG. The approximate configuration is almost the same as in the first embodiment. However, the power control for each functional block by the mode switching execution unit MJ is different.

  FIG. 12 is a power control flowchart in the semiconductor device 50 according to the second embodiment. In the second embodiment, when the bus monitor 10 detects access to the functional blocks of the ROM / RAM 22, the CDROM control unit 23, the HDD control unit 24, and the display device control unit 25 on the backbone bus B, the address A is stored in the address information storage table. A match search with the address information MA of the MT is performed by the address comparison unit AC (step 101).

  If the addresses match, the corresponding unit of the functional block address is searched from the control register CR (step 102), and it is compared whether the access count MC of the functional block exceeds the access occurrence count RO set in the control register CR (step 302). ). If the access count MC of the functional block does not exceed the access occurrence count RO set in the control register CR, there is a possibility that the access will occur at the next short interval, and a power supply rise time will occur if it is not predicted Therefore, the power supply is not shut off and only the clock is stopped (step 307). The generation of an access request to the functional block is monitored (step 308), and when an access request to the functional block is generated, the clock of the functional block is activated (step 309), and the process is terminated.

  If the access count of the functional block exceeds the access occurrence count RO set in the control register CR in step 302, the time SE22 to SE25 required for power-on and the address information storage table MT set in the control register CR are stored. The time until the next access stored is compared (step 303), and the remaining time until the predicted next access stored in the address information storage table MT is longer than the power supply rise time set in the control register CR. If is small, the processing of step 307 and step 308 is executed.

  If the remaining time until the predicted next access stored in the address information storage table MT is larger than the power supply rise time set in the control register CR in step 303, the function block power supply is cut off and the clock is stopped. (Step 304). When the remaining time until the next access is longer than the power supply rise time (step 305), the power-off state is maintained. If the remaining time until the next access is less than the power supply rise time, the power of the functional block is turned on (306), the clock of the functional block is activated (309), and the process is terminated.

  FIG. 13 compares whether the access count of the functional block exceeds the access occurrence count RO set in the control register CR, and the function block access count does not exceed the access occurrence count RO set in the control register CR. The operation and power transition diagram is shown. In FIG. 13, there is a possibility that an access will occur at the next short interval, and an unnecessary power supply rise time may occur if the prediction is lost, so the power supply is not shut down and the clock is stopped ( t1). The generation of an access request to the functional block is monitored (t1 to t2), and when an access request to the functional block is generated, the clock of the functional block is activated (t2 to t3), and the process is terminated.

  When the access count of the functional block exceeds the access occurrence count RO set in the control register CR, the power supply is shut down as in the first embodiment, and in this case, the power transition diagram of FIG. 7 is obtained.

  In the second embodiment, the power mode is executed in two stages based on the number of access to the functional block and the predicted remaining time until the next access. If the remaining number of times until the predicted next access stored in the address information storage table MT is greater than the power supply rise time and the number of occurrences of access RO of the functional block is longer than the power supply rise time, It is determined that an access delay does not occur, and the power supply is turned off as in the first embodiment.

  On the other hand, if the function block access count RO is less than or equal to the power supply rise time or the predicted remaining time until the next access stored in the address information storage table MT is smaller than the power supply rise time, It is determined that an access delay due to time occurs, and the clock to the functional block is stopped without shutting off the power as shown in FIG.

  Therefore, unlike Patent Document 1, it does not take time until the power is turned off after the access is lost, and after the power is turned off, an access delay occurs due to a delay in the rise of the power when the power is turned off. Less likely to degrade performance.

  According to the second embodiment, the power mode can be realized by selecting the power operation state from the three states of normal operation, clock stop, and power-off according to the size of the access interval and the number of learning of the address information storage table MT.

  As described above, according to each of the above-described embodiments, it is not necessary to wait for the number n of cycles until the shutdown required in the prior art of Patent Document 1 and the like. Low power consumption can be realized. Further, according to the second embodiment, the access delay (10 ms to 100 ms) due to the rise time at the time of recovery from power shutdown is concealed to reduce the system performance degradation.

  Although the embodiments have been described above, the present invention is not limited only to the configurations of the above embodiments, and of course includes various modifications and corrections that can be made by those skilled in the art within the scope of the present invention. It is.

  Since the power consumption can be reduced without deteriorating the operation speed of the semiconductor device, the present invention can be used for a wide variety of semiconductor devices.

10: Bus monitor 21: CPU
22: ROM / RAM (functional block)
23: CDROM controller (functional block)
24: HDD control unit (functional block)
25: Display device control unit (functional block)
50: Semiconductor device AC: Address comparison unit AM: Access input interval measurement unit CR: Control register D1: Power switch MJ: Mode switching execution unit MT: Address information storage table TT: Temporary storage table 1-6: Input / output signals A: Address signals A1 to A5: Bus B: Main bus D2 to D5: Power control signal MA: Address (address information storage table)
MC: Number of accesses (address information storage table)
MS: Access interval (address information storage table)
R0: Number of times access occurred (control register)
TA: Address (temporary storage table)
TS: Interval from next access (temporary storage table)

Claims (13)

With the main bus,
A plurality of functional blocks connected to the backbone bus;
Monitor the backbone bus, extract from the data on the backbone bus the end address of access to the functional block for each functional block, and the access interval until the next access to the functional block, and the termination When an address is accessed, the function block is powered off, and the function block is powered before the access interval so that the function block can be accessed when the access interval elapses. A bus monitor that controls to start up,
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the access interval is a shortest period until the next access is made to the functional block after accessing the end address of the functional block. The bus monitor
An access input interval measuring unit that extracts an end address of access to the functional block for each functional block from data on the backbone bus, and an access interval until the functional block is accessed next;
A storage table that stores an end address and access interval of the extracted access;
Based on the data stored in the storage table, a mode switching execution unit that performs power control of each functional block;
The semiconductor device according to claim 1, further comprising: The bus monitor includes a control register in which information including an address range for each functional block and a time required for power on for each functional block is stored,
Identify which functional block the data on the backbone bus accesses from the address range for each functional block of the control register;
4. The semiconductor device according to claim 3, wherein the timing for starting to start up the power supply of the functional block is determined using time information necessary for the power supply startup for each functional block of the control register. The storage table comprises a temporary storage table and an address information storage table,
The access input interval measurement unit checks whether the end address stored in the temporary storage table and the access interval are reproducible, and moves registration to the address information storage table for reproducible data,
5. The semiconductor device according to claim 3, wherein the mode switching execution unit performs power control of each functional block based on an access end address and an access interval registered in the address information storage table.   The access input interval measuring unit measures the last accessed address for each functional block and the time until the next access to the functional block, and stores the last accessed address in the temporary storage table. If it matches the end address, the access interval stored in the temporary storage table corresponding to the end address is compared with the next access time measured by the access input interval measurement unit, and the shorter one is calculated. 6. The semiconductor device according to claim 5, wherein the access interval is updated according to the time.   When the mode switching execution unit detects an access to an address stored in the address information storage table, if the number of accesses to the address does not satisfy a predetermined number, or the access interval is stored in the control register. 7. The semiconductor according to claim 5, wherein when the time required for power-on of the function block to be stored is less than the time required for the function block, the clock of the function block is stopped without shutting off the power of the function block. apparatus. Each functional block is provided with a power switch,
The said mode switching execution part controls interruption | blocking and starting of the said power supply by controlling conduction | electrical_connection / cutoff of the power switch provided in each said functional block, The any one of Claim 3 thru | or 7 characterized by the above-mentioned. The semiconductor device described. In a semiconductor device in which a plurality of functional blocks that can be turned on and off independently are connected to a common bus,
Monitoring the data on the bus, extracting an end address of access to the functional block for each functional block, and an access interval until the next access to the functional block;
Shutting off the power of the functional block when the end address is accessed;
Starting the power supply of the functional block before the access interval elapses so that the function block can be accessed when the access interval elapses;
A power supply control method for a semiconductor device, comprising: The semiconductor device includes an address information storage table that stores an end address and access interval for performing the power control, and a temporary storage table that stores an end address and an access interval as candidates for the address information storage table.
The access interval stored in the temporary storage table is compared with the access interval stored in the address information storage table. If the access interval stored in the temporary storage table is larger, the access interval is stored in the address information storage table. 10. The method of controlling a power supply for a semiconductor device according to claim 9, further comprising the step of replacing the end address and access interval with the end address and access interval stored in the temporary storage table.   The last accessed address for each functional block and the time until the next access to the functional block are measured, and the last accessed address is stored in either the address information storage table or the temporary storage table. If the time until the next access is longer than the access interval recorded in the temporary storage table, the end address and the access interval stored in the temporary storage table are 11. The method for controlling the power supply of a semiconductor device according to claim 10, further comprising the step of switching according to the measured address and time.   The last accessed address for each functional block and the time until the next access to the functional block is measured, and the last accessed address matches the end address stored in the temporary storage table, The method further comprises a step of updating the access interval with the measured time until next access if the time until the next access is smaller than the access interval corresponding to the end address. A power control method for a semiconductor device according to 10 or 11.   The last accessed address for each functional block and the time until the next access to that functional block is measured, and the last accessed address matches the end address stored in the address information storage table, If the time until the next access is smaller than the access interval corresponding to the end address, the access interval is further updated with the measured time until the next access. Item 13. A power control method for a semiconductor device according to any one of Items 10 to 12.

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