JP2018181248A - Information processing device and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid the disappearance of information recorded in volatile storage means even if a power supply of an information processing device is stopped.SOLUTION: When a CPU 11 hangs, a user turns off a power supply switch to eliminate this state. Even though this off operation stops the supply of power from a power supply 4 to an SoC 10, power stored in capacitor 9 is supplied instead of the stop of the supply of the power. The CPU 11 collectively writes a log written in an SRAM 12 to store the log in an NVRAM 6 by transferring the log to the NVRAM through an SPI bus 21 while the power is supplied from the capacitor 9 when it is detected that power supply 1 is turned off.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an information processing apparatus and program.

  Conventionally, it has been common to connect memories with a parallel interface. Data can be written from the CPU (Central Processing Unit) incorporated in the integrated circuit to the non-volatile storage device with a single storage instruction of the data designated by the address.

JP, 2017-10117, A

  An object of the present invention is to avoid the loss of information recorded in volatile storage means, even when the power supply of the information processing apparatus is stopped, when information is stored in the volatile storage means.

  An information processing apparatus according to the present invention comprises: recording means for recording information in volatile storage means; and the control by giving a delay immediately before the supply of power to the control unit is stopped when the power is stopped. And means for delaying the stop of the supply of power to the volatile storage means, and the information recorded in the volatile storage means while the stop of the supply of power is delayed by the delay means And transfer means for transferring data to the non-volatile storage means.

  Further, the power storage unit is provided, and the delay unit is characterized in that the power stored in the storage unit is supplied to the control unit when the power is stopped by a user operation.

  Further, the delay means is characterized by delaying a time until the supply of power from the power supply to the control unit is stopped when the power supply is stopped by a user operation.

  Further, the volatile memory means is connected in parallel with the control unit in an integrated circuit.

  Further, the non-volatile storage means is connected to an integrated circuit incorporating the control unit via a serial interface.

  A program according to the present invention includes the recording means for recording information in a volatile storage means, the control according to the present invention by giving a delay immediately before the supply of power to the control unit is stopped when the power is stopped. And means for delaying the stop of the supply of power to the volatile storage means, the information recorded in the volatile storage means being non-volatile while the stop of the supply of power is delayed by the delay means It functions as a transfer means for transferring data to the nature storage means.

  According to the first aspect of the present invention, even if the power supply of the information processing apparatus is stopped, it is possible to avoid the loss of the information recorded in the volatile storage means.

  According to the second aspect of the invention, the information stored in the volatile storage means can be transferred to the non-volatile storage means using the power stored in the storage means.

  According to the third aspect of the present invention, even when the power is shut down by the user operation, the power supply supplied from the power supply is used to be recorded in the volatile storage means by delaying the stopping of the power supply. Information can be transferred to the non-volatile storage means.

  According to the fourth aspect of the present invention, it is possible to avoid the loss of the information recorded in the volatile storage means connected in parallel with the control unit in the integrated circuit.

  According to the fifth aspect of the present invention, the information recorded in the volatile storage means can be transferred to the non-volatile storage means connected with the integrated circuit by the serial interface.

  According to the sixth aspect of the present invention, even if the power supply of the information processing apparatus is stopped, it is possible to avoid the loss of the information recorded in the volatile storage means.

It is a block block diagram which shows the principal part of a structure of Embodiment 1 of the information processing apparatus which concerns on this invention. FIG. 2 is a schematic internal configuration diagram of SoC in the first embodiment. 7 is a flowchart showing processing upon power saving mode transition in the first embodiment. 5 is a flowchart showing return processing from a power saving mode according to the first embodiment. FIG. 10 is a flowchart in the case where the CPU hangs up in the process of transition to the power saving mode according to the first embodiment. FIG. 5 is a flowchart showing processing executed after CPU is reset in the first embodiment. FIG. 16 is a block diagram showing an essential part of a configuration of an information processing device in a second embodiment.

  Hereinafter, preferred embodiments of the present invention will be described based on the drawings.

Embodiment 1
FIG. 1 is a block diagram showing the main part of the configuration of an embodiment of the information processing apparatus according to the present invention. The power supply 1, the power switch 2 and the substrate 3 are shown in FIG. 1. The power source 1 incorporates an AC / DC converter, has a function of converting a commercial power source (AC power source) into a DC power source, and serves as a power source for supplying power to the substrate 3. The power switch 2 is a power switch of this device, and when it is turned off, the supply of power to the entire device including the power source 1 and the substrate 3 is stopped.

  The substrate 3 includes a power supply 4, a system memory 5, an NVRAM (Non-Volatile RAM) 6, a ROM (Read Only Memory) 7, various interfaces (I / F) 8, a capacitor 9 and a SoC (System-on-a-Chip). ) Is mounted. The power supply 4 incorporates a DC / DC converter, has a function of stepping down the DC voltage from the power supply 1, and serves as a power supply for supplying power to the SoC 10. The system memory 5 is a memory area used by an OS (Operating System). In the present embodiment, although a case where Linux (registered trademark) is installed as an OS is described as an example, the present invention is not limited to this.

  The NVRAM 6 is a non-volatile memory of which the content is not lost even if the power switch 2 is turned off among the RAMs which can be freely read and written. In the present embodiment, the NVRAM 6 is formed by combining a general static random access memory (SRAM) with a battery (backup battery) so that power is always supplied. The ROM 7 is a read only storage unit. By the way, it is assumed that the information processing apparatus (computer) in the present embodiment is installed in an image forming apparatus such as a multifunction peripheral. Therefore, although devices such as a fuser unit and a scanner are also connected to the SoC 10, the interface for connecting them is not used in the description of the present embodiment, so various interfaces (I / F) 8 and It is illustrated collectively.

  The capacitor 9 is provided as a storage means, and accumulates the power necessary to complete the transfer of all the information recorded in the SRAM 12 of the SoC 10 to the NVRAM 6 as apparent from the operation of the SoC 10 described later.

  FIG. 2 is a schematic internal configuration diagram of the SoC 10 in the present embodiment. The SoC 10 is an integrated circuit product designed to integrate a function for application as well as a function that a general microcontroller has, such as a processor core, and to function as a system in cooperation. In the present embodiment, the SoC 10 is described as an example of the integrated circuit, but the present invention is not limited to this. For example, an integrated circuit such as Application Specific Standard Produce (ASSP) may be used.

  The SoC 10 incorporates a CPU 11, an SRAM 12, an SPI (Serial Peripheral Interface) controller 13, and an internal bus 14. The internal bus 14 is a relatively high-speed parallel interface bus, to which the system memory 5 and various interfaces 8 are connected in addition to the built-in components 11 to 13. The CPU 11 executes various programs. The SRAM 12 is a type of readable and writable RAM, and is a volatile memory for temporarily retaining data. The SRAM 12 built in the SoC 10 is easier to control than the NVRAM 6 for recording information.

  The SPI controller 13 is a controller of the SPI bus 21 connecting the NVRAM 6 and the ROM 7 in this embodiment. The SPI bus 21 is a bus that connects devices used in a computer and is a kind of serial bus that requires a smaller number of connection terminals than a parallel interface (parallel bus), but is a serial interface and is therefore relative. As slow as possible.

  By the way, conventionally, the SoC 10 and the NVRAM 6 mounted on the information processing apparatus are generally connected by a parallel interface. Therefore, from the CPU 11 incorporated in the SoC 10, data can be written to the non-volatile memory with only one write instruction of the data specified by the address.

  In recent years, the use of a parallel interface as the interface of the SoC 10 has decreased, and it has become mainstream to adopt a serial interface such as SPI in order to reduce the number of device connection terminals although it is relatively slow. The serial interface requires the CPU 11 to write data to the non-volatile memory by a plurality of read / write instructions to the controller (SPI controller 13 in the present embodiment) of the serial interface.

  Therefore, storage of information in NVRAM 6 could be realized with one instruction in the case of a parallel interface, but in the case of a serial interface, writing control of information has to be complicated because it is necessary to combine a plurality of instructions. It was not. In particular, during transition from a normal state to a low power state or during a transition from a low power state to a normal state, it relates to a device mounted on an image forming apparatus for analysis in the case of failure. Although the log needs to be written and saved in the NVRAM 6, the write control becomes complicated.

  Therefore, in the present embodiment, writing of information to the NVRAM 6 can be easily performed by effectively using the SRAM 12 connected to the CPU 11 via the internal bus 14 which is a parallel bus. However, the SRAM 12 loses the recorded log when the power supply is stopped. Therefore, in the present embodiment, when it is detected that the supply of power to SoC 10 incorporating CPU 11 and SRAM 12 is stopped, the supply of power can be made by giving a delay immediately before the supply of power to SoC 10 is stopped. It is characterized in that it has a configuration to delay the stop of the. Specifically, the power stored in the capacitor 9 is effectively used to transfer the information stored in the SRAM 12 to the NVRAM 6 so that the information can be written and saved.

  Next, the operation of the SoC 10 in the present embodiment will be described.

  The SoC 10 operates in a standby mode waiting for a user operation as a normal state. When an operation instruction is given by the user, processing such as copying or scanning is executed according to the user operation instruction. When the process is completed, the process returns to the instruction standby state. The CPU 11 writes the data handled by executing the program in the standby mode by writing the data in the NVRAM 6. In addition, while operating in the standby mode, at least the power necessary for data transfer from SRAM 12 to NVRAM 6 is stored in capacitor 9.

  If no operation is performed for a predetermined time while operating in the standby mode, the SoC 10 transitions to the power saving mode (low power state). In the power saving mode, the supply of power to the SoC 10 or the like is stopped to reduce power consumption, but since the power is not supplied to the SoC 10, the CPU 11 stops its operation and the SRAM 12 can not hold data. That is, the data held in the SRAM 12 is lost. Also, during normal times (during operation in standby mode), the functions installed in Linux can be used, but at the timing of transition to power saving mode, there are restrictions on the functions that can be used, so control for recording information (Exclusive control) becomes complicated. The process executed at the time of transition to the power saving mode (during transition) will be described using the flowchart shown in FIG.

  In the process executed at the time of transition to the power saving mode, a history (log) is recorded each time one transition process is completed, so that it is easy to grasp to what stage the transition process has been completed. Therefore, when the CPU 11 starts executing a predetermined program for shifting to the power saving mode, the CPU 11 switches the log recording destination from the NVRAM 6 to the SRAM 12 (step 101). Then, when the above processing is completed, the log in which the processing content is described is written in the SRAM 12 (step 102).

  Thereafter, the current state of the device is collected for each device, and the collected information is written to the SRAM 12 as a log. That is, when the CPU 11 executes the migration process including the process of stopping the power supply to the device by acquiring information on one device (steps 103-1 to n), the log on the implemented migration process is stored in the SRAM 12 Write (steps 104-1 to n). The information to be recorded as a log includes information indicating that the power-off of the device has been normally completed, and information specifying the device on which the migration process is to be performed next.

  When the migration processing and log writing are completed for all devices, the CPU 11 writes and saves the logs written in the SRAM 12 collectively by transferring them to the NVRAM 6 via the SPI bus 21 (step 105). ). Unlike the parallel interface, in the case of data transfer via the SPI bus 21, multiple read / write instructions may be required. However, in the present embodiment, all devices are in the power-off state, and in the case of a multi-core, the other CPUs are also in the stop state. Therefore, write control to the NVRAM 6 can be simplified because exclusive control does not have to be considered.

  Subsequently, a return process executed when returning from the power saving mode to the standby mode will be described using the flowchart shown in FIG.

  In the return processing, basically, the processing may be performed in the reverse order to the processing at the time of transition to the power saving mode. That is, when the CPU 11 starts execution of a predetermined program for returning to the standby mode, it writes a log to the effect that the execution of the return processing is started in the SRAM 12 (step 111).

  After that, when the CPU 11 executes recovery processing such as starting supply of power by turning on the power supply of the device for each device (steps 112-1 to n), the log regarding the implemented recovery processing is stored in the SRAM 12 (Step 113-1 to n).

  When the above recovery processing and log writing are completed for all devices, and power can be supplied to the NVRAM 6 so that the log can be recorded, the CPU 11 collectively collects the logs written in the SRAM 12 into the SPI bus. The data is written and saved by transferring to the NVRAM 6 through 21 (step 114). Then, the CPU 11 switches the log recording destination from the SRAM 12 to the NVRAM 6 (step 115).

  The above is the case where the transition to the power saving mode and the return from the power saving mode have ended normally, but here the processing in the case where a failure occurs during the transition to the power saving mode is shown in FIGS. It demonstrates using the flowchart shown. The same processes as in FIG. 3 are assigned the same reference numerals, and the description thereof will be omitted as appropriate.

  First, the log recording destination is switched to the SRAM 12 (step 101), and the log of the content is written and stored in the SRAM 12 (step 102). Then, transition processing of the power saving mode to each device and writing of the log are sequentially performed (steps 103-1 to 104-1). It is assumed that the CPU 11 hangs (freezes) due to the occurrence of a failure during execution of the transition processing x (1 ≦ x ≦ n) in the process of the processing (step 103-x).

  When the CPU 11 hangs up, the user is considered to turn off the power switch 2 and turn it on to restart the image forming apparatus and recover the state of the image forming apparatus in order to eliminate the state of the hang. In the conventional case, the power supply to the SRAM 12 is stopped by the user's operation of turning off the power switch 2. That is, the information held in the SRAM 12 will be lost soon after being saved in the NVRAM 6.

  When the user turns off the power switch 2 (step 106), the power supply 1 stops the supply of power to the substrate 3. Along with this, in the substrate 3, the power supply 4 stops the supply of power to the SoC 10. On the other hand, capacitor 9 starts discharging when the supply of power from power supply 4 is stopped. As a result, the capacitor 9 supplies power to the SoC 10 instead of the power supply 4.

  By the way, when the power supply 1 is turned off, the CPU 11 in the freeze state is reset. After reset, the CPU 11 can detect that the power supply 1 is turned off. Therefore, when detecting that the power supply 1 is turned off (Y in step 121), the CPU 11 writes and saves the logs written in the SRAM 12 collectively by transferring them to the NVRAM 6 through the SPI bus 21 ( Step 105). Although the CPU 11 executes a predetermined error process and the like following the writing of the log into the NVRAM 6, the description is omitted because it is not the gist of the present embodiment. After that, the SoC 10 stops when sufficient power supply from the capacitor 9 can not be received. On the other hand, when the CPU 11 is not reset due to the turning-off operation of the power switch 2 (N in step 121), the CPU 11 executes a normal start process (step 122).

  Here, the log writing process (step 104-n) corresponding to the last migration process (step 103-n) shown in FIG. 3 can not be executed until the log up to the migration process x-1 is written to NVRAM 6 Will be As a result, by analyzing the log written in the NVRAM 6, it may be possible to identify that a failure has occurred at the time of execution of the migration processing x, and it may be possible to identify the cause of the failure by analyzing the contents of the log.

  According to the present embodiment, the write control of the log to the NVRAM 6 can be simplified by effectively using the SRAM 12 built in the SoC 10 as described above. Further, by effectively using the power stored in capacitor 9, the power supply to SoC 10 is not immediately stopped with the turning-off operation of power switch 2, but the power supply is suspended immediately before the power supply is stopped. To be able to have This makes it possible to securely keep the log in the NVRAM 6.

  In the present embodiment, the capacitor 9 as the storage means is provided on the substrate 3, but it may be provided other than the substrate 3 or an existing storage means may be used.

Second Embodiment
FIG. 7 is a block diagram showing the main part of the configuration of the information processing apparatus in the present embodiment. The same components as in FIG. 1 are assigned the same reference numerals and descriptions thereof will be omitted. The information processing apparatus in the present embodiment has a relay circuit 22 provided between the commercial power supply and the power supply 1, and the power supply 1 includes the AC-DC converter 23 as in the first embodiment. In addition to, the switching unit 24 is provided. The switching unit 24 performs on / off switching control of the relay circuit 22 in response to the on / off operation of the power switch 2. In the present embodiment, in place of the capacitor 9 in the first embodiment, the relay circuit 22 and the switching unit 24 are provided as delay means. The configuration of SoC 10 may be the same as that of the first embodiment.

  In the first embodiment, the user turns off the power switch 2 as a trigger to receive power supply from the capacitor 9 and write data to the NVRAM 6 of the log. This embodiment is the same in that the user turns off the power switch 2 as a trigger, but in this embodiment, the power supply from the power source 1 is immediately supplied according to the off operation of the power switch 2. The power supply 1 is configured to stop the supply of power after delaying for a predetermined time after the turning-off operation of the power supply switch 2 instead of stopping it. In other words, the power supply switch 2 has a delay from when the power switch 2 is turned off until the power supply 1 actually stops supplying power. Here, the "predetermined time" refers to a time length longer than the time required to complete the process of transferring the log to the NVRAM 6.

  Hereinafter, although the operation in the present embodiment will be described, it may be basically the same as the first embodiment. The power saving mode transition process described with reference to FIGS. 3 and 4 and the return process from the power saving mode may be the same, and thus the description thereof will be omitted. In addition, the same processing flow may be applied when the CPU hangs up during the process of transition to the power saving mode described with reference to FIGS. 5 and 6. However, the operation when the power switch 2 is turned off is different. When the power switch 2 is on, the switching unit 24 controls the relay circuit 22 to be in a closed state. That is, power from the commercial power source is in a state of being supplied to the power source 1.

  Here, when it is detected that the power switch 2 has been turned off by the user (step 106), the switching unit 24 resets the CPU 11. When the reset CPU 11 detects an OFF operation by the user, the CPU 11 collectively transfers the logs written in the SRAM 12 to the NVRAM 6 via the SPI bus 21 to write and save (step 105).

  The switching unit 24 controls the relay circuit 22 to open by time-up when a predetermined time has elapsed after the user performs an off operation. Thereby, the supply of power to the substrate 3 is stopped. The transfer of the log to the NVRAM 6 is completed before the relay circuit 22 is controlled to open. After that, when the power switch 2 is turned on by the user, the switching unit 24 controls the relay circuit 22 to close. Thereby, the supply of power to the substrate 3 is started and the OS is started.

  As described above, according to the present embodiment, even when the power is turned off by the user, the power is supplied from the power source 1 to the substrate 3 for a predetermined time, and the log recorded in the SRAM 12 while being supplied Was able to be transferred to NVRAM6. This makes it possible to securely keep the log in the NVRAM 6.

  In each embodiment, the configuration is shown in which the stop of the supply of power to the SoC 10 is delayed, but both of these configurations may be provided to the information processing apparatus.

  In the present embodiment, a log is used as an example of the information to be written to the NVRAM 6, but the information need not be limited to the log.

  Further, although the computer incorporated in the image forming apparatus has been described as an example in the present embodiment, the present invention is not limited to this, and is applied to a computer incorporated in various devices such as PC (Personal Computer). It is possible.

1,4 power supply, 2 power supply switch, 3 boards, 5 system memory, 6 NVRAM, 7 ROM, 8 various interfaces (I / F), 10 SoC, 11 CPU, 12 SRAM, 13 SPI controller, 14 internal bus, 21 SPI Bus, 22 relay circuit, 23 AC-DC converter, 24 switching unit.

Claims (6)

Recording means for recording information in volatile storage means;
Delay means for delaying the stop of the supply of power to the control unit and the volatile storage means by giving a delay immediately before the supply of power to the control unit is stopped when the power supply is stopped;
Transfer means for transferring the information recorded in the volatile storage means to the non-volatile storage means while the stop of the power supply is delayed by the delay means;
An information processing apparatus comprising: Have storage means,
The information processing apparatus according to claim 1, wherein the delay unit supplies the power stored in the storage unit to the control unit when power is stopped by a user operation.   The information processing apparatus according to claim 1, wherein the delay unit delays a time until the supply of power from the power supply to the control unit is stopped when the power supply is stopped by a user operation.   The information processing apparatus according to claim 1, wherein the volatile storage unit is connected in parallel with the control unit in an integrated circuit.   The information processing apparatus according to claim 1, wherein the nonvolatile storage unit is connected to an integrated circuit including the control unit via a serial interface. Computer,
Recording means for recording information in volatile storage means,
Delay means for delaying the stop of the supply of power to the control unit and the volatile storage means by giving a delay immediately before the supply of power to the control unit is stopped when the power supply is stopped;
Transfer means for transferring the information recorded in the volatile storage means to the non-volatile storage means while the stop of the power supply is delayed by the delay means;
Program to function as.

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