JP2011013914A - Power-saving controller and power-saving control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power-saving controller and a power-saving control method, allowing easy mounting of transition processing to a power-saving mode of a CPU (Central Processing Unit) during poling processing, allowing a high-speed bus use load from the CPU during the poling processing to be reduced, and allowing contribution even to performance improvement of the whole system.SOLUTION: When execution of the poling processing is needed in the CPU 101, a power-saving mode management part 102 substitutionally executes the poling processing. By meantime transiting the CPU 101 to the power-saving mode, the CPU 101 does not need complicated processing for transition to the power-saving mode or consideration of an interrupt condition for restoration from the power-saving mode to easily mount the transition processing to the power-saving mode of the CPU 101 during the poling processing, and the high-speed bus use load from the CPU 101 during the poling processing is reduced to contribute even to the performance improvement of the whole system.

Description

  The present invention relates to a power saving control device and a power saving control method.

  In recent computer systems, improvement in processing capability is required, while power saving is required. For this reason, a CPU (Central Processing Unit) provided in the computer system is also equipped with a power saving mode, and it is necessary to control these efficiently to save the CPU power.

  In conventional CPU power saving control, the CPU itself determines whether or not the transition to the power saving mode is possible, and if possible, the transition processing to the power saving mode is executed (see Patent Document 1). In addition, since the return from the power saving mode to the normal mode was performed only by a specific interrupt signal, the return condition from the power saving mode to the normal mode cannot be arbitrarily changed, and the mode can be changed to the power saving mode. The state was limited.

JP-A-2005-346708

  By the way, in computer programming, a polling process is often used in which data of a specific address is repeatedly referred to and waited until an expected value is reached. During polling processing, it is often not possible to execute subsequent processing or other processing until the data at a specific address reaches the expected value, so it is desirable to transition the CPU to the power saving mode. It may not be possible to transition to the power saving mode because the transition process to the mode is complicated or the interrupt generation condition cannot be satisfied. Further, as described above, during the polling process, it is often impossible to execute subsequent processes or other processes until the data at a specific address reaches an expected value, but the CPU does not perform any process according to the program. In spite of the fact that the data of a specific address is repeatedly referenced based on a clock with a constant frequency, the power consumption does not change as usual, and the use of an unnecessary address bus or data bus prevents the processing of peripheral circuits. There is a problem.

  The disclosed technology has been made in view of the above, and can easily implement the transition process of the CPU to the power saving mode during the polling process, and can use the high-speed bus from the CPU during the polling process. It is an object of the present invention to provide a power saving control apparatus and a power saving control method that can contribute to improving the performance of the entire system by reducing the load.

  In one aspect, the power-saving control device disclosed in the present application provides the polling when the arithmetic device needs to execute a polling process that repeatedly refers to the data and waits until the data at the specific address reaches an expected value. A determination means for determining whether or not the data matches the expected value by executing processing, and control so that the arithmetic unit transitions to a power saving mode until it is determined that the data matches the expected value; And a control means.

  Further, in another aspect, the power saving control method disclosed in the present application is a power saving control method executed by a power saving control device that controls a transition of the main control unit to the power saving mode and a return from the power saving mode. The power saving control device includes a sub-control unit that performs processing at a lower frequency than the main control unit and a storage unit, and the determination unit that is executed by the sub-control unit expects data at a specific address. A determination step of determining whether or not the data matches the expected value by executing the polling process when the arithmetic unit needs to execute a polling process that repeatedly refers to the data and waits until a value is reached And a control step in which the control means controls the arithmetic device to transition to the power saving mode until it is determined that the data matches the expected value.

  According to one aspect of the power saving control device and the power saving control method disclosed in the present application, the CPU can easily implement the transition process to the power saving mode during the polling process, and the CPU during the polling process. It is possible to reduce the high-speed bus usage load and contribute to improving the performance of the entire system.

FIG. 1 is a block diagram of the configuration of the external device control apparatus according to the first embodiment. FIG. 2 is a diagram illustrating setting values set in each register included in the external device control apparatus according to the first embodiment. FIG. 3 is a flowchart of the power saving control process performed by the external device control apparatus according to the first embodiment. FIG. 4 is a block diagram of the configuration of the external device control apparatus according to the second embodiment. FIG. 5 is a block diagram of the configuration of the external device control apparatus according to the third embodiment.

  Embodiments of a power saving control device and a power saving control method disclosed in the present application will be described below in detail with reference to the drawings. In the present embodiment, an example in which the power saving control apparatus and the power saving control method according to the present invention are applied to an external device control apparatus that controls an external device such as a peripheral device will be described. Further, the present invention is not limited to the embodiments.

  FIG. 1 is a block diagram of the configuration of the external device control apparatus according to the first embodiment. FIG. 2 is a diagram illustrating setting values set in each register included in the external device control apparatus according to the first embodiment. The external device control apparatus 100 according to the present embodiment roughly includes a CPU 101, a power saving mode management unit 102, a clock control unit 103, and an external device control unit 110. The CPU 101, the power saving mode management unit 102, and the external device control unit 110 are connected to each other via an external bus.

  The external device control unit 110 controls the peripheral device 113 connected to the external device control apparatus 100. In this embodiment, the external device control unit 110 includes an external device control circuit 112 and a status register 111. The external device control circuit 112 is for actually performing communication or control with the peripheral device 113.

  The status register 111 is a hardware register assigned to a specific address (for example, 2000h), and stores data indicating the state of the external device control circuit 112. In this embodiment, the status register 111 stores data at a specific address that the CPU 101 repeatedly refers to when polling processing is necessary. Here, the polling process is a process of repeatedly referring to the data at the specific address until the data at the specific address reaches the expected value in the program.

  The CPU 101 is an arithmetic device that executes processing based on the clock output from the clock control unit 103. In this embodiment, the CPU 101 executes processing for the external device control circuit 112 based on the clock output from the clock control unit 103.

  The power saving mode management unit 102 controls the transition of the CPU 101 to the power saving mode and the return of the CPU 101 from the power saving mode. In this embodiment, the power saving mode management unit 102 includes an address storage unit 104, an expected value storage unit 105, a condition storage unit 106, a comparator 107, a condition detection time storage unit 108, and a time monitoring unit 109.

  As shown in FIG. 2, the address storage unit 104 is an address register that stores a specific address (for example, 2000h) in which data that the CPU 101 repeatedly refers to when polling processing is necessary.

  As shown in FIG. 2, the expected value storage unit 105 is a data register that stores an expected value (for example, 0012h) of data stored in a specific address (for example, 2000h) during the polling process. In this embodiment, the expected value storage unit 105 stores the expected value of the lower 8 bits of the data stored at the specific address.

  As shown in FIG. 2, the condition storage unit 106 is a condition register that stores a comparison condition for the expected value stored in the expected value storage unit 105. In the present embodiment, the condition storage unit 106 sets a comparison condition (for example, 00FFh) indicating that the lower 8 bits of data stored at a specific address (for example, 2000h) is compared with an expected value (for example, 0012h). Remember.

  The comparator 107 executes the polling process instead of the CPU 101 when the CPU 101 needs to execute the polling process. First, the comparator 107 repeatedly refers to data from the status register 111 according to the specific address stored in the address storage unit 104. Subsequently, the comparison unit 107 (determination unit) determines whether or not the referred data matches the expected value stored in the expected value storage unit 105 in the comparison condition stored in the condition storage unit 106. To do. Specifically, the comparator 107 fetches data from the status register 111 at an appropriate period in place of the CPU 101, the logical product of the fetched data and the comparison condition stored in the condition storage unit 106, and the expected value storage unit It is determined whether the expected value stored in 105 matches. In the present embodiment, it is assumed that the comparator 107 determines whether or not the lower 8 bits of the data stored in the specific address match the expected value.

  Then, until the comparator 107 (control unit) determines that the referred data matches the expected value stored in the expected value storage unit 105 in the comparison condition stored in the condition storage unit 106, a The power_save signal (true) (a. power_save signal) is output to the clock control unit 103 to control the CPU 101 to transition to the power saving mode. On the other hand, in the comparison condition stored in the condition storage unit 106, the comparator 107 (control means), when the referred data matches the expected value stored in the expected value storage unit 105, a. (False) is output to the clock control unit 103 to control the CPU 101 to return from the power saving mode. Note that the comparator 107 performs data reference and output of the a.power_save signal at a frequency sufficiently lower than the steady frequency that the CPU 101 uses as a reference.

  As shown in FIG. 2, the condition detection time storage unit 108 is a predetermined unit that determines whether the data referenced from the status register 111 by the comparator 107 matches the expected value stored in the expected value storage unit 105. It is a timer register that stores time (for example, 60 seconds).

  The time monitoring unit 109 (measurement unit) measures the time during which it is determined whether or not the data referenced from the status register 111 by the comparator 107 matches the expected value stored in the expected value storage unit 105. / W Timer.

  In this embodiment, the comparator 107 refers to the status register 111 when the time measured by the time monitoring unit 109 exceeds the predetermined time stored in the condition detection time storage unit 108 (that is, within the predetermined time). When the data does not match the expected value stored in the expected value storage unit 105), a. Power_save signal (false) is output to the clock control unit 103 so that the CPU 101 returns from the power saving mode. Control.

  The clock control unit 103 supplies the CPU 101 with a reference clock when the CPU 101 executes processing. More specifically, when the a. Power_save signal (false) is output from the comparator 107, the clock control unit 103 outputs a clock (b. CPU CLK) to the CPU 101 at a steady frequency. On the other hand, when the a power_save signal (true) is output from the comparator 107, the clock control unit 103 stops the output of the clock (b. CPU CLK) or the clock (b. CPU CLK) at a frequency lower than the steady frequency. ) Is output to the CPU 101.

  Next, the flow of the power saving control process in the external device control apparatus 100 according to the present embodiment will be described with reference to FIG. FIG. 3 is a flowchart of the power saving control process performed by the external device control apparatus according to the first embodiment.

  The comparator 107 determines whether or not the polling process is not necessary in the CPU 101 (that is, whether or not the data referenced from the status register 111 matches the expected value stored in the expected value storage unit 105). A. The power_save signal (false) is output to the clock control unit 103 to instruct the clock supply at the steady frequency (step S301).

  When the CPU 101 needs to execute the polling process, the CPU 101 requests the comparator 107 to perform the polling process, and also stores the address storage unit 104, the expected value storage unit 105, the condition storage unit 106, and the condition detection time storage. A specific address, an expected value, a comparison condition, and a predetermined time are set for the unit 107 (step S302).

  When the CPU 101 is requested to perform polling processing, the comparator 107 repeatedly refers to the data from the status register 111 in accordance with the specific address stored in the address storage unit 104 and also compares the comparison condition stored in the condition storage unit 106. , It is determined whether the referenced data matches the expected value stored in the expected value storage unit 105. If the referenced data does not match the expected value, a. Power_save signal (true) Is output to the clock control unit 103 to control the CPU 101 to transition to the power saving mode (step S303).

  When the a.power_save signal (true) is output from the comparator 107, the clock control unit 103 stops supplying the clock to the CPU 101, or outputs the clock to the CPU 101 at a frequency lower than the steady frequency (step S304). ).

  Then, the comparator 107 determines that a. Power_save when the referenced data matches the expected value, or when the time measured by the time monitoring unit 109 exceeds the predetermined time stored in the condition detection time storage unit 108. (False) is output and the CPU 101 is controlled to return from the power saving mode (step S305).

  When the a.power_save signal (false) is output from the comparator 107, the clock control unit 103 supplies a clock at a steady frequency to the CPU 101 (step S306). When the supply of the clock from the clock control unit 103 is resumed, the CPU 101 executes subsequent processing or other processing.

  As described above, according to the external device control apparatus 100 according to the present embodiment, when the CPU 101 needs to execute the polling process, the power saving mode management unit 102 (comparator 107) executes the polling process instead. In the meantime, by causing the CPU 101 to transition to the power saving mode, the CPU 101 does not need to consider complicated processing for transition to the power saving mode and interrupt conditions for returning from the power saving mode. It is possible to easily implement the transition processing of the CPU 101 to the power saving mode in the middle, and to reduce the high-speed bus usage load from the CPU 101 during the polling processing, thereby contributing to the improvement of the performance of the entire system.

  In this embodiment, the transition of the CPU to the power saving mode is entrusted to a plurality of power saving mode management units. In addition, description is abbreviate | omitted about the location similar to the above-mentioned Example, and only a different location is demonstrated.

  FIG. 4 is a block diagram of the configuration of the external device control apparatus according to the second embodiment. The external device control apparatus 400 according to the present embodiment is different from the external device control apparatus 100 according to the first embodiment in that the external device control apparatus 400 includes a plurality of power saving mode management units 102 and detection units 401.

  When the detection unit 401 (detection unit) detects that the a. Power_save signal (true) is output from the comparators 107 of all the power saving mode management units 102, the detection unit 401 (detection unit) outputs the c. Power_save signal (true). It outputs to the clock control part 103, and makes CPU101 change to a power saving mode. On the other hand, when detecting that the a. Power_save signal (false) is output from the comparator 107 of the at least one power saving mode management unit 102, the detecting unit 401 clocks the c. Power_save signal (false). It outputs to the control part 103 and makes CPU101 return from a power saving mode.

  As described above, according to the external device control apparatus 400 according to the present embodiment, the transition of the CPU 101 to the power saving mode is more finely performed by entrusting the transition to the power saving mode of the CPU 101 to the plurality of power saving mode management units 102. Can be controlled.

  In this embodiment, when the CPU is controlled to shift to the power saving mode and a preset additional condition is satisfied, the CPU is shifted to the power saving mode. In addition, description is abbreviate | omitted about the location similar to the above-mentioned Example, and only a different location is demonstrated.

  FIG. 5 is a block diagram of the configuration of the external device control apparatus according to the third embodiment. The external device control apparatus 500 according to the present embodiment is different from the above-described embodiment in that the power saving mode management unit 501 includes an additional condition monitoring unit 502.

  The additional condition monitoring unit 502 (monitoring means) outputs the a.power_save signal (true) from the comparator 107 and the a.power_save signal output from the comparator 107 is longer than a specified time (true). Only a hardware timer that outputs an a.power_save signal (true) to the clock controller 103. As a result, when the time required for the polling process is short, the CPU 101 can be controlled not to shift to the power saving mode.

  In this embodiment, a hardware timer is used as the additional condition monitoring unit 502. However, when an a.power_save signal (true) is output from the comparator 107 and a predetermined additional condition is satisfied, As long as the a.power_save signal (true) is output to the clock control unit 103, the present invention is not limited to this. For example, if a temperature sensor is used as the additional condition monitoring unit 502 and the a.power_save signal (true) is output from the comparator 107 and the detected temperature is equal to or lower than a specified temperature, control is performed so that the CPU 101 does not transition to the power saving mode. . Further, the additional condition monitoring unit 502 determines whether or not the conditions for executing the polling process and the history of the monitoring time during which the polling process is executed satisfy the predetermined additional conditions, and a. Power_save A signal may be output.

  As described above, according to the external device control apparatus 500 according to the present embodiment, when the CPU 101 is controlled to shift to the power saving mode and the preset additional condition is satisfied, the CPU 101 is shifted to the power saving mode. Thus, for example, when the time required for the polling process is short, the CPU 101 can be controlled so as not to shift to the power saving mode, so the transition of the CPU 101 to the power saving mode is controlled more finely. be able to.

  The program executed by the external device control apparatus of this embodiment is provided by being incorporated in advance in a ROM (Read Only Memory) or the like. The program executed by the external device control apparatus of this embodiment is a file in an installable format or an executable format, and is a CD (Compact Disk) -ROM, a flexible disk (FD), a CD-R, a DVD (Digital Versatile Disk). ) Or the like may be recorded and provided on a computer-readable recording medium.

  Furthermore, the program executed by the external device control apparatus of the present embodiment may be provided by being stored on a computer connected to a network such as the Internet and downloaded via the network. Further, the program executed by the external device control apparatus of the present embodiment may be configured to be provided or distributed via a network such as the Internet.

  The program executed by the external device control apparatus according to the present embodiment has a module configuration including the above-described units (power saving mode management unit, detection unit, additional condition monitoring unit, etc.). As actual hardware, The CPU (processor) as a sub-control unit that operates at a frequency sufficiently lower than the steady frequency of the CPU 101 (main control unit) reads the program from the ROM and executes it, so that the respective units are loaded on the main storage device, A power saving mode management unit, a detection unit, an additional condition monitoring unit, and the like are generated on the main storage device.

100, 400, 500 External device control apparatus 101 CPU
102 power saving mode management unit 107 comparator 109 time monitoring unit 401 detection unit 502 additional condition monitoring unit

Claims (8)

Whether or not the data matches the expected value due to the execution of the polling process when the processing unit needs to execute a polling process that repeatedly refers to the data and waits until the data at the specific address reaches the expected value A judging means for judging whether or not
Control means for controlling the arithmetic device to transition to a power saving mode until it is determined that the data matches the expected value;
A power-saving control device comprising: Measuring means for measuring a time for determining whether or not the data matches the expected value;
2. The power saving control device according to claim 1, wherein the control unit further controls to shift to the power saving mode when the measured time exceeds a predetermined time. 3. A plurality of power saving mode management units including the determination unit and the control unit;
Detecting means for transitioning to the power saving mode when it is detected that the control means of all the power saving mode management units is controlled to transition to the power saving mode;
The power saving control device according to claim 1, further comprising:   4. The apparatus according to claim 1, further comprising a monitoring unit that is controlled to transition to the power saving mode and that transitions to the power saving mode when a preset additional condition is satisfied. The power saving control device according to any one of the above. A power saving control method executed by a power saving control device that controls a transition to a power saving mode of the main control unit and a return from the power saving mode,
The power saving control device includes a sub-control unit that performs processing at a lower frequency than the main control unit and a storage unit,
Executed in the sub-control unit,
When the calculation unit needs to execute a polling process in which the determination unit repeatedly refers to the data and waits until the data at the specific address reaches the expected value, the data is set to the expected value by executing the polling process. A determination step of determining whether or not they match,
A control step for controlling the arithmetic device to transition to the power saving mode until the control means determines that the data matches the expected value;
A power saving control method comprising: Executed in the sub-control unit,
The measuring means further includes a measuring step of measuring a time during which it is determined whether or not the data matches the expected value;
6. The power saving control method according to claim 5, wherein the control step further performs control so as to transition to the power saving mode when the measured time exceeds a predetermined time. Executed in the sub-control unit,
The detection means is controlled to shift to the power saving mode in the control means of all the power saving mode management sections among the plurality of power saving mode management sections provided with the determination means and the control means. A detection step of transitioning to the power saving mode when
The power saving control method according to claim 5, further comprising: It is executed by the sub-control unit.
The monitoring means is further controlled to transition to the power saving mode, and further includes a monitoring step of transitioning to the power saving mode when a preset additional condition is satisfied. 8. The power saving control method according to any one of 7.

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