JP2015191279A - processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a processing system configured to perform polling with low power consumption.SOLUTION: A polling circuit (202): includes an address signal generating section which converts an address signal of a first address range, which is input from a processing apparatus (201), to a signal of a second address range, and outputs it to a peripheral circuit (PH1), and on the other hand, outputs the same address signal as that input from the processing apparatus, to the peripheral circuit, when the address signal input from the processing apparatus does not have the first address range; and a ready signal generating section which outputs the same ready signal as that of input from the peripheral circuit when the address signal input from the processing apparatus is an address of the first address range and a read data signal input from the peripheral circuit is the same as an expectation value corresponding to the address signal input from the processing apparatus, and on the other hand, outputs an inactive ready signal to the processing apparatus in the other cases.

Description

  The present invention relates to a processing system.

  There is known a polling unit that reads data at a predetermined cycle from a predetermined address in an address space accessible by the processor, and generates an interrupt signal for the processor when the read data satisfies a predetermined condition (for example, patent document) 1). The polling unit has an address assigned in the address space, and has a register for storing data for setting at least one of a predetermined address, a predetermined period, and a predetermined condition.

  In addition, when the processing device needs to execute polling processing by repeatedly referring to the data until the data at the specific address reaches the expected value, whether or not the data matches the expected value by executing the polling processing is determined. A power saving control device having a determination means for determining is known (for example, see Patent Document 2). The control means controls the arithmetic device to transition to the power saving mode until it is determined that the data matches the expected value.

JP 2009-238001 A JP 2011-13914 A

  In interrupt processing, the peripheral circuit notifies the central processing unit (CPU) of an interrupt signal indicating completion of processing. Therefore, after instructing the peripheral circuit to start processing, the CPU can perform completely different processing or can stand by in a sleep mode with low power consumption until an interrupt signal is notified. However, when the CPU is notified of the interrupt signal, the CPU is allowed to resume the processing being executed at that time before the transition to the interrupt processing, the value of the general-purpose register in the CPU, the value of the program counter, the CPU The value of the processor status register holding the internal state of the memory is temporarily saved in a random access memory (RAM). After the saving is completed, the CPU performs processing corresponding to the interrupt signal. When the processing is completed, the general-purpose register value saved in the RAM, the program counter value, and the processor status register value are restored and originally executed. Resume the process that was running.

  Further, when the CPU receives the interrupt signal in the sleep mode, the CPU saves the general-purpose register, program counter, and processor status register value during sleep, processing corresponding to the interrupt signal, general-purpose register from the RAM, program counter, Restores the value of the processor status register. In the interrupt processing, the disadvantage is that saving and restoring these values to the RAM is an overhead.

  In the interrupt process, the peripheral circuit side becomes a transmission source notifying the completion of the process, whereas in the polling process, the CPU inquires the peripheral circuit about the completion of the process. Specifically, the peripheral circuit includes a peripheral circuit status register whose value changes according to its processing state, and the CPU reads the value of the peripheral circuit status register and confirms the value to thereby check the peripheral circuit. It is determined whether or not the process is completed. When the read value of the peripheral circuit status register is a value indicating that processing is still being performed, the CPU repeats reading the value of the peripheral circuit status register and confirming the value again. While the CPU repeatedly reads the value of the peripheral circuit status register many times, the peripheral circuit eventually completes the process, and the value of the peripheral circuit status register changes to a value indicating the completion of the process. I can know.

  The merit of polling processing is that the values of general-purpose registers, program counters, and processor status registers that are stored before the transition to interrupt processing and before returning to normal processing are not saved to and restored from the RAM. And no power consumption overhead. When implementing a program that causes the CPU to perform processing frequently in the peripheral circuit, if this is implemented as a program using interrupt processing, interrupt processing is frequently performed and the overhead of interrupt processing increases. .

  The disadvantage of the polling process is that when the processing in the peripheral circuit is not completed easily and the number of times the CPU repeats reading the value of the peripheral circuit status register increases, the power consumption of the CPU and RAM increases, and in addition to the CPU The processing time in the module that accesses the bus is extended, and the power consumption is increased. When the CPU repeatedly reads the peripheral circuit status register, the CPU repeatedly executes the program shown in the following procedure.

  (1) The CPU reads the value of the peripheral circuit status register. (2) The CPU compares whether the read value matches the value indicating the completion of processing of the peripheral circuit. (3) If they do not match, the CPU returns to (1) and starts again.

  At this time, the CPU continues to operate and consumes power. Further, since the CPU reads from the RAM a program that instructs execution of (1), (2), and (3), the RAM consumes power. The CPU, RAM, and peripheral circuit are connected via a bus, and access to various registers of the peripheral circuit including the status register and access to the RAM are performed via the bus. However, the CPU frequently uses the bus during the polling process. Then, when there are blocks other than the CPU, such as a direct memory access controller (DMAC), the access to these blocks competes or obstructs, and the processing completion of other blocks is delayed. Or extra power is consumed by extending the operation time.

  Patent Document 1 discloses a polling unit that performs a dedicated polling process. Instead of the CPU directly reading the value of the status register of the peripheral circuit and determining whether it matches the expected value, the polling unit does this. An interrupt signal line is connected from the polling unit to the CPU. When the value of the status register matches the expected value, the polling unit notifies the CPU of an interrupt through this interrupt signal line. According to this, even when the peripheral circuit does not directly output a signal notifying the completion of processing as an interrupt signal to the CPU, the CPU can know the completion of the processing in the peripheral circuit by the interrupt processing via the polling unit. Therefore, another process can be performed until the process is completed, which is a merit of the interrupt process, and it is possible to enjoy the merit of being able to wait in a sleep mode with low power consumption. However, each time an interrupt signal is received, the CPU saves the values of the general-purpose register, program counter, and processor status register in the RAM, and restarts the processing that was originally executed when the processing is completed. The demerit that is restored is not resolved.

  Patent Document 2 discloses a power saving mode management unit that performs dedicated polling processing. The CPU previously sets the address of the status register to be polled and the expected value in the address register and data register provided in the power saving mode management unit, and then instructs the power saving mode management unit to execute polling. The power saving mode management unit instructs the clock control unit that supplies a clock to the CPU to stop the clock supply to the CPU, and simultaneously reads the value of the status register of the peripheral circuit designated by the address register. The power saving mode management unit checks whether the read value matches the value instructed by the data register. If there is a mismatch, it reads the value in the status register until it matches, and repeats the value match check to find a match. In this case, the clock control unit is caused to resume the clock supply to the CPU.

  In Patent Document 2, since interrupt processing is not used, there is no demerit that the values of general-purpose registers, program counters, and processor status registers are saved to and restored from RAM. In addition, the power saving mode management unit repeatedly reads the status register of the peripheral circuit, and during that time, the CPU stops the clock supply, so that power consumption in the CPU can be suppressed. Further, since the CPU does not read the program from the RAM and does not perform bus access for status register access, there is no problem of power consumption in the RAM and contention of bus access.

However, Patent Document 2 has the following three problems.
(1) It is necessary to set the address register and data register in the power saving mode management unit and instruct the power saving mode management unit to start polling processing in the program. Therefore, different implementation programs are required depending on whether or not the power saving mode management unit is provided, and the amount of program change increases when the program is ported to a system that does not include the power saving mode management unit.

  (2) The operation when the CPU is notified of an interrupt from a module other than the peripheral circuit that is the polling target by the power saving mode management unit is not disclosed.

  (3) A special CPU capable of suddenly stopping and restarting clock supply is required. A normal CPU has a wait mode in which clock supply can be stopped, but the transition to the wait mode is performed by executing a dedicated instruction for the wait mode transition on the CPU. In order to shift the CPU from the wait mode to the wake up mode again, it is common to restart the supply of the clock to the CPU and notify the CPU of some kind of interrupt. However, when the CPU is set to the wake up mode by the interrupt notification, it is necessary to save and restore the values of the general-purpose register, the program counter, and the processor status register to the RAM.

  An object of the present invention is to provide a processing system that can perform polling processing with low power consumption without requiring a special processing device.

  The processing system inputs a request signal and an address signal from the processing device, a polling circuit that outputs a ready signal and a read data signal to the processing device, and a request signal and an address signal from the polling circuit. And a peripheral circuit that outputs a ready signal and a read data signal to the polling circuit, and the processing device has an activated request signal and an address corresponding to the peripheral circuit for read access to the peripheral circuit. A signal is output, and the peripheral circuit outputs a ready signal in an inactive state when processing corresponding to the request signal of the processing device is not completed, and processing corresponding to the request signal of the processing device is performed. When finished, an active ready signal and a read data signal are output, When the address signal input from the processing device is an address in the first address range, the circuit converts the address signal input from the processing device into an address in the second address range and addresses the peripheral circuit An address signal generation unit that outputs a signal and outputs the same address signal as the address signal input from the processing device to the peripheral circuit when the address signal input from the processing device is not an address in the first address range; When the address signal input from the processing device is an address in the first address range, and the read data signal input from the peripheral circuit is the same as the expected value corresponding to the address signal input from the processing device. The same ready signal input from the peripheral circuit is output to the processing device, and in other cases And a ready signal generator for outputting a ready signal activated state to said processing unit.

  By providing the polling circuit, it is possible to perform polling processing with low power consumption without requiring a special processing device.

FIG. 1 is a diagram illustrating a configuration example of a wireless sensor node according to the present embodiment. FIG. 2 is a diagram illustrating a configuration example of the overall control unit. FIG. 3 is a diagram illustrating a configuration example of a part of the peripheral circuit. FIG. 4 is a diagram illustrating signals among the CPU, polling circuit, bus, and peripheral circuit. FIG. 5 is a timing chart showing signals between the CPU and the polling circuit. FIG. 6 is a timing chart showing signals between the polling circuit and the bus. FIG. 7 is a timing chart showing signals between the bus and peripheral circuits. FIG. 8 is a diagram showing a memory map. FIG. 9 is a diagram illustrating an example of a normal register area, a register area with an expected value of 0, and a register area with an expected value of 1 of the first peripheral circuit. FIG. 10 is a diagram illustrating a configuration example of the polling circuit. FIG. 11 is a diagram illustrating a configuration example of the address signal generation unit of FIG. FIG. 12 is a diagram illustrating a configuration example of the READY signal generation unit in FIG. FIG. 13 is a diagram for explaining the operation of the selector. FIG. 14 is a diagram illustrating a configuration example of the RDATA signal generation unit of FIG. FIG. 15 is a diagram illustrating a configuration example of the REQ signal generation unit in FIG. FIG. 16 is a diagram illustrating a configuration example of the enable signal generation unit in the peripheral circuit.

  FIG. 1 is a diagram illustrating a configuration example of a wireless sensor node 100 according to the present embodiment. The wireless sensor node 100 includes an overall control unit 101, a sensor unit 102, an RF (Radio Frequency) unit 103, a power generation power management unit 104, an antenna 105, and a power generation element 106. The power generation element 106 generates power based on energy 112 such as light, temperature difference, or vibration, and supplies power to the power generation power management unit 104. The power generation power management unit 104 manages power and supplies power to the overall control unit 101, the sensor unit 102, and the RF unit 103. The overall control unit 101 controls the sensor unit 102, the RF unit 103, and the power generation power management unit 104 via a serial interface such as I2C (Inter-Integrated Circuit) and SPI (Serial Peripheral Interface). The sensor unit 102 detects information 111 such as temperature, illuminance, acceleration, or pressure, and outputs the information 111 to the overall control unit 101. The overall control unit 101 transmits information 111 as a radio signal 113 via the RF unit 103 and the antenna 105. Further, the overall control unit 101 can transmit and receive other information as a radio signal 113 via the RF unit 103 and the antenna 105.

  A battery or a commercial power source is not connected to the wireless sensor node 100, and the power generation element 106 generates power based on energy 112 obtained from the environment. Therefore, the wireless sensor node 100 is required to thoroughly reduce power consumption. In order to perform control according to various required specifications and situations required for the wireless sensor node 100, the overall control unit 101 uses MCU (microcontroller unit) because programability is required.

  FIG. 2 is a diagram illustrating a configuration example of the overall control unit 101. The overall control unit 101 is a processing system, which is a central processing unit (CPU) 201, a polling circuit 202, a RAM 203, an interrupt controller 204, a bus 205, a direct memory access controller (DMAC) 206, a first peripheral circuit PH1, a second Peripheral circuit PH2, third peripheral circuit PH3, and fourth peripheral circuit PH4. A polling circuit 202, a RAM 203, a DMAC 206, and peripheral circuits PH1 to PH4 are connected to the bus 205. The bus 205 is connected between the polling circuit 202 and the peripheral circuits PH1 to PH4. The interrupt controller 204 receives the interrupt signals IR1 to IR4 of the peripheral circuits PH1 to PH4 and the external interrupt signal IRR, and outputs the interrupt signal IR to the CPU 201 and the polling circuit 202. The peripheral circuits PH1 to PH4 output enable signals ENS1 to ENS4 to the polling circuit 202, respectively. The peripheral circuits PH1 to PH3 are interface circuits such as an I2C circuit or an SPI circuit, and are connected to the sensor unit 102, the RF unit 103, and the power generation power management unit 104 in FIG.

  FIG. 3 is a diagram illustrating a configuration example of a part of each of the peripheral circuits PH1 to PH4. Each of the peripheral circuits PH1 to PH4 includes an address register 301, a transmission data buffer register 302, a reception data buffer register 303, a control register 304, a status register 305, a logical sum (OR) circuit 306, and a selector 307. The data terminal D and the enable terminal EN of the registers 301 to 305 receive the 32-bit output data of the logic circuits 311 to 320. Each of the registers 301 to 305 latches input data at the data terminal D in synchronization with the clock signal, and outputs the latched 32-bit data from the output terminal Q. The selector 307 selects any of the 32-bit output data of the registers 301 to 305 according to the address ADDR input from the bus 205 and outputs the 32-bit data RDATA to the bus 205. The logical sum circuit 306 outputs a logical sum of 32-bit data at the enable terminal EN of the status register 305 as an enable signal ENS.

  The procedure in which the CPU 201 transmits data to the sensor unit 102, the RF unit 103, and the power generation management unit 104 via the peripheral circuits PH1 to PH3 is as follows. As an example, a procedure in which the CPU 201 transmits data to the sensor unit 102 via the peripheral circuit PH1 will be described. First, the CPU 201 writes the transmission destination address in the address register 301 in the peripheral circuit PH1 via the polling circuit 202 and the bus 205. The transmission destination address is an address indicating the sensor unit 102. Next, the CPU 201 writes the transmission data to the transmission data buffer register 302 in the peripheral circuit PH1 via the polling circuit 202 and the bus 205. Here, the transmission data includes a sensor data read command and the like. Next, the CPU 201 writes a transmission instruction to the control register 304 in the peripheral circuit PH1 via the polling circuit 202 and the bus 205. Thereafter, the peripheral circuit PH1 transmits the transmission data to the sensor unit 102. The sensor unit 102 detects the information 111 according to the transmission data, and transmits the information 111 to the CPU 201 via the peripheral circuit 104, the bus 205, and the polling circuit 202.

  FIG. 4 is a diagram illustrating signals among the CPU 201, the polling circuit 202, the bus 205, and the peripheral circuit PH1. Although the case of the peripheral circuit PH1 is shown as an example, the peripheral circuits PH2 to PH4 are similar to the case of the peripheral circuit PH1. The request signal REQ is an access request signal. The address signal ADDR is an access destination address signal. The access type signal WRITE is a signal indicating the type of read or write access. The write data signal WDATA is a write data signal at the time of write access. The read data signal RDATA is a read data signal at the time of read access. The ready signal READY is a signal indicating completion of access.

  For example, when the CPU 201 is a 32-bit CPU, the signals ADDR, WDATA, and RDATA are 32-bit signals. Signals REQ, ADDR, WRITE, and WDATA are signals output from the access source to the access destination. The signals RDATA and READY are signals output from the access destination to the access source. In FIG. 4, the final access destination is the peripheral circuit PH1, but since the CPU 201 reads the program code and reads / writes the data, the RAM 203 in FIG. 1 can also be the final access destination. In FIG. 4, the CPU 201 is the access source, but the DMAC 206 of FIG. 2 can be the access source because it performs read and write access to the RAM 203 and the peripheral circuits PH1 to PH4. However, since the DMAC 206 does not perform polling processing, it is not necessary to go through the polling circuit 202 and is directly connected to the bus 205.

  The polling circuit 202 receives a request signal REQ, an address signal ADDR, an access type signal WRITE, and a write data signal WDATA from the CPU 201, and outputs a ready signal READY and a read data signal RDATA to the CPU 201. The peripheral circuit PH1 inputs the request signal REQ, the address signal ADDR, the access type signal WRITE, and the write data WDATA from the polling circuit 202 via the bus 205, and outputs the ready signal READY and the read data signal RDATA to the polling circuit 202. .

  Next, normal polling processing of the CPU 201 will be described. When the processing instructed by the CPU 201 is completed, the peripheral circuit PH1 to be polled changes the value of the least significant bit of the 32-bit status register 305 from 0 to 1. The CPU 201 reads the value of the 32-bit status register 305 and extracts the value of the least significant bit. When the least significant bit is 1, since the processing of the peripheral circuit PH1 is completed, the CPU 201 proceeds to the next processing. When the least significant bit is 0, since the peripheral circuit PH1 has not yet completed the process, the CPU 201 does not proceed to the next process and repeats the process of confirming whether the process of the peripheral circuit PH1 is completed again. . If the processing of the peripheral circuit PH1 takes time and the least significant bit of the status register 305 does not readily change to 1, the CPU 201 repeats the process of reading and confirming the least significant bit of the status register 305 many times. . In the present embodiment, processing for eliminating such repeated processing will be described. In the present embodiment, it is guaranteed that the value obtained by reading the least significant bit of the status register 305 is always 1, and the next processing can be surely proceeded by the first execution. Details will be described below.

  5 is a timing chart showing signals between the CPU 201 and the polling circuit 202, FIG. 6 is a timing chart showing signals between the polling circuit 202 and the bus 205, and FIG. 7 shows signals between the bus 205 and the peripheral circuit PH1. It is a timing chart which shows. The signal CLK is a clock signal. The signal LSB is a signal of the least significant bit of data in the status register 305 in the peripheral circuit PH1.

  An example in which the CPU 201 performs read access to the least significant bit of the status register 305 in the peripheral circuit PH1 will be described. All signals are transmitted at the rising edge of the clock signal CLK supplied in common to the CPU 201, polling circuit 202, bus 205 and peripheral circuit PH1. The CPU 201 confirms that the signal READY = 1 indicating that the access request may be made to the polling circuit 202 at time T1 in FIG. 5, and outputs an access request with the signal REQ = 1. At the same time, the CPU 201 notifies the polling circuit 202 of an access destination address signal ADDR = A ′ (an address indicating the least significant bit LSB of the status register 305) and a signal WRITE = indicating that the access type is read access. 0 is output.

  The polling circuit 202 converts the signal ADDR = A ′ input from the CPU 201 into the signal ADDR = A in FIG. 6 and outputs it to the bus 205 by the internal address signal generation unit 1001 (FIG. 10). The polling circuit 202 outputs the signal REQ and the signal WRITE input from the CPU 201 to the bus 205 as they are.

  The bus 205 knows that a read access request is received from the CPU 201 based on the signals REQ and WRITE from the polling circuit 202. Then, the bus 205 determines the access destination from the signal ADDR, and outputs the signals REQ, ADDR, and WRITE from the polling circuit 202 to the peripheral circuit PH1 that is the access destination. The peripheral circuit PH1 outputs to the bus 205 a signal READY = 0 indicating that the read data of the least significant bit LSB of the status register 305 is being prepared. The signal READY is output from the peripheral circuit PH1 to the CPU 201 via the bus 205 and the polling circuit 202. Since the signal READY = 0, the CPU 201 knows that the read access is still being executed.

  After time T3, the peripheral circuit PH1 is ready to output the value Data (A) of the status register 305 designated by the address signal ADDR = A, and outputs the signal RDATA = Data (A). At the same time, the signal RDATA A signal READY = 1 indicating that is valid data is output. At this time, since the peripheral circuit PH1 has not completed the sensor data reading process instructed by the CPU 201, the value of the least significant bit LSB of the status register 305 is 0. Therefore, the least significant bit LSB of the signal RDATA is 0. The signals READY and RDATA are output from the peripheral circuit PH1 to the polling circuit 202 via the bus 205.

  At time T4, the polling circuit 202 knows that the signal RDATA = Data (A) is input at the same time because the signal READY = 1 at the rising edge of the clock signal CLK. The polling circuit 202 extracts the value of the least significant bit LSB that the CPU 201 wants to confirm as a polling target from the 32-bit signal RDATA, and confirms whether this value is 1 expected by the CPU 201. Since the least significant bit LSB is 0, the polling circuit 202 continuously outputs the signal READY = 0 to the CPU 201.

  At time T6 after the predetermined time, the polling circuit 202 again outputs the signal ADDR = A, the signal REQ = 1, and the signal WRITE = 0 to the peripheral circuit PH1 via the bus 205. At time T5 before time T6, the peripheral circuit PH1 completes the sensor data reading process instructed by the CPU 201, and changes the least significant bit LSB of the status register 305 from 0 to 1.

  After time T7, the peripheral circuit PH1 outputs a signal READY = 0 indicating that the read data of the least significant bit LSB of the status register 305 is being prepared to the CPU 201 via the bus 205 and the polling circuit 202. . Since the signal READY = 0, the CPU 201 knows that the read access is still being executed.

  After time T8, the peripheral circuit PH1 is ready to output the value Data (A) of the status register 305 designated by the address signal ADDR = A, and outputs the signal RDATA = Data (A). At the same time, the signal RDATA A signal READY = 1 indicating that is valid data is output. At this time, since the peripheral circuit PH1 has completed reading processing of the sensor data instructed from the CPU 201, the value of the least significant bit LSB of the status register 305 is 1. Therefore, the least significant bit LSB of the signal RDATA is 1. The signals READY and RDATA are output from the peripheral circuit PH1 to the polling circuit 202 via the bus 205.

  After the time T8, the polling circuit 202 knows that the signal RDATA = Data (A) is input at the same time because the signal READY = 1. The polling circuit 202 extracts the value of the least significant bit LSB that the CPU 201 wants to confirm as a polling target from the 32-bit signal RDATA, and confirms whether this value is 1 expected by the CPU 201. Since the least significant bit LSB is 1, the polling circuit 202 outputs a signal READY = 1 and a 32-bit signal RDATA = 1 to the CPU 201. Since the signal READY = 1, the CPU 201 knows that the read access has been completed. At this time, the signal RDATA input by the CPU 201 is guaranteed to be 1. The CPU 201 guarantees that the value obtained by reading the least significant bit LSB of the status register 305 is always 1, and can always proceed to the next processing in the first execution.

  As described above, the CPU 201 outputs the request signal REQ of “1” and the address signal ADDR corresponding to the peripheral circuit PH1 in order to perform read access to the peripheral circuit PH1. The peripheral circuit PH1 outputs a ready signal READY of “0” when the processing corresponding to the request signal REQ of the CPU 201 is not finished, and “1” when the processing corresponding to the request signal REQ of the CPU 201 is finished. The ready signal REDY and the read data signal RDATA are output. In the signals REQ and READY, “1” indicates an activated state and “0” indicates an inactivated state.

  The polling circuit 202 repeats output of the signal REQ = 1 and the like to the peripheral circuit PH1 until the least significant bit LSB of the signal RDATA becomes 1. The polling circuit 202 outputs the signal REQ = 1 and the like twice to the peripheral circuit PH1, but the CPU 201 outputs the access request of the signal REQ = 1 and then the actually requested signal RDATA = Data. The expected value of 1 is received in one read access until the arrival of (A ′). Therefore, since it is not necessary for the CPU 201 to repeatedly read and confirm the signal REQ = 1, the power consumption can be suppressed, and the power consumption of the RAM 203 caused by repeatedly reading the program from the RAM 203 can be suppressed.

  FIG. 8 is a diagram showing a memory map. Hereinafter, based on the address signal ADDR input from the CPU 201, the polling circuit 202 determines what bit value of the 32-bit signal RDATA is to be checked in the polling process, and the expected values are 0 and 1. A method for discriminating between the two will be described. Each of the registers 301 to 305 is assumed to be byte addressed with 32 bits (1 byte = address is assigned in units of 8 bits).

  The various registers 301 to 305 of the first peripheral circuit PH1 are mapped from addresses 0x40000000 to 0x40000FFC. Here, 0x indicates a hexadecimal number. For example, the address of the status register 305 is mapped to 0x40000000, the control register 304 is mapped to 0x40000004, the reception data buffer register 303 is mapped to 0x40000008, and so on. Normally, when the CPU 201 reads the values of the registers 301 to 305 or writes the values to the registers 301 to 305, access is made using these addresses.

  Addresses 0x50000000 to 0x5001FFFC are addresses when the CPU 201 reads and accesses a register in the hope that a certain bit of the register of the first peripheral circuit PH1 is 0. Addresses 0x60000000 to 0x6001FFFC are addresses used when the CPU 201 reads and accesses a register in the hope that a certain bit of the register of the first peripheral circuit PH1 is 1.

  The register area 801a is a normal register area of the first peripheral circuit PH1. The register area 801b is a register area where the expected value of the first peripheral circuit PH1 is zero. The register region 801c is a register region in which the expected value of the first peripheral circuit PH1 is 1. The register area 802a is a normal register area of the second peripheral circuit PH2. The register area 802b is a register area where the expected value of the second peripheral circuit PH2 is zero. The register area 802c is a register area in which the expected value of the second peripheral circuit PH2 is 1. The register area 804a is a normal register area of the fourth peripheral circuit PH4. The register area 804b is a register area where the expected value of the fourth peripheral circuit PH4 is zero. The register area 804c is a register area in which the expected value of the fourth peripheral circuit PH4 is 1.

  FIG. 9 is a diagram illustrating an example of the normal register area 801a, the register area 801b having an expected value of 0, and the register area 801c having an expected value of 1 of the first peripheral circuit PH1. For example, when reading and accessing the 0th bit (least significant bit) A of the register whose address of the normal register area 801a is specified by 0x40000000 with the expectation that the value is 0, the CPU 201 sets the signal ADDR = 0x50000000. Output to the polling circuit 202. Also, when reading and accessing the 0th bit (least significant bit) A of the register whose address of the normal register area 801a is designated by 0x40000000 in the expectation that the value is 1, the CPU 201 sets the signal ADDR = 0x60000000. Output to the polling circuit 202.

  The CPU 201 outputs the signal ADDR = 0x50000004 to the polling circuit 202 when reading and accessing the first bit B of the register designated by the address 0x40000000 in the normal register area 801a with the expectation that the value is 0. Further, when reading and accessing the first bit B of the register designated by the address 0x40000000 in the normal register area 801a in the expectation that the value is 1, the CPU 201 outputs the signal ADDR = 0x60000004 to the polling circuit 202. To do.

  When the CPU 201 reads and accesses the 31st bit (the most significant bit) C of the register designated by the address 0x40000FFC in the normal register area 801a with the expectation that the value is 0, the CPU 201 polls the signal ADDR = 0x5001FFFC. To 202. In addition, when reading and accessing the 31st bit (most significant bit) C of the register whose address of the normal register area 801a is specified by 0x40000FFC with the expectation that the value is 1, the CPU 201 outputs the signal ADDR = 0x6001FFFC. Output to the polling circuit 202.

  When the address of the normal register area 801a of the registers 301 to 305 to be accessed by the polling process is Addr_n and the bit position is BIT, the address signal ADDR output by the CPU 201 when reading access is performed with the expectation that this bit is 0. Is expressed by the following equation.

  ADDR = 0x50000000 + (Addr_n-0x40000000) × 32 × 4 + BIT × 4

  Similarly, assuming that the address of the normal register area 801a of the registers 301 to 305 to be accessed by polling processing is Addr_n and the bit position is BIT, the CPU 201 outputs when reading access with the expectation that this bit is 1. The address signal ADDR is expressed by the following equation.

  ADDR = 0x60000000 + (Addr_n-0x40000000) × 32 × 4 + BIT × 4

  FIG. 10 is a diagram illustrating a configuration example of the polling circuit 202. The polling circuit 202 includes an address signal generation unit 1001, a ready (READY) signal generation unit 1002, a read data (RDATA) signal generation unit 1003, and a request (REQ) signal generation unit 1004.

  FIG. 11 is a diagram illustrating a configuration example of the address signal generation unit 1001 of FIG. The address signal generation unit 1001 includes an address comparison unit 1101, an address conversion unit 1102, an address holding unit 1103, and a selector 1104. The address signal generation unit 1001 converts the signal ADDR from the CPU 201 and outputs the converted signal ADDR to the bus 205. If the upper 4 bits of the 32-bit signal ADDR input from the CPU 201 are 0x5, the address comparison unit 1101 determines that the register area 801b of the expected value 0 is accessed, and if the upper 4 bits are 0x6, It is determined that the access is to the register area 801c with the expected value 1. Further, when the upper 4 bits are other values, the address comparison unit 1101 determines that the access is other than the polling process, such as access to the normal register area 801a and access to the RAM 203.

  When the upper 4 bits of the signal ADDR are 0x5 or 0x6, the address comparison unit 1101 outputs a polling access signal of “1” to notify that an access request for polling has been received from the CPU 201, and otherwise , "0" polling access signal is output. Further, the address comparison unit 1101 outputs 0 as the expected value signal when the upper 4 bits of the signal ADDR are 0x5, and outputs 1 when the upper 4 bits of the signal ADDR is 0x6. Further, the address comparison unit 1101 calculates a bit position to be polled based on a value obtained by dividing the lower 7 bits of the signal ADDR by 4, and outputs a bit position signal.

  When the polling access signal is 0, the address conversion unit 1102 outputs the signal ADDR from the CPU 201 to the address holding unit 1103 and the selector 1104 as it is. Also, when the polling access signal is 1, the address conversion unit 1102 calculates the address Addr_n according to the following procedure, and outputs the calculated address Addr_n to the address holding unit 1103 and the selector 1104.

  (1) The address conversion unit 1102 subtracts 0x50000000 from the signal ADDR input from the CPU 201 when the expected value is 0, and subtracts 0x60000000 from the signal ADDR input from the CPU 201 when the expected value is 1.

  (2) The address conversion unit 1102 shifts the value obtained in (1) to the right by 7 bits.

  (3) The address conversion unit 1102 adds 0x40000000 to the value obtained in (2).

  According to the above procedure, the address Addr_n of the normal register area 801a of the register including the bit that the CPU 201 wants to confirm by the polling process can be restored. The address conversion unit 1102 outputs the address Addr_n to the address holding unit 1103 and the selector 1104.

  The address holding unit 1103 holds the address Addr_n generated by the address conversion unit 1102 when the polling access signal is 1. As a result, when the value of the status register 305 read from the peripheral circuit PH1 is not an expected value, the polling circuit 202 can repeatedly perform read access to the status register 305.

  When the polling access signal is 0, the selector 1104 outputs the signal ADDR output from the address conversion unit 1102 to the bus 205 as it is. At this time, the address conversion unit 1102 does not perform address conversion, and outputs the signal ADDR from the CPU 201 as it is. When the polling access signal is 1, the selector 1104 outputs the address Addr_n output from the address holding unit 1103 to the bus 205.

  As described above, when the address signal ADDR input from the CPU 201 is the address of the register areas (first address range) 801b and 801c having the expected value 0 and the expected value 1, the address signal generating unit 1001 The input address signal ADDR is converted into an address in the normal register area (second address range) 801a, and the address signal ADDR is output to the peripheral circuit PH1 via the bus 205. Also, the address signal generation unit 1001 receives the address signal input from the CPU 201 when the address signal ADDR input from the CPU 201 is not the address of the register areas (first address range) 801b and 801c with the expected value 0 and the expected value 1. The same address signal ADDR as ADDR is output to the peripheral circuit PH1 via the bus 205. The address holding unit 1103 holds an address obtained by converting the address signal ADDR input from the CPU 201 into the address of the normal register area (second address range) 801a.

  FIG. 12 is a diagram illustrating a configuration example of the READY signal generation unit 1002 of FIG. The READY signal generation unit 1002 includes selectors R1 and R2, a bit position holding unit 1201, an expected value holding unit 1202, an expected value comparison unit 1203, and a polling interruption determination unit 1204. The READY signal generation unit 1002 generates a signal READY that is output to the CPU 201.

  The bit position holding unit 1201 holds the bit position signal output from the address comparison unit 1101 in FIG. 11 during the polling process, and outputs the bit position signal to the selector R1. The selector R1 selects the value of the bit position indicated by the bit position signal output from the bit position holding unit 1201 from the 32-bit signal RDATA input from the bus 205, and outputs it as a bit signal.

  The expected value holding unit 1202 holds the expected value signal output from the address comparing unit 1101 in FIG. 11 during the polling process, and outputs it to the expected value comparing unit 1203. The expected value comparison unit 1203 compares the bit signal input from the selector R1 with the expected value signal input from the expected value holding unit 1202, and outputs an expected value determination signal of “1” if they match. When the two do not match, an expected value determination signal of “0” is output. The polling interruption determination unit 1204 receives an interrupt signal IR input to the CPU 201, and outputs an “1” polling interruption signal to the selector R2 when an interrupt occurs to the CPU 201.

  The selector R2 receives the polling access signal output from the address comparison unit 1101 in FIG. 11, the expected value determination signal output from the expected value comparison unit 1203, and the polling interruption signal output from the polling interruption determination unit 1204 from the bus 205. A signal READY or 0 is output to the CPU 201. The signal output from the selector R2 is the signal READY output from the polling circuit 202 to the CPU 201.

  FIG. 13 is a diagram for explaining the operation of the selector R2. The selector R2 outputs a signal in response to the polling access signal, the expected value determination signal, and the polling interruption signal. When the polling interruption signal is 1, the selector R2 selects and outputs the signal READY from the bus 205 regardless of the values of the polling access signal and the expected value determination signal. The reason will be described later. Further, when the polling interruption signal is 0, the selector R2 performs the following operation.

  When the polling access signal is 0, the CPU 201 performs normal access that is not access for polling, so the selector R2 outputs the signal READY from the bus 205 to the CPU 201 as it is.

  When the polling access signal is 1 and the expected value determination signal is 1, the value expected by the CPU 201 is obtained, so the selector R2 outputs the signal READY from the bus 205 to the CPU 201 as it is. At this time, since the process in which the polling circuit 202 reads the value of the status register 305 of the peripheral circuit PH1 through the bus 205 has been completed, the signal READY from the bus 205 is 1.

  When the polling access signal is 1 and the expected value determination signal is 0, the value expected by the CPU 201 is not obtained, and it appears to the CPU 201 that read access is continuing. "READY" is output to the CPU 201.

  Next, the condition that the polling interruption signal becomes 1 and the operation of the polling circuit 202 at that time will be described. When the CPU 201 is performing the polling process, if the value of the status register 305 to be polled does not change to the value expected by the CPU for a long time, the signal READY output from the polling circuit 202 to the CPU 201 is 0 for a long time. Will remain. When viewed from the CPU 201, it appears that the read access has been suspended for a long time. When the CPU 201 receives an interrupt signal IR of “1” during the bus access, the polling circuit 202 confirms the expected value match if the CPU 201 is designed to wait for the completion of the bus access before proceeding to the interrupt processing. Until then, it appears to the CPU 201 that the signal READY is 0 and the bus access is not completed. Therefore, the CPU 201 waits for a long time before shifting to the interrupt process. Therefore, when the interrupt signal IR of “1” is input to the CPU 201, the CPU 201 immediately interrupts the program currently being executed and shifts to the interrupt processing program.

  In the present embodiment, in order to prevent a situation in which a long waiting time is caused before the transition to the interrupt processing, the polling interruption determination unit 1204 receives the interrupt signal IR input to the CPU 201 and an interrupt is generated to the CPU 201. If so, a polling interruption signal of “1” is output to interrupt the polling process. The selector R2 outputs the signal READY from the bus 205 to the CPU 201 as it is in order to complete the bus access viewed from the CPU 201.

  At this time, since the signal RDATA output to the CPU 201 is the value of the designated bit of the status register 305 most recently read by the polling circuit 202, the bit signal holding unit 1401 (holding the bit signal output by the selector R1) FIG. 14) is provided.

  As described above, the READY signal generation unit 1002 is the address of the register areas (first address range) 801b and 801c in which the address signal ADDR input from the CPU 201 has the expected value 0 and the expected value 1, and is transmitted via the bus 205. When the read data signal RDATA input from the peripheral circuit PH1 is the same as the expected value corresponding to the address signal ADDR input from the CPU 201, the ready signal READY is the same as the ready signal READY input from the peripheral circuit PH1 via the bus 205. Is output to the CPU 201, and in other cases, a ready signal READY of “0” is output to the CPU 201.

  Specifically, the READY signal generation unit 1002 is the address of the register area (third address range) 801b in which the address signal ADDR input from the CPU 201 is an expected value 0, and the read data signal RDATA input from the peripheral circuit PH1. When the value of the bit corresponding to the address signal ADDR input from the CPU 201 is 0, the ready signal READY that is the same as the ready signal READY input from the peripheral circuit PH1 is output to the CPU 201. Further, the READY signal generation unit 1002 is an address of the register area (fourth address range) 801c in which the address signal ADDR input from the CPU 201 is an expected value 1, and the CPU 201 of the read data signal RDATA input from the peripheral circuit PH1. When the value of the bit corresponding to the address signal ADDR input from 1 is 1, the ready signal READY that is the same as the ready signal READY input from the peripheral circuit PH1 is output to the CPU 201.

  Further, when the interrupt signal IR input to the CPU 201 becomes “1” (activated state), the READY signal generation unit 1002 has the same ready signal as the ready signal READY input from the peripheral circuit PH1 via the bus 205. The signal READY is output to the CPU 201.

  FIG. 14 is a diagram illustrating a configuration example of the RDATA signal generation unit 1003 of FIG. The RDATA signal generation unit 1003 generates a signal RDATA output from the polling circuit 202 to the CPU 201. The RDATA signal generation unit 1003 includes a bit signal holding unit 1401 and a selector 1402. The bit signal holding unit 1401 inputs the bit signal from the READY signal generation unit 1002 in FIG. 12 as the least significant bit, fills the upper 31 bits with 0, as in the register areas 801b and 801c in FIG. A signal is generated and output to the selector 1402. When the polling access signal is “1”, the selector 1402 outputs the 32-bit signal output from the bit signal holding unit 1401 to the CPU 201 as the signal RDATA. When the polling access signal is 0, the CPU 201 is performing bus access not for polling processing, so the selector 1402 outputs the signal RDATA from the bus 205 to the CPU 201 as it is.

  As described above, when the address signal ADDR input from the CPU 201 is the address of the register areas (first address range) 801b and 801c with the expected value 0 and the expected value 1, the RDATA signal generation unit 1003 uses the bus 205 Of the read data signal RDATA input from the peripheral circuit PH1 via the CPU, a bit signal corresponding to the address signal ADDR input from the CPU 201 is output to the CPU 201 as the read data signal RDATA. The bit signal holding unit 1401 holds a bit signal corresponding to the address signal ADDR input from the CPU 201 in the read data signal RDATA input from the peripheral circuit PH1 via the bus 205.

  Specifically, the RDATA signal generation unit 1003 uses a bit signal corresponding to the address signal ADDR input from the CPU 201 in the read data signal RDATA input from the peripheral circuit PH1 via the bus 205 as the lower bit, Is output to the CPU 201 as a read data signal RDATA.

  FIG. 15 is a diagram illustrating a configuration example of the REQ signal generation unit 1004 of FIG. The REQ signal generation unit 1004 generates a signal REQ that is output from the polling circuit 202 to the bus 205. The REQ signal generation unit 1004 includes selectors 1501 and 1502. When the polling access signal is 0, the CPU 201 is performing a normal access that is not an access for the polling process. Therefore, the selector 1501 outputs the signal REQ from the CPU 201 as it is to the bus 205 as a signal REQ. When the polling access signal is 1, the selector 1501 generates a signal REQ to the bus 205 by the following operation.

  When the polling access signal is 1, the selector 1501 outputs a signal REQ of “1” to the bus 205 for the first access of the status register 305 of the peripheral circuit PH1.

  The read value of the status register 305 of the peripheral circuit PH1 does not match the expected value, and the output of the signal REQ for performing read access to the status register 305 for the second and subsequent times is performed when the selector 1502 outputs the access timing signal. Do. The selector 1502 selects any one of the enable signals ENS1 to ENS4 output from the peripheral circuits PH1 to PH4 based on the normal register address output from the address holding unit 1103 in FIG. 11, and supplies the selector 1501 as an access timing signal. Output. For example, when the addresses of the normal register areas of the peripheral circuits PH1 to PH4 have the configuration shown in FIG. 8, when the normal register address is in the range of 0x40000000 to 0x40000FFC, the selector 1502 selects the enable signal ENS1 of the peripheral circuit PH1, and the access timing Output as a signal.

  FIG. 16 is a diagram illustrating a configuration example of the enable signal generation unit in each of the peripheral circuits PH1 to PH4. The 32 D-type flip-flops FF1 to FF32 correspond to the status register 305 in FIG. 3 and store 32-bit values. The OR circuit 306 corresponds to the OR circuit 306 in FIG. The enable signal generation unit generates an enable signal ENS. The enable signal ENS output from the enable signal generator in the first peripheral circuit PH1 corresponds to the enable signal ENS1 output from the first peripheral circuit PH1 in FIG. The enable signal ENS output from the enable signal generation unit in the second peripheral circuit PH2 corresponds to the enable signal ENS2 output from the second peripheral circuit PH2 in FIG. The enable signal ENS output from the enable signal generator in the third peripheral circuit PH3 corresponds to the enable signal ENS3 output from the third peripheral circuit PH3 in FIG. The enable signal ENS output from the enable signal generation unit in the fourth peripheral circuit PH4 corresponds to the enable signal ENS4 output from the fourth peripheral circuit PH4 in FIG.

  The status register 305 has D-type flip-flops FF1 to FF32 with an enable terminal EN. Each of the D-type flip-flops FF1 to FF32 with the enable terminal EN is a 1-bit storage element. When the signal of the enable terminal EN is 1, the value of the input terminal D is taken in and held therein, and the held value is stored. Output from the output terminal Q. Therefore, when the signal input to the enable terminal EN of each D-type flip-flop FF1 to FF32 is 1, the value of each D-type flip-flop FF1 to FF32 may be rewritten. Even if 1 is input to the enable terminal EN, if the value input to the input terminal D is the same as the value originally held by each D-type flip-flop FF1 to FF32, as a result, each D-type flip-flop The values of FF1 to FF32 are not rewritten and the same value is continuously output from the output terminal Q. The logical sum circuit 306 outputs a logical sum of signals from the enable terminals EN of the D flip-flops (status registers) FF1 to FF32 as an enable signal ENS. The enable signal ENS corresponds to the enable signals ENS1 to ENS4 in FIG.

  In FIG. 15, the selector 1502 selects one of the enable signals ENS1 to ENS4 according to the normal register address, and outputs it to the selector 1501 as an access timing signal. When the polling access signal is 1 and the access timing signal is 1, the selector 1501 determines that there is a possibility that the value of the status register 305 of the peripheral circuits PH1 to PH4 to be polled has changed. A “1” signal REQ for access is output to the bus 205. Further, when the polling access signal is 1 and the access timing signal is 0, the selector 1501 determines that there is no possibility that the value of the status register 305 of the peripheral circuits PH1 to PH4 to be polled has changed, and “0”. The signal REQ is output to the bus 205. When there is no possibility that the value of the status register 305 has changed, the signal REQ of “0” is output to the bus 205, so that it is possible to prevent the status register 305 from being read-accessed uselessly. As a result, wasteful power consumption of the polling circuit 202 and the bus 205 can be suppressed, and a bus access conflict with a module using the bus 205 in addition to the DMAC 206 can be prevented.

  As described above, each of the peripheral circuits PH1 to PH4 reads the read data from the status register 305 having the enable terminal EN according to the request signal REQ of the CPU 201. For example, when the signal of the enable terminal EN of the status register 305 of the peripheral circuit PH1 becomes 1, the REQ signal generation unit 1004 outputs a request signal REQ of “1” to the peripheral circuit PH1. In the signal of the enable terminal EN, “1” indicates an activated state and “0” indicates an inactivated state.

  Specifically, the status register 305 includes a plurality of flip-flops FF1 to FF32 having an enable terminal EN. The REQ signal generation unit 1004 outputs a request signal REQ of “1” to the peripheral circuit PH1 when one of the signals of the enable terminals EN of the plurality of flip-flops FF1 to FF32 becomes 1.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

DESCRIPTION OF SYMBOLS 100 Wireless sensor node 101 Overall control part 102 Sensor part 103 RF part 104 Power generation power supply management part 105 Antenna 106 Power generation element 201 Central processing unit (CPU)
202 Polling circuit 203 RAM
204 Interrupt controller 205 Bus 206 Direct memory access controller (DMAC)
PH1 First peripheral circuit PH2 Second peripheral circuit PH3 Third peripheral circuit PH4 Fourth peripheral circuit

Claims (10)

A processing device;
A polling circuit for inputting a request signal and an address signal from the processing device, and outputting a ready signal and a read data signal to the processing device;
A peripheral circuit that inputs a request signal and an address signal from the polling circuit and outputs a ready signal and a read data signal to the polling circuit,
The processing device outputs an activated request signal and an address signal corresponding to the peripheral circuit for read access to the peripheral circuit,
The peripheral circuit outputs a deactivated ready signal when the processing corresponding to the request signal of the processing device is not completed, and when the processing corresponding to the request signal of the processing device is completed. Outputs an active ready signal and read data signal,
The polling circuit includes:
When the address signal input from the processing device is an address in the first address range, the address signal input from the processing device is converted to an address in the second address range and the address signal is output to the peripheral circuit When the address signal input from the processing device is not an address in the first address range, an address signal generation unit that outputs the same address signal as the address signal input from the processing device to the peripheral circuit;
When the address signal input from the processing device is an address in a first address range, and the read data signal input from the peripheral circuit is the same as the expected value corresponding to the address signal input from the processing device, A ready signal generating unit that outputs a ready signal that is the same as the ready signal input from the peripheral circuit to the processing device; in other cases, a ready signal generation unit that outputs a ready signal in an inactive state to the processing device Processing system. The peripheral circuit reads read data from a register having an enable terminal in response to a request signal of the processing device,
The polling circuit includes a request signal generation unit that outputs an activated request signal to the peripheral circuit when a signal of an enable terminal of a register of the peripheral circuit is activated. Item 2. The processing system according to Item 1. The peripheral circuit register includes a plurality of flip-flops having an enable terminal,
The request signal generation unit outputs an activated request signal to the peripheral circuit when any one of the signals of the enable terminals of the plurality of flip-flops of the peripheral circuit is activated. The processing system according to claim 2, further comprising:   The polling circuit corresponds to an address signal input from the processing device among read data signals input from the peripheral circuit when the address signal input from the processing device is an address in a first address range. The processing system according to claim 1, further comprising: a read data signal generation unit that outputs a bit signal as a read data signal to the processing device.   The read data signal generation unit sets a signal of a bit corresponding to an address signal input from the processing device of read data signals input from the peripheral circuit as a lower bit and a signal in which upper bits are padded with 0 as read data 5. The processing system according to claim 4, wherein the processing system outputs the signal to the processing device. The first address range has a third address range with an expected value of 0 and a fourth address range with an expected value of 1.
The ready signal generator is
The address signal input from the processing device is an address in the third address range, and the value of the bit corresponding to the address signal input from the processing device in the read data signal input from the peripheral circuit is 0. In this case, the same ready signal input from the peripheral circuit is output to the processing device,
The address signal input from the processing device is an address in the fourth address range, and the value of the bit corresponding to the address signal input from the processing device in the read data signal input from the peripheral circuit is 1. 6. The processing system according to claim 1, wherein a ready signal that is the same as a ready signal input from the peripheral circuit is output to the processing device.   The address signal generation unit includes an address holding unit that holds an address obtained by converting an address signal input from the processing device into an address in the second address range. The processing system according to item.   The ready signal generation unit outputs the same ready signal as the ready signal input from the peripheral circuit to the processing device when an interrupt signal input to the processing device is activated. The processing system according to any one of claims 1 to 7.   The read data signal generation unit includes a bit signal holding unit that holds a signal of a bit corresponding to an address signal input from the processing device among read data signals input from the peripheral circuit. The processing system according to 4 or 5.   The processing system according to claim 1, further comprising a bus connected between the polling circuit and the peripheral circuit.

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