JP2010251560A - Wiring board and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board capable of inexpensive production without need of a complicated manufacturing process by forming a shield structure on the wiring board where an electronic component is mounted. <P>SOLUTION: The wiring board 10 includes a core substrate 11 and build-up layers 16 and 17, and has a structure where an electronic component can be mounted on an upper surface. The wiring board 10 includes an electrode pad group 40a provided oppositely to a terminal group of the electronic component, and an electrode pad group 40b provided around it. A plated layer 41 containing at least palladium is formed on the surface of the electrode pad groups 40a and 40b. In addition, a metallic member having a second plated layer joined with an upper part of the electrode pad group 40b and not containing palladium formed on a surface is provided. A cap member made of a conductive material can be joined with an upper part of the metallic member via a conductive adhesive. Therefore, while one kind of plated layer 41 is formed on the electrode pad groups 40a and 40b, the metallic member and the cap member can form a good shield structure. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a wiring board on which electronic components are mounted, and more particularly to a wiring board including an electrode pad group having a plating layer formed on the surface and a manufacturing method thereof.

  Conventionally, wiring boards on which electronic components such as semiconductor chips can be mounted have been widely used. In general, a structure of a wiring board in which build-up layers in which conductor layers and insulating layers are alternately laminated are arranged above and below a core substrate, an electrode pad group is provided on one surface, and a mounted electronic component is connected to the electrode pad group It has been known. Each pad of the electronic component is bonded to, for example, a solder bump formed on each electrode pad of the wiring board. In general, copper is used as the material of the electrode pad, and a structure in which a nickel, palladium, or gold plating layer having good bondability with solder is formed on the surface thereof is employed. The electrode pad having such a structure is used not only for bonding with an electronic component but also for bonding with a chip component such as a chip capacitor.

  On the other hand, when the wiring board is incorporated into various electronic devices, it is required to suppress the generation of electromagnetic noise (EMI). As a countermeasure against EMI in a wiring board, it is effective to form a shield structure that shields noise (see, for example, Patent Documents 1 to 3). As an example of such a shield structure, a cap member made of a metal material is bonded to the surface of the build-up layer using a conductive adhesive, and is connected to the underlying ground wiring via a part of the electrode pad group. Can be realized. In general, since the cap member is large in size, it is important to ensure sufficient adhesive strength with the conductive adhesive.

JP 2004-71629 A Japanese Patent Laid-Open No. 2004-259992 JP 2006-245126 A

  When forming the above-described shield structure, for example, a structure in which a cap member is bonded to a plating layer similar to an electrode pad group for an electronic component using a conductive adhesive is also conceivable. However, it is known that a general epoxy-based conductive adhesive cannot obtain good adhesion with plating containing palladium. In such a structure using a plating layer, the adhesion of the cap member is not achieved. The strength may be insufficient. On the other hand, if the plating layer is changed only for the electrode pad to be joined to the cap member and, for example, a plating layer of nickel or gold is formed on the surface, it is possible to ensure the adhesive strength. However, when such a structure is adopted, it is necessary to form two types of plating layers according to the presence or absence of palladium in the same layer of the wiring board. Accordingly, a complicated formation process using two plating masks is required, and there is a problem that the manufacturing process of the wiring board becomes complicated and the manufacturing cost increases.

  The present invention has been made to solve these problems. A shield structure is formed on a wiring board on which electronic components are placed without complicating the manufacturing process, thereby reliably shielding electromagnetic noise. It is an object of the present invention to provide a highly reliable and low-cost wiring board.

  In order to solve the above problems, a wiring board according to the present invention includes a core substrate and a buildup layer in which insulating layers and conductor layers are alternately formed on both surfaces of the core substrate, and one of the buildup layers is provided. A wiring board capable of mounting an electronic component on a surface thereof, disposed on a region of one side of the buildup layer facing and electrically connected to a terminal group of the electronic component, and including at least palladium. A first electrode pad group having one plated layer formed on a surface thereof, and disposed on a region around the first electrode pad group on one surface of the build-up layer, wherein the first plated layer is formed on the surface; A second electrode pad group, and a metal member bonded to the upper part of the second electrode pad group and having a second plating layer not containing palladium formed on the surface thereof. Conductive material through the agent Junction configured to be able to cap member made.

  According to the wiring substrate of the present invention, the first electrode pad group and the surrounding second electrode pad group are provided on one surface of the buildup layer, the first plating layer is formed on each surface, and the first electrode is formed. Each terminal of the electronic component is joined to the upper part of the pad group, a metal member is joined to the upper part of the second electrode pad group, and a cap member is joined to the upper part of the metal member. Therefore, while forming the shield structure of the wiring board by the metal member and the cap member, the first plating layer common to the first electrode pad group and the second electrode pad group disposed on the same layer is formed to simplify the manufacturing process. Can be At this time, since the second plating layer is formed on the surface of the metal member in advance, the bonding strength of the cap member bonded through the conductive adhesive can be sufficiently ensured.

  For example, the first plating layer may be formed using nickel, palladium, or gold, and the second plating layer may be formed using nickel or gold. Moreover, an epoxy resin can be used for the material of the said conductive adhesive, for example. Furthermore, the metal member can be joined to the upper part of the second electrode pad group via solder.

  When the shield structure is formed by the metal member and the cap member, the second electrode pad group may be electrically connected to a predetermined conductor layer supplied with a ground potential in the buildup layer. In this case, the metal member may be formed in a ring shape surrounding the electronic component in a state where the electronic component is mounted on one surface of the buildup layer.

  In addition, in order to solve the above-described problem, a method for manufacturing a wiring board according to the present invention includes forming a buildup layer by alternately stacking insulating layers and conductor layers on both sides of a core substrate, and forming one of the buildup layers. A step of forming an electrode pad group on one surface of the build-up layer on a wiring board capable of mounting electronic components on the surface; and forming a first plating layer containing at least palladium on the surface of the electrode pad group And a metal member on the surface of which the second plating layer not containing palladium is formed, in the electrode pad group, one or a plurality of electrode pads arranged in a region around the electronic component mounting region. A manufacturing method including a step of bonding to the upper portion is applied, and a cap member made of a conductive material can be bonded to the upper portion of the metal member via a conductive adhesive.

  When the electrode pad group is formed, nickel, palladium, and gold plating layers are sequentially formed on the surface as the first plating layer, and the second plating layer is formed on the surface of the metal member. It is desirable to sequentially form nickel and gold plating layers. In addition, when the metal member is bonded to the upper part of one or a plurality of electrode pads arranged in a region around the electronic component, a reflow process may be performed by placing solder on the metal member.

  According to the present invention, when the shield structure is formed on the wiring board on which the electronic component is mounted, the common first plating layer is formed on the surface of all the electrode pads on one surface of the buildup layer, and the cap member Since the metal member having the second plating layer formed on the surface in advance is interposed for the attachment, it is possible to avoid complication of the manufacturing process associated with applying different plating layers to the same layer. And since the 2nd plating layer of a metal member does not contain palladium, the cap member joined to a metal member via a conductive adhesive can ensure sufficient adhesive strength. As described above, by adopting the structure of the present invention, it is possible to realize a wiring board that can reliably suppress noise by a shield structure with good characteristics and can be manufactured at a low cost by a simple manufacturing process.

1 is a schematic cross-sectional structure diagram of a wiring board 10 of an embodiment. It is a figure which shows an example of the top view of the wiring board 10 of FIG. It is the 1st modification of the wiring board 10 of Drawing 2 when paying attention to electrode pad 40b. It is the 2nd modification of the wiring board 10 of FIG. 2 when paying attention to the electrode pad 40b. 2 is a diagram showing a structural example in a state where a semiconductor chip 60, a plurality of chip capacitors 61, and a ring member 62 are joined to the upper part of the wiring board 10, respectively. FIG. It is a figure which shows the structural example at the time of attaching the cap member 65 to the upper part of the wiring board 10 of the state of FIG. It is a figure which shows the structural example of the ring member 62 which combined the several member piece. It is a 1st structure figure showing a manufacturing method of wiring board 10 of this embodiment. It is a 2nd structure figure which shows the manufacturing method of the wiring board 10 of this embodiment. It is a 3rd structure figure which shows the manufacturing method of the wiring board 10 of this embodiment. It is a 4th structure figure showing the manufacturing method of wiring board 10 of this embodiment.

  Hereinafter, a preferred embodiment of a wiring board to which the present invention is applied will be described with reference to the drawings.

  FIG. 1 is a schematic cross-sectional structure diagram of a wiring board 10 of the present embodiment. FIG. 1 shows a schematic cross-sectional structure of a wiring substrate 10 including a core substrate 11, a buildup layer 16 on the upper surface side of the core substrate 11, and a buildup layer 17 on the lower surface side of the core substrate 11. . The role of the wiring board 10 of the present embodiment is to mount an electronic component such as a semiconductor chip on the upper part and electrically connect the electronic component to an external circuit via the wiring board 10.

  The core substrate 11 is made of, for example, an epoxy resin containing glass fiber, and copper conductor layers 14 and 15 are formed on both surfaces thereof. A through-hole conductor 12 is formed at a predetermined location of the core substrate 11 on the inner wall of the through hole. The inside of the through hole is filled with a hole filling material 13 made of, for example, glass epoxy. The through-hole conductor 12 and the hole-filling material 13 extend vertically, penetrate the core substrate 11 in the laminating direction, and connect and conduct the upper conductor layer 14 and the lower conductor layer 15. In FIG. 1, only one set of through-hole conductors 12 and hole filling materials 13 are shown for simplicity, but an actual wiring board 10 has a large number of through-hole conductors 12 and holes for connecting various wirings. A filling material 13 is provided.

  One buildup layer 16 is formed on the surface of the core substrate 11 on the side of the conductor layer 14, and a resin insulating layer 21, a conductor layer 22, and a resin insulating layer 23 are sequentially laminated on the upper layer. The other buildup layer 17 is formed on the surface of the core substrate 11 on the conductor layer 15 side, and a resin insulating layer 24, a conductor layer 25, and a resin insulating layer 26 are sequentially laminated on the lower layer. A plurality of electrode pads 40 a and 40 b are formed on the surface of the upper resin insulation layer 23. The resin insulating layer 23 is covered with the solder resist layer 18, and the respective electrode pads 40 a and 40 b are exposed at predetermined locations where the solder resist layer 18 is opened. A plurality of BGA pads 50 are formed on the surface of the lower resin insulating layer 26. The resin insulating layer 26 is covered with the solder resist layer 19, and each BGA pad 50 is exposed at a predetermined location where the solder resist layer 19 is opened. A plating layer 41 is formed on the surface of each electrode pad 40a, 40b, and a plating layer 51 is formed on the surface of each BGA pad 50.

  In the build-up layer 16, a plurality of via conductors 30 are provided to penetrate the resin insulating layer 21 and connect the conductor layer 14 and the conductor layer 22 in the stacking direction, and the conductor layer penetrates the resin insulating layer 23. A plurality of via conductors 31 are provided to connect and connect 22 and the plurality of electrode pads 40a and 40b in the stacking direction. Further, the buildup layer 17 is provided with a plurality of via conductors 32 that penetrate the resin insulating layer 24 and connect the conductor layer 15 and the conductor layer 25 in the stacking direction and penetrate the resin insulating layer 26. A plurality of via conductors 33 are provided for connecting and conducting the conductor layer 25 and the plurality of BGA pads 50 in the stacking direction.

  The wiring board 10 of FIG. 1 is characterized by the arrangement and role of the plurality of electrode pads 40a and 40b. That is, the electrode pad 40a (first electrode pad group of the present invention) arranged near the center has a role of bonding a semiconductor chip as an electronic component, and the electrode pad 40b (second electrode of the present invention) arranged around the periphery. The pad group) has a role of joining metal members described later. A plated layer 41 (first plated layer of the present invention) using nickel, palladium, and gold is formed on each surface of the electrode pads 40a and 40b. A plurality of solder bumps 42 for bonding to a plurality of pads (not shown in FIG. 1) of the semiconductor chip are formed on the central electrode pad 40a and the plating layer 41. On the other hand, a metal member is bonded to the surrounding electrode pads 40b and the upper part of the plated layer 41 via solder, and is used to form a shield structure of the wiring board 10, which will be described in detail later.

  In order to specifically describe the arrangement of the plurality of electrode pads 40a and 40b, FIG. 2 shows an example of a top view of the wiring board 10 of FIG. First, in the vicinity of the center of the wiring substrate 10, 16 electrode pads 40a are arranged in an array in a region R1 facing the semiconductor chip. In addition, four electrode pads 40 b are arranged at the four corners of the wiring board 10. Further, in addition to the electrode pads 40a and 40b, a large number of chip capacitor electrode pads 43 (not shown in FIG. 1) are arranged outside the region R1. Each of these electrode pads 40a, 40b, 43 has the plating layer 41 formed on the surface thereof. In FIG. 2, 16 electrode pads 40a and 4 electrode pads 40b are shown. However, the number and arrangement of each are merely examples, and the electrode pads 40a and 40b are not limited to FIG. Various numbers and arrangements can be designed.

  3 and 4 show a modification of the wiring board 10 of FIG. 2 when attention is paid to the electrode pad 40b. That is, in FIG. 2, four electrode pads 40b are arranged separately at each corner, but as shown in the modification of FIG. 3, one electrode pad 40b formed continuously in a ring shape. May be provided. Further, FIG. 2 shows a case where each electrode pad 40b has a circular shape, but each electrode pad 40b may have a square shape as shown in the modification of FIG.

  FIG. 5 shows a structural example in which a semiconductor chip 60, a plurality of chip capacitors 61, and a ring member 62 (metal member of the present invention) are joined to the upper part of the wiring board 10 of FIGS. FIG. 5A shows a top view of the wiring board 10 in this state, and FIG. 5B shows a structure of a cross section aa ′ in the upper part of the wiring board 10 in FIG. 5A. . 5A is common to all of FIGS. 2 to 4, the structure of FIG. 5B is a modification in which the ring-shaped electrode pad 40 b of FIG. 3 is provided. It corresponds.

  As shown in FIG. 5A, the semiconductor chip 60 is mounted at a position overlapping the region R1 (FIGS. 2 to 4) of the wiring board 10. A plurality of pads 60 a (FIG. 5B) are provided on the lower surface of the semiconductor chip 60, and each pad 60 a is electrically connected to the electrode pad 40 a facing downward via the solder bump 42. . A total of 16 chip capacitors 61 are mounted around the region R1, one for each pair of adjacent electrode pads 43. These chip capacitors 61 are connected to the power supply wiring and the like of the semiconductor chip 60 via the wiring structure below each electrode pad 43.

  On the other hand, a ring member 62 formed in a ring shape along the outer shape of the wiring board 10 is disposed near the outer edge of the wiring board 10. As shown in FIG. 5B, the ring member 62 has a quadrangular cross-sectional shape, and a lower end thereof is joined to an electrode pad 40b facing downward via a solder 64. On the surface of the ring member 62, a plating layer 63 (second plating layer of the present invention) using nickel and gold is formed in advance. Note that the electrode pad 40b is not limited to the structure shown in FIG. 3, and the ring member 62 shown in FIG. 5 and the cross-sectional structure below it are common even in the structures shown in FIGS.

  FIG. 6 shows a structural example when a cap member 65 is attached to the upper part of the wiring board 10 in the state of FIG. 6A, the position of the wiring board 10 in FIG. 5A is indicated by a dotted line, but the cap member 65 is disposed so as to cover the wiring board 10 as a whole. As shown in FIG. 6B, a part of the lower surface of the cap member 65 is joined to the upper end of the ring member 62 via a conductive adhesive 66. The conductive adhesive 66 is made of, for example, conductive epoxy resin or low-temperature solder (Sn—Pb, Sn—Zn, Sn—Ag, etc.). The cap member 65 has a shape in which the outer edge portion is bent downward to form a side surface and surround the side surface of the wiring substrate 10.

  In FIG. 6, the ring member 62 and the cap member 65 integrally form a shield structure of the wiring board 10. 6B, the electrode pad 40b, the plating layer 41, the solder 64, the ring member 62 and the plating layer 63 on the surface thereof, the conductive adhesive 66, and the cap member 65 are electrically connected to each other. . In this case, the electrode pad 40b can be connected to the ground wiring of the conductor layer 22 through the lower via conductor 31, for example. Thereby, since the electrode pad 40b to the cap member 65 are all made of a conductive material, a shield structure connected to the ground potential can be realized.

  The material of the ring member 62 and the cap member 65 is not particularly limited. For example, a metal material such as Kovar, 42 alloy, aluminum, copper, or a copper alloy, or a conductive plastic material can be used. The shield structure including the ring member 62 and the cap member 65 may be connected to another fixed potential such as a power supply voltage in addition to the connection to the ground potential as described above, or connected to the fixed potential. You may keep in a floating state, without. However, in order to obtain a high shielding effect, it is desirable to connect the shield structure to the ground potential.

  Here, as already described, the plating layer 41 on the surface of the electrode pads 40a and 40b is formed of nickel, palladium, and gold, and the plating layer 63 on the surface of the ring member 62 is formed of nickel and gold. That is, the plating layer 41 is different in that it contains palladium and the plating layer 63 does not contain palladium. The reason why the plating layer 41 is formed on the surface of the electrode pads 40a and 40b is that when copper and solder are joined, nickel, palladium and gold plating are interposed between them to obtain good joining properties. On the other hand, the surface of the ring member 62 needs to be plated for preventing corrosion and preventing solder erosion. However, the conductive adhesive 66 is incompatible with plating containing palladium and the adhesive strength may be lowered. Are known. Therefore, a nickel or gold plating layer 63 not containing palladium is formed on the surface of the ring member 62.

  When forming the shield structure of the wiring board 10, a configuration in which a plating layer not containing palladium is directly formed on the surface of the electrode pad 40 b and the cap member 65 is joined to the upper portion thereof via the conductive adhesive 66 is also conceivable. . However, if this configuration is adopted, two types of plating are applied to the electrode pads 40a and 40b formed in the same layer on the upper surface of the buildup layer 16, so that the electrode pads 40a and 40b are formed on the surface of the central electrode pad 40a. Since the plating process for the power plating layer 41 and the plating mask for the plating layer (nickel, gold) to be formed on the surface of the surrounding electrode pad 40b need to be performed separately, the manufacturing process is reduced. It becomes extremely complicated. When a configuration in which the ring member 62 is separately attached as in the present embodiment is adopted, a single plating mask corresponding to one type of plating may be used for the electrode pads 40a and 40b, thereby simplifying the manufacturing process. be able to.

  The ring member 62 is not limited to an integral shape as shown in FIG. 5, and may have a structure in which a plurality of member pieces are combined as shown in FIG. FIG. 7A shows an example of the structure of the ring member 62 composed of two member pieces symmetrical left and right within the plane. FIG. 7B shows a structural example of the ring member 62 composed of four member pieces symmetrical in the vertical and horizontal directions in the plane. In any case, the cap member 65 can be bonded to the ring member 62 according to the same process with the ring member 62 bonded to the electrode pad 40b.

  Further, when it is not necessary to provide the plurality of chip capacitors 61 of FIG. 5 on the wiring board 10, the plurality of electrode pads 43 shown in FIGS. 2 to 4 may be omitted. Further, although not shown in FIGS. 2 to 4, a conduction lug is provided on each side in the plane of the wiring board 10, and the ring member 62 is connected to the ground wiring from each side of the wiring board 10 via the conduction lug. A structure may be adopted.

  Next, the manufacturing method of the wiring board 10 of this embodiment is demonstrated with reference to FIGS. First, as shown in FIG. 8, the core substrate 11 is prepared. The core substrate 11 is made of, for example, a copper clad laminate in which a copper foil is attached to both surfaces of a base material having a thickness of about 0.8 mm. Then, a drilling process is performed on the core substrate 11 to form a through hole. In this state, electroless copper plating and electrolytic copper plating are performed, and the surface is roughened. Next, the through-hole conductor 12 and the hole-filling material 13 are formed by filling the through-hole portion with an epoxy resin.

  Next, as shown in FIG. 9, a dry film is laminated on the copper foils on both sides of the core substrate 11, exposure and development are performed, electrolytic copper plating is performed, and then the dry film is peeled off. Thereby, the upper and lower conductor layers 14 and 15 of the core substrate 11 are formed. Next, a film-like insulating resin material is laminated on the upper and lower sides of the core substrate 11 with the conductor layers 14 and 15 interposed therebetween to form a resin insulating layer 21 on the upper surface side and a resin insulating layer 24 on the lower surface side. Subsequently, the resin insulating layers 21 and 24 are exposed and developed to open a plurality of via holes, and after heat curing, electrolytic copper plating is performed to form via conductors 30 and 32.

  Next, as shown in FIG. 10, a dry film is laminated on the surfaces of the resin insulating layers 21 and 24, exposed and developed, subjected to electrolytic copper plating, and then the dry film is peeled off. Thereby, the conductor layers 22 and 25 are formed above and below the resin insulating layers 21 and 24. Next, film-like insulating resin materials are laminated on the upper and lower sides of the resin insulating layers 21 and 24 with the conductor layers 22 and 25 interposed therebetween, respectively, to form an upper surface side resin insulating layer 23 and a lower surface side resin insulating layer 26. Subsequently, the resin insulating layers 23 and 26 are exposed and developed to open a plurality of via holes, and after heat curing, electrolytic copper plating is performed to form via conductors 31 and 33.

  Next, as shown in FIG. 11, a dry film is laminated on the surface of the resin insulating layer 23, exposure and development are performed, electrolytic copper plating and electroless copper plating are performed, and then the dry film is peeled off. Thereby, electrode pads 40a and 40b are formed. Further, a BGA pad 50 is formed on the surface of the resin insulating layer 26 by the same method. Next, a solder resist film is laminated on the upper surface of the resin insulation layer 23, and after exposure and development, thermal curing is performed to form the solder resist layer 18 in which the electrode pads 40a and 40b are exposed. Further, the solder resist layer 19 with the BGA pad 50 exposed is formed on the lower surface of the resin insulating layer 26 by the same method. The description will be made assuming that the electrode pads 43 for the chip capacitor 61 are not provided.

  Next, returning to FIG. 1, palladium, nickel, and gold are plated in this order on the surfaces of the electrode pads 40 a and 40 b to form a common plating layer 41. A plating layer 51 is also formed on the surface of the BGA pad 50 by the same method. Solder bumps 42 are formed on the electrode pads 40a disposed in the center and on the plating layer 41, respectively. A solder ball (not shown) for external connection is formed on each BGA pad 50.

  Next, as shown in FIG. 5B, a ring member 62 having a nickel and gold plating layer 63 formed on the surface in advance is prepared. Then, the ring member 62 is placed on the electrode pads 40 b arranged around and the plating layer 41 via solder 64. In this state, a reflow process is performed to heat and melt the solder 64 to a temperature of 200 to 350 degrees, and then the solder 64 is solidified to join the ring member 62. At this point, the wiring board 10 of this embodiment is completed.

  Thereafter, as shown in FIG. 6B, the semiconductor chip 60 is mounted in a state where each pad 60 a of the semiconductor chip 60 is bonded to each solder bump 42. In addition, a cap member 65 that covers the upper portion of the semiconductor chip 60 is attached with the conductive adhesive 66 applied to the upper end of the ring member 62. Thereby, the wiring substrate 10 in which the semiconductor chip 60 is shielded by the ring member 62 and the cap member 65 can be obtained.

  The contents of the present invention have been specifically described above based on the present embodiment, but the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. For example, in the present embodiment, an example in which the semiconductor chip 60 is mounted on the wiring board 10 has been described. However, the present invention is widely applied to the wiring board 10 on which various electronic components that can be bonded via the electrode pads 40a are mounted. Can be applied. Further, the shape and material of the ring member 62 and the cap member 65 are not limited to the example of the present embodiment, and the provision of these is not limited to the purpose of forming a shield structure, and the protection of electronic components, etc. Even if it is provided for the purpose, the present invention can be widely applied.

DESCRIPTION OF SYMBOLS 10 ... Wiring board 11 ... Core board 12 ... Through-hole conductor 13 ... Hole-filling material 14, 15, 22, 25 ... Conductor layer 16, 17 ... Build-up layer 18, 19 ... Solder resist layer 21, 23, 24, 26 ... Resin insulating layers 30, 31, 32, 33 ... via conductors 40a, 40b, 43 ... electrode pads 41, 51, 63 ... plated layer 42 ... solder bump 50 ... BGA pad 60 ... semiconductor chip 61 ... chip capacitor 62 ... ring member 64 ... solder 65 ... cap member 66 ... conductive adhesive

Claims (9)

A wiring board capable of mounting electronic components on one side of the buildup layer, comprising a core board and a buildup layer in which insulating layers and conductor layers are alternately formed on both sides of the core board,
1st electrode pad group which is arrange | positioned in the area | region which can be electrically connected facing the terminal group of the said electronic component among the one surfaces of the said buildup layer, and the 1st plating layer containing at least palladium was formed in the surface When,
A second electrode pad group disposed in a region around the first electrode pad group on one surface of the buildup layer, and the first plating layer formed on the surface;
A metal member bonded to the upper part of the second electrode pad group and having a second plating layer not containing palladium formed on the surface;
And a cap member made of a conductive material can be bonded to the upper part of the metal member via a conductive adhesive.   The wiring board according to claim 1, wherein the first plating layer is formed using nickel, palladium, and gold, and the second plating layer is formed using nickel and gold.   The wiring board according to claim 1, wherein the conductive adhesive is made of an epoxy resin.   4. The wiring board according to claim 1, wherein the metal member is bonded to an upper portion of the second electrode pad group via solder. 5.   The second electrode pad group is electrically connected to a predetermined conductor layer supplied with a ground potential in the build-up layer, and forms a shield structure in which the metal member is connected to the ground potential together with the cap member. The wiring board according to claim 1, wherein:   The wiring board according to claim 5, wherein the metal member is formed in a ring shape surrounding the electronic component in a state where the electronic component is mounted on one surface of the buildup layer. An insulating layer and a conductor layer are alternately laminated on both surfaces of a core substrate to form a buildup layer, and a method of manufacturing a wiring board capable of mounting an electronic component on one surface of the buildup layer,
Forming an electrode pad group on one surface of the build-up layer;
Forming a first plating layer containing at least palladium on the surface of the electrode pad group;
The metal member on which the second plating layer not containing palladium is formed is bonded to the upper part of one or a plurality of electrode pads arranged in a region around the electronic component mounting region in the electrode pad group. Process,
And a cap member made of a conductive material can be bonded to the upper part of the metal member via a conductive adhesive. On the surface of the electrode pad group, nickel, palladium and gold plating layers are sequentially formed as the first plating layer,
8. The method of manufacturing a wiring board according to claim 7, wherein nickel and gold plating layers are sequentially formed on the surface of the metal member as the second plating layer.   9. The metal member is placed on top of one or a plurality of electrode pads arranged in a region around the electronic component via solder, and bonded by performing a reflow process. The manufacturing method of the wiring board as described.

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