JP2015012022A - Printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed wiring board which has via conductors for composing a stacked via, which are good in electric reliability.SOLUTION: A printed wiring board comprises: a first build-up layer having a first insulation layer, a first conductor layer formed on the first insulation layer and a first via conductor which pierces the first insulation layer and links to the first conductor layer; a second build-up layer having a second insulation layer formed on the first build-up layer, a second conductor layer formed on the second insulation layer and a second via conductor which pierces the second insulation layer, for electrically connecting the first conductor layer and the second conductor layer; and a third build-up layer having a third insulation layer formed on the second build-up layer, a third conductor layer formed on the third insulation layer and a third via conductor which pierces the third insulation layer, for electrically connecting the third conductor layer and the second conductor layer. A thermal expansion coefficient of the second insulation layer is smaller than a thermal expansion coefficient of each of the first insulation layer and the third insulation layer. The first via conductor, the second via conductor and the third via conductor form a stacked via structure.

Description

  The present invention relates to a printed wiring board.

  Japanese Patent Application Publication No. 2008-112987 (Patent Document 1) discloses a wiring substrate having a stacked via. In FIG. 1 of Patent Document 1, each via conductor forming a stacked via is positioned in a straight line. In FIG. 5 of Patent Document 1, the axis of the lowermost via conductor (the via conductor closest to the core material) forming the stacked via is offset from the axis of the other via conductor. In FIG. 1 of Patent Document 1, four via conductors are arranged in a straight line, and in FIG. 5 of Patent Document 1, three via conductors are arranged in a straight line. Moreover, the thermal expansion coefficient of the interlayer insulating material in which the via conductor is formed is 35 ppm / ° C. or more and 50 ppm / ° C. or less.

JP 2008-112987 A

  The wiring board shown in FIG. 1 of Patent Document 1 has a core material. In order to make the printed wiring board thinner, a printed wiring board having no core material and a printed wiring board having a thin core material have been developed. Even if the thermal expansion coefficient of the interlayer insulating material is not less than 35 ppm / ° C. and not more than 50 ppm / ° C., three or more via conductors as shown in FIG. When the stack via stacked on the stack is formed, it is considered that a large stress acts between the stack via and the conductor circuit to which the stack via is connected in the heat cycle. The stress is expected to reduce the connection reliability between the stack via and the conductor circuit to which the stack via is connected.

  The contents of Japanese Patent Application Publication No. 2008-112987 are incorporated in this specification.

  The printed wiring board according to the present invention includes a first insulating layer, a first conductor layer formed on the first insulating layer, and a first conductor layer penetrating the first insulating layer and connected to the first conductor layer. A first build-up layer having one via conductor; a second insulating layer formed on the first build-up layer; a second conductor layer formed on the second insulating layer; A second buildup layer having a second via conductor penetrating through the two insulating layers and electrically connecting the first conductor layer and the second conductor layer; and formed on the second buildup layer. A third insulating layer, a third conductor layer formed on the third insulating layer, and electrically connecting the third conductor layer and the second conductor layer through the third insulating layer; And a third buildup layer having a third via conductor. A thermal expansion coefficient of the second insulating layer is smaller than a thermal expansion coefficient of the first insulating layer and a thermal expansion coefficient of the third insulating layer, and the first via conductor, the second via conductor, and the third Via conductors are stacked like a staircase, and the first via conductor, the second via conductor, and the third via conductor form a stacked via structure.

Sectional drawing which shows the printed wiring board which concerns on one Embodiment of this invention. Sectional drawing which shows the printed wiring board which concerns on another embodiment of this invention. The figure explaining a double-sided copper-clad laminated board. The figure explaining the process of forming a through-hole. The figure explaining the process of forming a through-hole conductor. The figure explaining the process of forming a conductor layer. 10A and 10B illustrate a step of forming an insulating layer. The figure explaining the process of forming the opening for via conductors. The figure explaining the process of forming a conductor layer and a via conductor. The figure explaining the process of forming a 2nd buildup layer. The figure explaining the process of forming a 3rd buildup layer. The figure explaining the process of forming a soldering resist layer and a solder bump. The perspective view which shows an inductor. Sectional drawing which shows the printed wiring board which incorporates an inductor. Sectional drawing of a stack via structure. The conceptual diagram which looked at the stacked via structure from the upper surface. Sectional drawing of a stack via structure. Sectional drawing of a stack via structure.

  A printed wiring board having no core material, a printed wiring board having a core material having a thickness of 400 μm or less, and a printed wiring board having a C4 pad pitch of 130 μm or less are shown in FIG. When the thermal expansion coefficient of each interlayer resin insulating layer through which the via structure is formed and the stacked via structure passes through is the same, it is expected that a large stress is applied to the stacked via structure. It is assumed that the connection reliability of the stacked via structure is lowered due to the stress.

  Hereinafter, a printed wiring board and a manufacturing method thereof according to an embodiment of the present invention will be described in detail with reference to the drawings. In the figure, arrows Z1 and Z2 indicate the stacking direction of the wiring boards (or the thickness direction of the wiring boards) corresponding to the normal direction of the main surface (front and back surfaces) of the wiring boards. On the other hand, arrows X1, X2 and Y1, Y2 indicate directions orthogonal to the stacking direction. The main surface of the printed wiring board is an XY plane.

  The conductor layer includes one or more conductor circuits. The conductor layer includes pads, lands, and the like.

  The land is a conductor formed on or around the opening for the via conductor or the through hole for the through-hole conductor, and the land is directly connected to the via conductor or the through-hole conductor. When the via conductor is a filled via, the land of the via conductor is formed around the via conductor and on the via conductor. Via conductors and through-hole conductors are conductors formed in openings and through holes.

  Examples of stacked via structures are shown in FIGS. 7A, 7B, and 7C. FIG. 7A shows a stacked via structure formed by two via conductors (via conductor UV and via conductor LV). FIG. 7C shows a stacked via structure formed of three via conductors. FIG. 7B shows the top surface of the land of the via conductor LV and the like. An outer periphery S111 of the land of the via conductor LV is indicated by a solid line, and a bottom opening S123 of the via conductor UV is indicated by a dotted line. Furthermore, the top opening S112 of the via conductor LV is indicated by a broken line. The via conductor UV is formed on the land of the via conductor LV, and the bottom surface of the via conductor UV is located in the land of the via conductor LV. FIG. 7A corresponds to FIG. 7B. Each via conductor of the stacked via structure is preferably a filled via.

(Embodiment)
A printed wiring board 1000 according to this embodiment is shown in FIG. In this specification, the printed wiring board is also referred to as a wiring board.

  As shown in FIG. 1, the wiring board 1000 includes a core substrate 104 having a first surface F <b> 1 and a second surface F <b> 2 opposite to the first surface. The core substrate 104 includes an insulating layer 10 having a first surface F1 and a second surface F2 opposite to the first surface, an upper conductor layer 20a on the first surface F1 of the insulating layer 10, and an insulating layer 10 The lower conductor layer 20b on the second surface F2 and the through-hole conductor 101 that penetrates the insulating layer 10 and connects the upper conductor layer 20a and the lower conductor layer 20b. The insulating layer 10 is formed of a cured resin and a reinforcing material such as a glass cloth.

  The wiring board 1000 further includes a first insulating layer (lower first insulating layer) 11b formed on the second surface F2 of the core substrate, and a first conductor formed on the first insulating layer 11b. Layer (lower first conductor layer) 21b, and first via conductor (lower side conductor) penetrating the first insulating layer 11b and connecting the first conductor layer 21b and the lower conductor layer 20b of the core substrate. A first buildup layer (lower first buildup layer) B1b formed with the first via conductor (31b). The wiring board 1000 further includes a second insulating layer (lower second insulating layer) 12b formed on the lower first buildup layer B1b and a second insulating layer 12b formed on the second insulating layer 12b. A second via conductor (lower second conductor layer) 22b, which penetrates the second insulating layer 12b and connects the second conductor layer 22b and the first conductor layer 21b. And a second buildup layer (lower second buildup layer) B2b formed of the via conductor (32b). The wiring board 1000 further includes a third insulating layer (lower third insulating layer) 13b formed on the lower second buildup layer B2b and a third insulating layer 13b formed on the third insulating layer 13b. A third via conductor (lower third via) that penetrates the third conductor layer (lower third conductor layer) 23b and the third insulating layer 13b and connects the second conductor layer 22b and the third conductor layer 23b. And a third buildup layer (lower third buildup layer) B3b formed of the conductor 33b.

  A lower buildup layer Bb is formed by the lower first buildup layer B1b, the lower second buildup layer B2b, and the lower third buildup layer B3b. The printed wiring board may be formed of only the lower buildup layer Bb.

  The wiring board 1000 further includes a first insulating layer (upper first insulating layer) 11a formed on the first surface F1 of the core substrate, and a first conductor layer formed on the first insulating layer 11a. (Upper first conductor layer) 21a and a first via conductor that penetrates the first insulating layer 11a and connects the first conductor layer 21a and the upper conductor layer 20a of the core substrate (upper first via conductor) And a first buildup layer (upper first buildup layer) B1a formed of 31a. The wiring board 1000 further includes a second insulating layer (upper second insulating layer) 12a formed on the upper first buildup layer B1a and a second conductor formed on the second insulating layer 12a. A layer (upper second conductor layer) 22a, and a second via conductor (upper second via conductor) 32a penetrating the second insulating layer 12a and connecting the second conductor layer 22a and the first conductor layer 21a; The second buildup layer (upper second buildup layer) B2a is formed. The wiring board 1000 further includes a third insulating layer (upper third insulating layer) 13a formed on the upper second buildup layer B2a and a third conductor formed on the third insulating layer 13a. A layer (upper third conductor layer) 23a, and a third via conductor (upper third via conductor) 33a passing through the third insulating layer 13a and connecting the second conductor layer 22a and the third conductor layer 23a; The third buildup layer (upper third buildup layer) B3a is formed.

  The upper buildup layer Ba is formed by the upper first buildup layer B1a, the upper second buildup layer B2a, and the upper third buildup layer B3a. The printed wiring board may be formed of only the upper buildup layer Ba.

  The wiring board 1000 has openings 52b and 51b for exposing the conductor circuit 232b included in the lower third conductor layer 23b and the land 231b of the lower third via conductor 33b on the lower buildup layer Bb. You may have the lower soldering resist layer 5b which has. The conductor circuit 232b included in the lower third conductor layer 23b exposed by the opening and the land 231b of the lower third via conductor 33b function as BGA pads, and solder bumps for connecting to the motherboard on the BGA pads (BGA bumps) 62b and 61b are formed.

  The wiring board 1000 has upper openings 52a and 51a on the upper buildup layer Ba that expose the conductor circuit 232a included in the upper third conductor layer 23a and the land 231a of the upper third via conductor 33a. You may have the soldering resist layer 5a. The conductor circuit 232a included in the upper third conductor layer 23a exposed through the opening and the land 231a of the upper third via conductor 33a function as C4 pads, and solder bumps (C4 for mounting an IC on the C4 pads) Bumps) 62a and 61a are formed. The distance between the centers of gravity of adjacent C4 pads is the C4 pad pitch.

The printed wiring board may be formed of only the lower buildup layer Bb and the lower solder resist layer 5b.
The printed wiring board may be formed of a solder resist layer that sandwiches the lower buildup layer and the lower buildup layer. In that case, solder resist layers are formed on both sides of the lower buildup layer.

  In the printed wiring board of the present invention, the first buildup layer includes a plurality of first conductor layers, a plurality of first insulating layers, and a plurality of first via conductors penetrating each first insulating layer. You may have. Here, the first conductor layers and the first insulating layers are alternately stacked, and adjacent conductor layers are sandwiched between adjacent conductor layers and connected by first via conductors that penetrate the first insulating layer. Similarly, the third buildup layer may include a plurality of third conductor layers, a plurality of third insulating layers, and a plurality of third via conductors penetrating each third insulating layer. Here, the third conductor layer and the third insulating layer are alternately laminated, and the adjacent conductor layers are sandwiched between the adjacent conductor layers and connected by the third via conductor that penetrates the third insulating layer. For example, in the embodiment shown in FIG. 2, the first buildup layer B1a passes through the first conductor layer 2101a and the first conductor layer 2102a, the first insulation layer 111a and the first insulation layer 112a, and the first insulation layers. A first via conductor 311a and a first via conductor 312a. Here, the first conductor layer and the first insulating layer are laminated in the order of the first insulating layer 111a, the first conductor layer 2101a, the first insulating layer 112a, and the first conductor layer 2102a, and the adjacent conductor layer 2101a and the conductor layer are laminated. 2102a is connected by a first via conductor 312a that penetrates the first insulating layer 112a, and the first conductor layer 2101a and the conductor layer 20a of the core substrate are connected by a first via conductor 311a that penetrates the first insulating layer 111a.

  The number of upper first insulating layers belonging to the upper first buildup layer is preferably the same as the number of upper third insulating layers belonging to the upper third buildup layer. The number of lower first insulating layers belonging to the lower first buildup layer is preferably the same as the number of lower third insulating layers belonging to the lower third buildup layer.

  The lower second insulating layer is positioned in the center in the cross-sectional direction Z1-Z2 of the printed wiring board in the lower buildup layer. Therefore, even if the lower buildup layer includes insulating layers having different thermal expansion coefficients, warpage of the printed wiring board is reduced. The number of upper first insulating layers belonging to the upper first buildup layer is preferably the same as the number of lower first insulating layers belonging to the lower first buildup layer. The number of upper third insulating layers belonging to the upper third buildup layer is preferably the same as the number of lower third insulating layers belonging to the lower third buildup layer.

The thermal expansion coefficient of the lower second insulating layer 12b is such that the lower first insulating layer 11b belonging to the lower first buildup layer B1b and the lower third insulating layer 12b belonging to the lower third buildup layer B3b. It is smaller than the thermal expansion coefficient of the insulating layer 13b. The thermal expansion coefficient of the lower first insulating layer 11b belonging to the lower first buildup layer B1b is equal to the thermal expansion coefficient of the lower third insulating layer 13b belonging to the lower third buildup layer B3b. Is preferred.
The thermal expansion coefficient of the upper second insulating layer 12a is such that the heat of the upper first insulating layer 11a belonging to the upper first buildup layer B1a and the upper third insulating layer 13a belonging to the upper third buildup layer B3a. It is preferably smaller than the expansion coefficient.
The thermal expansion coefficient of the lower first insulating layer 11b belonging to the upper first buildup layer B1b is preferably equal to the thermal expansion coefficient of the lower third insulating layer 13b belonging to the upper third buildup layer B3b. . The thermal expansion coefficient of the upper second insulating layer 12a is preferably the same as the thermal expansion coefficient of the lower second insulating layer 12b. The insulating layers belonging to the upper and lower buildup layers similarly shrink in the heat cycle.

  When the volume of the conductor belonging to the upper buildup layer is smaller than the volume of the conductor belonging to the lower buildup layer, the thermal expansion coefficient of the upper first insulating layer belonging to the upper first buildup layer and the upper first The thermal expansion coefficient of the upper third insulating layer belonging to the three buildup layers is preferably equal to the thermal expansion coefficient of the upper second insulating layer. Since the volume of the conductor of the upper buildup layer is small, the upper buildup layer has low rigidity. For this reason, if the thermal expansion coefficients of the insulating layers are different, there is a possibility that the warp of the printed wiring board is increased or peeling occurs between the upper third buildup layer and the upper second buildup layer. is there.

  As a method of making the thermal expansion coefficient of the lower second insulating layer 12b smaller than the thermal expansion coefficients of the other insulating layers, for example, a method of using a resin having a low thermal expansion coefficient for the insulating layer 12b, or a method of using the insulating layer 12b The method of adding fillers, such as an inorganic particle, to resin is mentioned. By making the amount of inorganic particles contained in the lower second insulating layer 12b larger than the amount of inorganic particles contained in the other insulating layers, the thermal expansion coefficient of the lower second insulating layer 12b is other than that. It becomes smaller than the thermal expansion coefficient of the insulating layer. When an aramid film is used for the lower second insulating layer 12b and an epoxy film is used for the other insulating layers, the thermal expansion coefficient of the lower second insulating layer 12b is other than that. It becomes smaller than the thermal expansion coefficient of the insulating layer. Specifically, in the range of 25 ° C. to 150 ° C., the thermal expansion coefficient of the lower second insulating layer 12b is 15 ppm / ° C. to 30 ppm / ° C., which is larger than that of the lower second insulating layer 12b. Other insulating layers having a thermal expansion coefficient have a thermal expansion coefficient of 35 ppm / ° C. to 50 ppm / ° C.

  Further, the thermal expansion coefficient of the lower second insulating layer 12b is preferably 70% or less of the thermal expansion coefficient of the other insulating layer having a larger thermal expansion coefficient than the lower second insulating layer 12b, and is 50%. Or less, more preferably 30% or less. Here, the thermal expansion coefficient of the insulating layer is a thermal expansion coefficient in the finished product of the printed wiring board, and is a value in the range of 25 ° C to 150 ° C. The thermal expansion coefficient is a value in the main surface direction of the wiring board.

  The insulating layer 10 of the core substrate 104 is made of, for example, a reinforcing material such as glass cloth and a cured epoxy resin.

  The insulating layer belonging to the upper buildup layer Ba and the insulating layer belonging to the lower buildup layer Bb are each formed of a resin and inorganic particles. All the insulating layers can further have a reinforcing material. In this case, the thermal expansion coefficient can be changed depending on the type of resin and the amount of inorganic particles. Only the lower second insulating layer may include a reinforcing material such as glass cloth. The thermal expansion coefficient of the lower second insulating layer is smaller than the thermal expansion coefficients of the other insulating layers. Moreover, since the rigidity of the lower buildup layer is increased, the warp of the printed wiring board is reduced.

  As shown in FIG. 1, the stacked via structure S1 formed by the upper first via conductor 31a, the upper second via conductor 32a, and the upper third via conductor 33a is formed in the upper buildup layer Ba. Is formed. The upper first via conductor 31a of the upper stacked via structure S1 is formed on the upper conductor layer 20a of the core substrate 104. In FIG. 1, the central axis of the upper first via conductor 31a forming the upper stacked via structure S1, the central axis of the upper second via conductor 32a, and the central axis of the upper third via conductor 33a coincide. ing. Such a stacked via structure is referred to as a concentric axis stacked via structure. Here, the central axis is a straight line passing through the center of the top opening of the via conductor opening formed on the upper surface of the insulating layer 11a and perpendicular to the main surface such as the first surface of the core substrate of the printed wiring board. An opening for a via conductor is formed from the upper surface by a laser or the like. The top opening is an opening of the via conductor opening at the interface between the insulating layer and the land of the via conductor. A bottom surface of the via conductor is formed on the lower surface opposite to the upper surface. However, the upper stack via structure may not be a concentric stack via structure.

  Further, as shown in FIG. 1, the lower stacked via structure S2 formed by the lower first via conductor 31b, the lower second via conductor 32b, and the lower third via conductor 33b is provided. It is formed in the lower buildup layer Bb. The lower first via conductor 31b of the lower stacked via structure S2 is formed on the lower conductor layer 20b of the core substrate 104. In FIG. 1, the central axis of the lower first via conductor 31b, the central axis of the lower second via conductor 32b, and the center of the lower third via conductor 33b forming the lower stacked via structure S2. The axis is offset. The lower stacked via structure S2 is inclined with respect to the normal (Z-axis) direction of the main surface of the wiring board. In FIG. 1, the lower stack via structure S2 is a step-type stack via structure. The central axis of each via conductor forming the lower stacked via structure S2 moves in order from the lower first via conductor 31b toward the lower third via conductor 33b in the outer circumferential direction of the printed wiring board. ing. In this specification, the term “peripheral direction of the printed wiring board” means a direction from the central portion of the main surface of the printed wiring board toward the outer periphery. A straight line that passes through the center of gravity of the first surface of the core substrate and is perpendicular to the first surface of the core substrate is referred to as the central axis of the printed wiring board. For example, the distance between the central axis of the printed wiring board and the central axis of the lower second via conductor is larger than the distance between the central axis of the printed wiring board and the central axis of the lower first via conductor. The via conductor UV is laminated on the via conductor LV (FIG. 7A). The lower third via conductor is similarly formed on the lower second via conductor. The configuration of the insulating layer of the upper buildup layer Ba is the same as the configuration of the insulating layer of the lower buildup layer Bb, and the upper buildup layer may have a stepped stack via structure.

  In the concentric stack via structure, the center axis of each via conductor is coincident, so stress is applied to the interface between the land of the via conductor and the via conductor connected to the via conductor and the center axis of the via conductor. Easy to concentrate. Therefore, there is a possibility that the connection reliability of the concentric axis stack via structure deteriorates in a heat cycle. On the other hand, in the staircase type stacked via structure, since the central axes of the via conductors do not coincide with each other, it is difficult for stress to concentrate on one place. In the staircase type stacked via structure, since the central axes of the via conductors do not coincide with each other, horizontal wiring (via conductor land) of the printed wiring board exists between the central axes of the upper and lower via conductors. The stress is relieved by the horizontal wiring. Therefore, the connection reliability of the staircase type stacked via structure is high. Here, the horizontal direction of the printed wiring board is a direction parallel to the main surface of the printed wiring board.

  FIG. 7A shows two adjacent via conductors in a stepped stacked via structure. In the drawing, the via conductor drawn at the top is the lower via conductor LV, and the via conductor drawn at the bottom is the upper via conductor UV. The upper via conductor UV is stacked on the land of the lower via conductor LV. The via conductor UV is close to the lower solder resist layer, and the via conductor LV is close to the core substrate. The distance between the central axis of the upper via conductor and the central axis of the lower via conductor is the shift amount δ, which is shown in FIG. 7A.

  In the example of FIGS. 7A and 7B, the bottom surface of the upper via conductor UV is not located on the top opening of the lower via conductor LV. The bottom surface of the upper via conductor UV is formed on the land of the lower via conductor LV, but is formed on a land other than the land on the top opening of the lower via conductor. However, according to the examples of FIGS. 7A and 7B, since the shift amount is large, the size of the printed wiring board increases as the number of build-up layers increases. If the number of insulating layers of the build-up layer having a staircase type stacked via structure is four or more, the connection reliability of the stacked via structure is likely to be lowered due to the size of the printed wiring board. When a staircase type stacked via structure is formed in a build-up layer having four or more insulating layers, the staircase type stacked via structure shown in FIG. 7C is preferable. In the example of FIG. 7C, the bottom surface of the upper via conductor is located on the outer periphery S112 of the top opening of the lower via conductor. Therefore, the shift amount in FIG. 7C is smaller than the shift amount in FIG. 7B. The size of the printed wiring board is reduced. The effect of stress due to the size of the printed wiring board is reduced. The connection reliability of the staircase type stacked via structure is increased. Furthermore, it is preferable that the central axis of the upper via conductor passes through the top opening of the lower via conductor. The size of the printed wiring board is reduced. It is preferable that the stack via structure is a step-type stack via structure, and the entire bottom surface of the upper via conductor is formed on the top opening of the lower via conductor. The size of the printed wiring board is reduced. Since the bottom is not located on the outer periphery of the top opening, it is difficult for the upper via conductor to receive complicated stress.

  The shift amount δ12 between the lower first via conductor 31b and the lower second via conductor 32b is preferably smaller than the shift amount δ23 between the lower second via conductor 32b and the lower third via conductor 33b. . Since the insulating layer and the conductor layer forming the build-up layer are made of different materials, the printed wiring board contracts during the heat cycle, and the printed wiring board is warped. The warp places stress on the stacked via structure. In this embodiment, since the thermal expansion coefficient of the lower second insulating layer 12b is smaller than the thermal expansion coefficients of the other insulating layers 11b and 13b, the stress increases. In this embodiment, the lower stacked via structure S2 is inclined in the outer peripheral direction of the printed wiring board. Therefore, the lower third via conductor 33b is located outside the printed wiring board from the lower second via conductor 32b. Since the deformation amount of the outer peripheral region of the printed wiring board is larger than the deformation amount of the central region of the printed wiring board, the stress between the lower third via conductor 33b and the lower second via conductor 32b is lower. This is considered to be greater than the stress between the second via conductor 32b and the lower first via conductor 31b. By making the shift amount δ23 larger than the shift amount δ12, the stress between the lower third via conductor 33b and the lower second via conductor 32b can be alleviated. The reliability of the lower stacked via structure is improved.

  The shift amount δ is preferably 5 μm to 50 μm. If the shift amount is less than 5 μm, the stress tends to concentrate on one place. When the shift amount exceeds 50 μm, the stress applied to the stacked via structure increases due to the influence of the size of the printed wiring board.

The printed wiring board according to the embodiment of the present invention has a staircase type stacked via structure. Therefore, the size of the printed wiring board tends to be larger than that of the printed wiring board that does not have the staircase type stacked via structure. As the size increases, the amount of deformation of the printed wiring board increases. Stress applied to the stacked via increases. The printed wiring board of the embodiment is suitable for a printed wiring board for mounting an IC chip. An IC chip is mounted on the printed wiring board of the embodiment, and the printed wiring board of the embodiment is mounted on a motherboard. Therefore, in order to reduce the stress applied to the printed wiring board, the thermal expansion coefficient of the printed wiring board is preferably a value between the thermal expansion coefficient of the IC chip and the thermal expansion coefficient of the motherboard. In order to reduce the influence of the size, in the embodiment, the thermal expansion coefficient of the lower second insulating layer is smaller than the thermal expansion coefficients of the other insulating layers. Further, in order to adjust the thermal expansion coefficient of the printed wiring board of the embodiment, in the embodiment, the thermal expansion coefficient of the lower second insulating layer 12b is smaller than the thermal expansion coefficients of the other insulating layers 11b and 13b. Since the lower second insulating layer 12b having a small thermal expansion coefficient is formed between the lower first buildup layer B1b and the lower third buildup layer B3b, the lower first buildup layer The deformation of B1b and the deformation of the lower second buildup layer B2b can be suppressed. In addition, the thermal expansion coefficient of the printed wiring board can be adjusted efficiently. Therefore, the connection reliability of the staircase type stacked via structure is increased. If the lower first buildup layer B1b and the lower third buildup layer B3b are laminated on the lower second insulating layer 12b having a small thermal expansion coefficient, the lower second insulating layer 12b is laminated. And the lower third buildup layer B3b become longer. Therefore, it is difficult to suppress the deformation of the lower third buildup layer B3b with the lower second insulating layer 12b. It is considered that the connection reliability of the stacked via structure is lowered.
In view of the above, the upper buildup layer also has a stepped stack via structure, and the thermal expansion coefficient of the upper second insulating layer is higher than the thermal expansion coefficient of the upper first buildup layer insulating layer and / or It is preferable that it is smaller than the thermal expansion coefficient of the insulating layer of the upper third buildup layer.

  In the present embodiment, the upper stacked via structure S1 is formed by the via conductors of all layers of the upper buildup layer Ba, and the lower stacked via structure S2 is formed by the via conductors of all layers of the lower buildup layer Bb. It is formed. For this reason, it becomes easy to secure the wiring space, and the degree of freedom in designing the wiring pattern increases. As a result, high-density wiring is easily realized. Also, wiring in the X direction or Y direction can be omitted. Therefore, the wiring length can be shortened.

  The upper stacked via structure S1 and the lower stacked via structure S2 are electrically connected through the through-hole conductor 101.

  Since the stress directly under the IC chip is large, it is preferable that the stepped stack via structure S2 is formed immediately under the IC chip. There may be a plurality of stacked via structures S1 and S2.

  The size of the via conductor is not particularly limited. For example, the width D1 (top opening diameter) of the via conductor opening is 100 μm, and the bottom width D2 (bottom opening diameter) of the via conductor 31b is 80 μm. In the present embodiment, each via conductor has substantially the same dimensions.

  When the stack via structure is inclined in the normal direction of the main surface of the wiring board, stress tends to concentrate near the center of the stack via structure in the thickness direction. In particular, heat is applied to the wiring board in the process. In such a case, stress due to the difference in thermal expansion coefficient between the insulating layer and the conductor layer tends to concentrate near the center in the thickness direction during cooling. Therefore, a load is applied to the stacked via structure, and cracks or delamination may occur. This is presumably because the stress is difficult to escape near the center in the thickness direction. In this embodiment, the via conductor located at the center in the thickness direction of the stacked via structure is made by making the thermal expansion coefficient of the insulating layer located near the center in the thickness direction smaller than the thermal expansion coefficient of the other insulating layers. It is considered that the stress applied to is reduced. Generation of peeling between the bottom surface of the via conductor and the land of the via conductor can be prevented. It is considered that an insulating layer having a small thermal expansion coefficient suppresses deformation of the insulating layer sandwiching the insulating layer. For this reason, it is assumed that the stress applied between the via conductors formed in the insulating layer having a small thermal expansion coefficient and the via conductors formed above and below the via conductors is small, so that problems such as peeling are unlikely to occur. . Further, it is considered that the deformation amount in the portion located at the center in the thickness direction becomes relatively smaller than the deformation amounts of the other insulating layers. Thus, according to this embodiment, the connection reliability of the printed wiring board is improved.

  The number of insulating layers belonging to the buildup layer is preferably 4 or more and 13 or less. Since the stress applied to the stacked via structure is large when the number of insulating layers is four or more, a step-type stacked via structure is preferable. When the insulating layer is 14 layers or more, the stress applied to the stacked via structure is too large. Problems are likely to occur in the stacked via structure. When the number of insulating layers in the buildup layer is n and an even number, the number of insulating layers in the first buildup layer is n / 2, and the number of insulating layers in the second buildup layer is 1. It is preferable that the number of layers in the third buildup layer is (n / 2-1). When the number of insulating layers of the buildup layer is n and an odd number, the number of insulating layers of the first buildup layer is ((n−1) / 2) layers, and the insulation of the second buildup layer The number of layers is preferably one, and the number of third buildup layers is preferably ((n-1) / 2). A plurality of insulating layers (insulating layers having a smaller thermal expansion coefficient than other insulating layers) of the second buildup layer may be provided. Since the thermal expansion coefficient of the printed wiring board is reduced, the reliability of the staircase type stacked via structure is increased.

  The lower buildup layer may have the multilayer inductor 400 shown in FIG. A multilayer inductor is formed of a via conductor that connects a coil pattern included in a conductor layer and a coil pattern formed in an adjacent conductor layer. For example, as shown in FIG. 5, the multilayer inductor 400 is a via conductor that connects three layers of conductor patterns (coil patterns) and adjacent coil patterns, and an inductor of approximately 1.5 turns is formed. The coil pattern 401 is included in the lower first conductor layer, the coil pattern 402 is included in the lower second conductor layer, and the coil pattern 403 is included in the lower third conductor layer. The via conductor 411 is included in the lower first via conductor, the via conductor 412 is included in the lower second via conductor, and the via conductor 413 is included in the lower third via conductor. When the multilayer inductor is formed in the lower buildup layer, the volume of the conductor in the upper buildup layer and the volume of the conductor in the lower buildup layer are greatly different. Therefore, the warp of the printed wiring board is increased. Therefore, the lower buildup layer having the multilayer inductor has a staircase type stacked via structure, and the lower first buildup layer B1b and the lower second buildup layer B2b described in the embodiment. And the lower third buildup layer B3b.

  FIG. 6 shows a lower buildup layer having a multilayer inductor. The insulating layer 11b is a lower first insulating layer, the insulating layer 12b is a lower second insulating layer, and the insulating layer 13b is a lower third insulating layer. The thermal expansion coefficient of the lower second insulating layer 12b is smaller than the thermal expansion coefficients of the lower first insulating layer 11b and the lower third insulating layer 13b. Further, as shown in FIG. 6, the lower buildup layer includes a staircase type stacked via structure S2.

  Hereinafter, a method for manufacturing the printed wiring board 1000 according to the present embodiment will be described.

  As shown in FIG. 3A, a double-sided copper clad laminate 100 (starting material) is prepared. The double-sided copper-clad laminate 100 includes an insulating layer 10 having a first surface F1 and a second surface F2 opposite to the first surface F1, and a metal foil 102a laminated on the first surface F1 of the insulating layer 10. , And the metal foil 102b laminated on the second surface F2 of the insulating layer 10. The thickness of the insulating layer 10 is 60 to 600 μm.

  Subsequently, as shown in FIG. 3B, a through hole 103 for a through hole conductor is formed in the copper clad laminate 100.

  Subsequently, an electroless copper plating process and an electrolytic copper plating process are performed in the through hole 103 and on the metal foils (copper foils) 102a and 102b. The through hole 103 is filled with an electrolytic copper plating film. A through-hole conductor is formed in the through hole (see FIG. 3C).

  Then, the upper conductor layer 20a is formed on the first surface of the insulating layer 10 and the lower conductor layer 20b is formed on the second surface of the insulating layer 10 by a so-called tenting method (see FIG. 3D). . Each of the conductor layers 20a and 20b includes conductor circuits 202a and 202b and through-hole conductor lands 201a and 201b, respectively. A core substrate 104 is obtained (see FIG. 3D). The first surface F1 of the core substrate 104 and the first surface of the insulating layer 10 are the same, and the second surface F2 of the core substrate 104 and the second surface of the insulating layer 10 are the same.

  4A, an upper first insulating layer (upper first interlayer resin insulating layer) 11a is formed on the first surface F1 of the core substrate 104, and the second surface F2 of the core substrate 104 is formed. A lower first insulating layer (lower first interlayer resin insulating layer) 11b is formed thereon.

  Subsequently, as shown in FIG. 4B, using a laser or the like, a via hole 311a that penetrates the upper first insulating layer 11a to reach the upper conductor layer 20a is formed, and penetrates the lower first insulating layer 11b. Then, a via hole 311b reaching the lower conductor layer 20b is formed.

  Subsequently, as shown in FIG. 4C, the upper first conductor layer 21a is formed on the upper first insulating layer 11a by the semi-additive method, and the upper conductor layer 20a and the upper first conductor layer are formed in the via hole 311a. An upper first via conductor 31a connecting 21a is formed. The upper first conductor layer 21a includes an upper first conductor circuit 212a and an upper first via conductor land 211a. In this way, the upper first buildup layer B1a is formed. Also, as shown in FIG. 4C, a lower first conductor layer 21b is formed on the lower first insulating layer 11b, and the lower conductor layer 20b and the lower first conductor layer 21b are formed in the via hole 311b. A lower first via conductor 31b is formed. The lower first conductor layer 21b includes a lower first conductor circuit 212b and a lower first via conductor land 211b. In this way, the lower first buildup layer B1b is formed.

4D, an upper second buildup layer B2a is formed on the upper first buildup layer B1a, and a lower second buildup is formed on the lower first buildup layer B1b. The up layer B2b is formed. The manufacturing method is similar to the method described with reference to FIGS. 4A, 4B, and 4C. However, the thermal expansion coefficient of the lower second insulating layer 12b belonging to the lower second buildup layer B2b is smaller than the thermal expansion coefficient of the lower first insulating layer 11b. For example, the amount of inorganic particles contained in the lower first insulating layer 11b is 30 vol%, and the amount of inorganic particles contained in the lower second insulating layer 12b is 45 vol%.
The thermal expansion coefficient of the upper second insulating layer 12a belonging to the upper second buildup layer B2a, the thermal expansion coefficient of the upper first insulating layer 11a, and the thermal expansion coefficient of the lower first insulating layer 11b are the same. May be. In this case, the thermal expansion coefficient of the upper buildup layer Ba tends to be larger than the thermal expansion coefficient of the lower buildup layer Bb. When the lower buildup layer Bb has laminated coils, the conductor volume differs between the upper and lower buildup layers, but the warpage of the printed wiring board is reduced due to the difference in the conductor volume and the difference in thermal expansion coefficient. . The thermal expansion coefficient of the upper second insulating layer 12a and the thermal expansion coefficient of the lower second insulating layer 12b are the same, and the thermal expansion coefficient of the upper first insulating layer 11a and the lower first insulating layer 11b are the same. May have the same thermal expansion coefficient. Since the balance between the upper and lower buildup layers is good, the warp of the printed wiring board is reduced.

  Further, as shown in FIG. 7C, the lower second via conductor 32b is formed on the land of the lower first via conductor 31b. The central axis of the lower second via conductor 32b is shifted in the outer peripheral direction of the printed wiring board with respect to the central axis of the lower first via conductor 31b. The shift amount δ12 is about 40 μm. As shown in FIG. 4D, the upper second via conductor 32a is formed on the land 211a of the upper first via conductor 31a. The central axis of the upper second via conductor 32a coincides with the central axis of the upper first via conductor 31a.

  Subsequently, as shown in FIG. 4E, an upper third buildup layer B3a is formed on the upper second buildup layer B2a, and a lower third buildup layer B2b is formed. The up layer B3b is formed. The manufacturing method is similar to the method described with reference to FIGS. 4A, 4B, and 4C. However, the thermal expansion coefficient of the lower third insulating layer 13b belonging to the lower third buildup layer B3b is substantially the same as the thermal expansion coefficient of the lower first insulating layer 11b. For example, the amount of inorganic particles contained in the lower third insulating layer 13b is 30 vol%. In this way, the upper and lower buildup layers B3a and B3b are completed.

  The thermal expansion coefficient of the upper third insulating layer 13a, the thermal expansion coefficient of the upper second insulating layer 12a, the thermal expansion coefficient of the upper first insulating layer 11a, the thermal expansion coefficient of the lower first insulating layer 11b, and the lower The thermal expansion coefficient of the third insulating layer 13b on the side may be the same. In this case, the thermal expansion coefficient of the upper buildup layer Ba tends to be larger than the thermal expansion coefficient of the lower buildup layer Bb. When the lower buildup layer Bb has a laminated coil, the conductor volume differs between the upper and lower buildup layers, but the warpage of the printed wiring board is reduced due to the difference in the conductor volume and the difference in thermal expansion coefficient. . The thermal expansion coefficient of the upper second insulating layer 12a and the thermal expansion coefficient of the lower second insulating layer 12b are the same, and the thermal expansion coefficient of the upper third insulating layer 13a and the upper first insulating layer 11a The thermal expansion coefficient, the thermal expansion coefficient of the lower third insulating layer 13b, and the thermal expansion coefficient of the lower first insulating layer 11b may be the same. Since the balance between the upper and lower buildup layers is good, the warp of the printed wiring board is reduced.

  Further, as shown in FIG. 7B, the lower third via conductor 33b is formed on the land 221b of the lower second via conductor 32b. The central axis of the lower third via conductor 33b is shifted in the outer peripheral direction of the printed wiring board with respect to the central axis of the lower second via conductor 32b. The shift amount δ23 is about 50 μm. As shown in FIG. 4E, the upper third via conductor 33a is formed on the land 221a of the upper second via conductor 32a. The central axis of the upper third via conductor 33a coincides with the central axis of the upper second via conductor 32a. Controlling the position of each via conductor is achieved, for example, by setting the position where the via conductor opening is formed in the laser processing machine.

  As shown in FIG. 4F, a stepped stack via structure S2 is formed in the lower buildup layer Bb, and a concentric stack via structure S1 is formed in the upper buildup layer Ba. A stepped stacked via structure may be formed in the upper buildup layer. The staircase type stacked via structure is inclined with respect to the normal direction of the main surface of the printed wiring board. When the staircase type stacked via structure includes various shift amounts δ, as shown in FIG. 8, the stacked via structure may appear to be bent or have a plurality of inclinations.

Next, as shown in FIG. 4F, an upper solder resist layer 5a having openings 51a and 52a exposing the upper third conductor layer 23a is formed on the upper buildup layer, and the lower buildup layer is formed. A lower solder resist layer 5b having openings 51b and 52b exposing the lower third conductor layer 23b is formed thereon. In this way, the printed wiring board is completed.
The upper third conductor layer 23a exposed through the opening of the upper solder resist layer is a C4 pad. The lower third conductor layer 23b exposed by the opening of the lower solder resist layer is a BGA pad. Solder bumps (C4 bumps) 61a and 62a are formed on the C4 pad, and solder bumps (BGA bumps) 61b and 62b are formed on the BGA pad. The IC chip is mounted on the printed wiring board via the C4 bump, and the printed wiring board is mounted on the motherboard via the BGA bump.

  FIG. 2 shows a printed wiring board according to another embodiment. In a printed wiring board according to another embodiment, the first and third buildup layers have a plurality of insulating layers and a plurality of conductor layers, which are alternately stacked. In FIG. 2, the upper first buildup layer B1a has two insulating layers 111a and 112a and two conductive layers 2101a and 2102a, and the upper third buildup layer B3a has two insulating layers. 131a, 132a and two conductor layers 2301a and 2302a, the lower first buildup layer B1b has two insulating layers 111b and 112b and two conductor layers 2101b and 2102b, and the lower side The third buildup layer B3b includes two insulating layers 131b and 132b and two conductor layers 2301b and 2302b. As shown in FIG. 2, the upper and lower buildup layers have a step-type stack via structure.

  The upper and lower second buildup layers can have a plurality of insulating layers and conductor layers. When the buildup layer includes 10 or more insulating layers, the number of insulating layers in the second buildup layer is preferably plural. The thermal expansion coefficient of the printed wiring board is reduced. Stress applied to the stacked via structure is reduced.

1000 Printed wiring board 10 Core insulating layer 100 Double-sided copper-clad laminate 101 Through-hole conductors 102a and 102b Metal foil 103 Through-hole 104 Core substrate 20a and 20b Core substrate conductor layers 201a, 211a, 2111a, 2112a, 221a, 231a and 2311a , 2312a Land 201b, 211b, 2111b, 2112b, 221b, 231b, 2311b, 2312b Land 202a, 212a, 232a, 202b, 212b, 232b Conductor circuit 11a, 111a, 112a, 12a, 13a, 131a, 132a Insulating layer (interlayer resin) Insulation layer)
11b, 111b, 112b, 12b, 13b, 131b, 132b Insulating layer (interlayer resin insulating layer)
311a, 311b Via hole 21a, 2101a, 2102a, 22a, 23a, 2301a, 2302a Conductor layer 21b, 2101b, 2102b, 22b, 23b, 2301b, 2302b Conductor layer 31a, 311a, 312a, 32a, 33a, 331a, 332a Via conductor 31b 311b, 312b, 32b, 33b, 331b, 332b Via conductor Ba, B1a, B2a, B3a, Bb, B1b, B2b, B3b Build-up layer F1 First surface F2 Second surface S1, S2 Stack via structure LV, UV via Conductor S111 Outer circumference S112 of via conductor S11 Top opening S123 of via conductor S11 Bottom opening 400 of via conductor S12 Multilayer inductor 401, 402, 403 Coil pattern 411, 412, 413 Via conduction of inductor Body 5a, 5b Solder resist layer 51a, 52a, 51b, 52b Solder resist layer opening 61a, 62a, 61b, 62b Solder bump δ, δ12, δ23, δ34, δ45 Shift amount

Claims (6)

A first build having a first insulating layer, a first conductor layer formed on the first insulating layer, and a first via conductor penetrating the first insulating layer and connected to the first conductor layer Up layer,
A second insulating layer formed on the first buildup layer; a second conductor layer formed on the second insulating layer; and the first conductor layer and the second conductor layer penetrating the second insulating layer. A second buildup layer having a second via conductor electrically connecting the two conductor layers;
A third insulating layer formed on the second buildup layer; a third conductor layer formed on the third insulating layer; the third conductor layer penetrating through the third insulating layer; A printed wiring board having a third buildup layer having a third via conductor electrically connecting the second conductor layer,
The thermal expansion coefficient of the second insulating layer is smaller than the thermal expansion coefficient of the first insulating layer and the thermal expansion coefficient of the third insulating layer,
The first via conductor, the second via conductor, and the third via conductor are stacked like a step, and the first via conductor, the second via conductor, and the third via conductor form a stacked via structure. Is formed.   2. The printed wiring board according to claim 1, wherein a central axis of the second via conductor is positioned in an outer peripheral direction of the printed wiring board from a central axis of the first via conductor, and a central axis of the third via conductor is It is located in the outer peripheral direction of the printed wiring board from the central axis of the second via conductor. The printed wiring board according to claim 1, wherein the first build-up layer includes a plurality of the first insulating layer, the first conductor layer, and the first via conductor, and the first insulating layer and the The first conductor layers are alternately stacked, and the first via conductors are formed on the first insulating layers,
The third build-up layer includes a plurality of the third insulating layer, the third conductor layer, and the third via conductor, and the third insulating layer and the third conductor layer are alternately stacked, A third via conductor is formed in each of the third insulating layers;
The stacked via structure is formed by the first via conductor, the second via conductor, and the third via conductor respectively formed in the first insulating layer and the third insulating layer.   4. The printed wiring board according to claim 3, wherein the number of the first insulating layers and the number of the third insulating layers are the same.   2. The printed wiring board according to claim 1, wherein a value of a coefficient of thermal expansion of the second insulating layer is 70% or less of a coefficient of thermal expansion of the first insulating layer, and a heat of the third insulating layer. 70% or less of the expansion coefficient.   The printed wiring board according to claim 1, wherein a buildup layer is formed by the first buildup layer, the second buildup layer, and the third buildup layer, and the buildup layer includes a plurality of coils. A multilayer inductor formed of a via conductor connecting the pattern and the coil pattern is included.

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