JP2010246011A - A/d converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an A/D converter that suppresses a change in inclination (resolution) of I/O characteristics and has origin-based I/O characteristics. <P>SOLUTION: Pulse delay circuits 11, 12, 13 connect a plurality of stages of delay units for delaying pulse signals with delay times corresponding to analog voltages. Detection circuits 23, 22 detect the first number of stages and the second number of stages of delay units in the pulse delay circuits 13, 12 through which pulse signals have passed. A timing output circuit 41 outputs a timing signal indicating a timing when a difference between the first number of stages and the second number of stages becomes a predetermined value. A detection circuit 21 detects the third number of stages of delay unit in the pulse delay circuit 11 through which pulse signals have passed. An arithmetic output circuit 31 outputs a difference between the third number of stages detected at the timing indicated by the timing signal and the first number of stages, as digital values corresponding to the analog input voltages. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to an A / D converter that converts an analog input voltage into a digital value using a pulse delay circuit that delays a pulse signal by a delay time corresponding to the magnitude of the analog input voltage.

  2. Description of the Related Art Conventionally, an A / D conversion apparatus that can obtain a high-resolution digital value with a simple configuration is known as shown in FIG. 9 (see Patent Document 1). In the A / D converter 400 shown in FIG. 9, the pulse delay circuit 11 has a configuration in which a plurality of delay units (NAND1, BUF1,..., BUF15) each consisting of various gate circuits are connected in a ring shape. ing. An analog input voltage Vin to be A / D converted is supplied as a power supply voltage for each delay unit.

  When a sampling pulse (SP) is input to the pulse delay circuit 11, the SP sequentially passes through each delay unit with a delay time corresponding to the power supply voltage, and circulates in the pulse delay circuit 11. The number of stages of delay units through which the SP passes is determined by the delay time of each delay unit, that is, the analog input voltage Vin supplied as the power supply voltage. The pulse passage stage number detection circuit 21 detects the number of passage stages (and the number of turns).

  The arithmetic output circuit 31 takes in the detection result of the number of passage stages by the pulse passage stage number detection circuit 21 at the timing when the latch pulse (LP) is inputted after the sampling time has elapsed after the SP input is started. Further, the arithmetic output circuit 31 outputs a value obtained by encoding the number of passing stages as a digital value (out) after A / D conversion.

  In the A / D converter 400 described above, when the analog input voltage Vin is in a predetermined input voltage range (Vmin to Vmax), the relationship between Vin and out is linear as indicated by the solid line L10 in FIG.

JP-A-5-259907

  However, in the A / D converter 400 described above, the delay time of the delay unit varies depending on environmental factors such as temperature, element type, element variation, and the like, as indicated by the broken line L11 in FIG. There is a problem that the slope of the characteristic (= resolution) varies greatly and a stable result cannot be obtained.

  More specifically, when the input / output characteristics are represented by a solid line L10 in FIG. 10, the range that can be taken by the A / D conversion result for a predetermined voltage range (Vmin to Vmax) is Δout0. On the other hand, when the input / output characteristics are represented by the broken line L11 in FIG. 10, the range that the A / D conversion result can take for a predetermined voltage range (Vmin to Vmax) is Δout1. However, the sampling time is the same. Since the slopes of the solid line L10 and the broken line L11 in Vmin to Vmax are different, as shown in FIG. 10, Δout0 and Δout1 which are A / D conversion result ranges for the same voltage range (Vmin to Vmax) are different. For this reason, a stable A / D conversion result cannot be obtained.

  Further, as indicated by the broken line L12 in FIG. 10, even if the linear portion of the input / output characteristics is extended to the position of Vin = 0 [V], the output out does not become 0 [stage], and the intercept b remains. That is, the relationship between Vin and out is not proportional but is represented by a linear function. For this reason, in the above A / D conversion apparatus, if the result of A / D conversion is directly used for calculation, the intercept b may be an error factor.

For example, when the input / output characteristics are expressed by a linear function out = Vin × a + b, the ratio of the output out2 when Vin is 2 [V] and the output out1 when Vin is 1 [V] is calculated. Then, the following equation (1) is obtained.
out2 / out1 = (2a + b) / (a + b) ≠ 2 (1)
That is, the ratio before A / D conversion (= 2) does not match the ratio after A / D conversion. In addition, the intercept b largely fluctuates due to environmental factors such as temperature, which causes deterioration in accuracy.

  The present invention has been made in view of the above-described problem, and suppresses fluctuations in the slope (resolution) of the input / output characteristics, and at the same time the input / output characteristics based on the origin (the voltage to be subjected to A / D conversion is 0). An object of the present invention is to provide an A / D converter having a characteristic that the output sometimes becomes zero.

  The present invention has been made to solve the above-described problem, and is an A / D converter that converts an analog input voltage into a digital value. A first pulse signal is input at a first timing. A first pulse delay circuit in which a plurality of delay units for delaying the first pulse signal with a delay time corresponding to the magnitude of one analog voltage are connected; and the first pulse signal is the first pulse delay A first pulse passing stage number detection circuit that detects a first stage number that has passed through a delay unit in the circuit; and a second pulse signal that is input at a second timing that is the same as the first timing; A second pulse delay circuit in which a plurality of delay units for delaying the second pulse signal with a delay time corresponding to the magnitude of the second analog voltage different from the second analog voltage is connected, and the second pulse signal Above And a timing at which a difference between the first stage number and the second stage number becomes a predetermined stage number, and a second pulse passing stage number detection circuit that detects the second stage number that has passed through the delay unit in the two pulse delay circuits. A timing output circuit that outputs a timing signal indicating the level, a level shift circuit that outputs a level shift voltage obtained by shifting the voltage level of the analog input voltage by the level of the first analog voltage, the first timing, and the A third pulse signal is input at the same timing as the second timing, and a third stage in which delay units for delaying the third pulse signal by a delay time corresponding to the magnitude of the level shift voltage are connected in a third stage. A pulse delay circuit and a third pulse for detecting a third stage number of the third pulse signal having passed through a delay unit in the third pulse delay circuit; An information on the difference between the third stage number detected at the timing indicated by the timing signal and the third stage number and the first stage number is calculated, and the result of the calculation corresponds to the analog input voltage. And an output circuit that outputs a digital value.

  In addition, the A / D conversion device of the present invention further includes a memory circuit that stores a sampling time corresponding to the timing indicated by the timing signal, and the third pulse delay circuit further includes the first timing, The fourth pulse signal is input at the second timing and the fourth timing after the third timing, and the fourth pulse signal is further input to the third pulse passage stage number detection circuit. At a timing when the sampling time stored in the memory circuit has elapsed, a fourth stage number at which the fourth pulse signal has passed through a delay unit in the third pulse delay circuit is detected, and the output The circuit further calculates information related to the difference between the fourth stage number and the first stage number, and the result of the calculation is calculated as the digital input voltage corresponding to the analog input voltage. And outputs it as a value.

  The A / D converter according to the present invention further includes a control unit that stops the operation of the first pulse delay circuit or / and the second pulse delay circuit after the sampling time is stored in the memory circuit. Also have.

  The A / D converter according to the present invention shifts the level at a timing when the difference between the first stage number corresponding to the first analog voltage and the second stage number corresponding to the second analog voltage becomes a predetermined number of stages. A third stage number corresponding to the voltage is detected. As described above, since the third stage number is detected under the condition that the A / D conversion result with respect to the predetermined voltage range is constant, according to the A / D conversion device of the present invention, the slope (resolution) of the input / output characteristics is reduced. Variation can be suppressed.

  The A / D converter according to the present invention calculates information regarding the difference between the first stage number and the third stage number, and outputs the result of the calculation as a digital value corresponding to the analog input voltage. Since the difference between the first stage number and the third stage number is 0 when the analog input voltage is the first analog voltage, according to the A / D converter of the present invention, the input / output characteristics are used as the origin reference. be able to.

1 is a block diagram showing a configuration of an A / D conversion device according to a first embodiment of the present invention. It is a flowchart which shows the process sequence of the A / D converter by the 1st Embodiment of this invention. It is a reference figure which shows the input / output characteristic of the A / D converter by the 1st Embodiment of this invention. It is a block diagram which shows the structure of the A / D converter by the 2nd Embodiment of this invention. It is a flowchart which shows the process sequence of the A / D converter by the 2nd Embodiment of this invention. It is a timing chart which shows the waveform of the sampling pulse and latch pulse in the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the A / D converter by the 3rd Embodiment of this invention. It is a flowchart which shows the process sequence of the A / D converter by the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the conventional A / D converter. It is a reference figure which shows the input / output characteristic of the conventional A / D converter.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
First, a first embodiment of the present invention will be described. FIG. 1 shows the configuration of the A / D converter according to the present embodiment. In FIG. 1, an A / D converter 100 includes a pulse delay circuit 11, 12, 13, a pulse passage stage number detection circuit 21, 22, 23, an arithmetic output circuit 31, a timing output circuit 41, and a level shift circuit 51. Consists of

  The pulse delay circuit 11 has a configuration in which a plurality of delay units that delay the sampling pulse (SP) with a delay time corresponding to the magnitude of Vin (analog input voltage) + Vmin (minimum value of the voltage range that Vin can take) are connected. Have. The pulse delay circuit 12 has a configuration in which a plurality of delay units that delay the SP by a delay time corresponding to the maximum value (Vmax) of the voltage range that Vin can take are connected. The pulse delay circuit 13 has a configuration in which a plurality of delay units that delay the SP with a delay time corresponding to the minimum value (Vmin) of the voltage range that Vin can take are connected.

  The pulse passage stage number detection circuit 21 detects the number of stages that the SP has passed through the delay unit in the pulse delay circuit 11. The pulse passage stage number detection circuit 22 detects the number of stages that the SP has passed through the delay unit in the pulse delay circuit 12. The pulse passage stage number detection circuit 23 detects the number of stages that the SP has passed through the delay unit in the pulse delay circuit 13.

  The timing output circuit 41 generates a latch pulse (LP2) based on the output signals of the pulse passage stage number detection circuit 22 and the pulse passage stage number detection circuit 23 and outputs the latch pulse (LP2) to the arithmetic output circuit 31. The arithmetic output circuit 31 latches the output signals of the pulse passage stage number detection circuit 21 and the pulse passage stage number detection circuit 23 based on LP2, calculates each output signal, and outputs a digital value (out) corresponding to Vin. To do. The level shift circuit 51 outputs a voltage (Vin + Vmin) obtained by adding Vin and Vmin.

  Hereinafter, a detailed configuration of the pulse delay circuit 11 will be described. The pulse delay circuit 11 is a ring delay line (RDL) that has a configuration in which 16 stages of delay units that give an input signal a delay amount corresponding to a power supply voltage are connected in a ring shape, and this configuration circulates an SP. . The first-stage delay unit NAND has two input terminals, SP is input to one input terminal, and the output of the 16th-stage delay unit BUF15 is input to the other input terminal. The delay unit NAND inverts the logic of the output of the 16th stage delay unit BUF15 whenever the pulse delay circuit 11 is operating.

  Each delay unit from the second-stage delay unit BUF1 to the sixteenth-stage delay unit BUF15 has a gate circuit that outputs the value input to the input terminal to the output terminal (for example, a buffer in which two stages of NOT gates are connected). Circuit). Vin + Vmin is applied as a power supply voltage to each delay unit (NAND1, BUF1,..., BUF15). Each delay unit delays the SP input from the preceding delay unit by a delay time corresponding to the voltage level of the power supply voltage (Vin + Vmin) and outputs the delayed SP to the subsequent delay unit. Each delay unit connected in a ring shape operates in the same manner, and the SP is sequentially transmitted from the preceding stage to the subsequent delay unit, so that the SP circulates in the pulse delay circuit 11.

  The process in which the SP circulates in the pulse delay circuit 11 will be specifically described as follows. When SP is not input to one input terminal of the first-stage delay unit NAND (when SP is at “L” level), the level of the output terminal of the delay unit NAND does not depend on the input of the other input terminal, Becomes “H” level. The level of the output terminal of each delay unit after the second-stage delay unit BUF1 also becomes “H” level.

  Subsequently, SP is input to one input terminal of the first-stage delay unit NAND (SP becomes “H” level). Since the level of the other input terminal of the delay unit NAND is “H” level by the SP output from the delay unit BUF15 in the final stage, the level of the output terminal of the delay unit NAND is the power supply voltage (Vin + Vmin). It switches to the “L” level with a delay time corresponding to the voltage level. The level of the output terminal of each delay unit after the second-stage delay unit BUF1 is also sequentially switched to the “L” level with a delay time corresponding to the voltage level of the power supply voltage (Vin + Vmin).

  When the level of the output terminal of the last-stage delay unit BUF15 is switched to the “L” level, the level of the output terminal of the first-stage delay unit NAND is “H” over a delay time corresponding to the voltage level of the power supply voltage (Vin + Vmin). “Switch to level. The level of the output terminal of each delay unit after the second-stage delay unit BUF1 is also sequentially switched to the “H” level with a delay time corresponding to the voltage level of the power supply voltage (Vin + Vmin).

  When the level of the output terminal of the final delay unit BUF15 is switched to the “H” level, the level of the output terminal is switched to the “L” level in order from the first delay unit NAND in the next round. Thereafter, while the SP is being input, an operation in which the level of the output terminal is sequentially switched from the first delay unit NAND to the opposite level every time the level of the output terminal of the delay unit BUF15 of the final stage is switched is repeated. As a result, the SP continues to circulate in the pulse delay circuit 11.

  The time required from when the level of the input terminal of each delay unit is switched to when the level of the output terminal is switched is a delay time corresponding to Vin + Vmin which is the power supply voltage of each delay unit. For this reason, the number of stages of the delay unit through which the SP passes within a predetermined time depends on the analog voltage (Vin + Vmin).

  The pulse passage stage number detection circuit 21 is a circuit that detects the number of stages that the SP has passed through the delay unit in the pulse delay circuit 11. An output signal of each delay unit in the pulse delay circuit 12 is input to the pulse passage stage number detection circuit 21.

  The pulse passing stage number detection circuit 21 is the number of times that the level of the output terminal of the 16th delay unit BUF15 in the pulse delay circuit 11 is switched from "H" level to "L" level or from "L" level to "H" level. Is output as an 8-bit count value. The pulse passing stage number detection circuit 21 outputs 16-bit data representing a state in which the output terminal level of each of the 16 delay units of the pulse delay circuit 11 is “H” level or “L” level. To do.

  The above 8-bit count value and 16-bit data output from the pulse passage stage number detection circuit 21 indicate how many rounds the SP has traveled through the pulse delay circuit 11 and to which delay unit has been advanced. . For example, when the count value is 4 times, the output of the delay unit BUF4 at the fifth stage is “L” level, and the output of the delay unit BUF5 at the sixth stage is “H” level, the SP sets the delay unit. The number of stages passed is 16 stages × 4 times + 5 stages = 69 stages.

  As described above, the pulse passing stage number detection circuit 21 uses the 8-bit + 16-bit digital signal to indicate the number of stages that the SP has passed through the pulse delay circuit 11 constituted by the delay unit to which the analog voltage (Vin + Vmin) is applied as the power supply voltage. Output.

  The configurations of the pulse delay circuit 12 and the pulse passage stage number detection circuit 22 are the same as those of the pulse delay circuit 11 and the pulse passage stage number detection circuit 21, respectively. The pulse passing stage number detection circuit 22 outputs the number of stages that the SP has passed through the pulse delay circuit 12 constituted by a delay unit to which the analog voltage (Vmax) is applied as a power supply voltage as a digital signal of 8 bits + 16 bits.

  The configurations of the pulse delay circuit 13 and the pulse passage stage number detection circuit 23 are the same as those of the pulse delay circuit 11 and the pulse passage stage number detection circuit 21, respectively. The pulse passing stage number detection circuit 23 outputs the number of stages that the SP has passed through the pulse delay circuit 13 constituted by a delay unit to which an analog voltage (Vmin) is applied as a power supply voltage, as a digital signal of 8 bits + 16 bits.

  Next, the processing procedure of the A / D conversion apparatus 100 will be described with reference to FIG. First, SP is simultaneously input to the pulse delay circuits 11, 12, and 13 (the SP level is switched from the “L” level to the “H” level) (step S1). The SP has different delay times in the pulse delay circuits 11, 12, and 13 (in the pulse delay circuit 11, a delay time based on Vin + Vmin, in the pulse delay circuit 12, a delay time based on Vmax, and in the pulse delay circuit 13 Vmin. Is started at a delay time based on (step S2). The pulse passage stage number detection circuits 21, 22, and 23 detect the number of stages that the SP passes through each delay unit (step S3).

Here, the number of stages through which the SP passes through the delay unit in the pulse delay circuit 12 is Cmax, the number of stages through which the SP passes through the delay unit in the pulse delay circuit 13 is Cmin, and a predetermined predetermined number of stages is Δout. . The timing output circuit 41 outputs the latch pulse (LP2) (at the level of LP2) at the timing when the difference between Cmax and Cmin exceeds Δout, that is, the timing (Step S4) that satisfies the condition of the following expression (2). ("L" level is switched to "H" level) (step S5).
Δout ≧ Cmax−Cmin (2)

  The arithmetic output circuit 31 latches the number of stages (count value and output value of each delay unit) detected by the pulse passage stage number detection circuit 21 and the pulse passage stage number detection circuit 23 at the timing when LP2 is input (step S6). The difference in the number of stages is encoded to 12 bits and output as the final A / D conversion result (out) (step S7).

For example, the output (Clin) of the pulse passage stage number detection circuit 21 becomes 1000 stages (the output value of each delay unit of 1 to 16 stages = “0000000011111111”, the count value = “00111110”). When the output (Clmin) becomes 100 stages (output value of each delay unit of 1 to 16 stages = “000011111111111”, count value = “00000110”), the output out is expressed by the following equation (3).
out = Clin−Clmin = 900 stages (decimal number) = “001110000001” (binary number) (3)
That is, the arithmetic output circuit 31 outputs a 12-bit digital signal “001110000001”.

  In A / D conversion device 100 operating in this way, the difference between Vmax and Vmin (Vmax−Vmin) is constant, and the predetermined number of stages Δout is constant. Also, sampling of Vmax, Vmin, Vin + Vmin is started simultaneously, and at the timing when the number of stages corresponding to the difference between Vmax−Vmin becomes Δout, the number of stages corresponding to Vin + Vmin and Vmin is latched respectively, and the difference between these stages (Vin The corresponding number of stages) is output as the A / D conversion result (out). Therefore, when the input / output characteristic of the output out with respect to the analog input voltage Vin is linear, the slope (= resolution) of the input / output characteristic is constant.

  For example, in the above-described conventional A / D converter 400 (FIG. 9), the input / output characteristic at the temperature T1 is the straight line L10 in FIG. 10, and the input / output characteristic at the temperature T2 is the straight line L11 in FIG. To do. When the A / D converter 100 according to the present embodiment is configured using the pulse delay circuit having the same characteristics as the pulse delay circuit 11 included in the A / D converter 400, regardless of the change in the slope of the input / output characteristics due to the temperature change. , Δout becomes constant (Δout0 = Δout1 in FIG. 10), the A / D converter 100 operates so that the output timing of LP2 at temperature T2 is later than the output timing of LP2 at temperature T1. To do. For this reason, the slopes of the input / output characteristics are the same regardless of whether the temperature is T1 or T2.

  As described below, the input / output characteristics of the A / D converter 100 according to the present embodiment are based on the origin (the output is 0 when the input is 0). FIG. 3 shows the input / output characteristics of the A / D converter 100.

  When Vin is 0, the power supply voltage (Vin + Vmin) applied to each delay unit in the pulse delay circuit 11 is equal to the power supply voltage (Vmin) applied to each delay unit in the pulse delay circuit 13. For this reason, the number of stages detected by the pulse passage stage number detection circuit 21 and the pulse passage stage number detection circuit 23 becomes equal, and the A / D conversion result (out), which is the difference between the number of stages, becomes zero. Therefore, as shown in FIG. 3, the input / output characteristics (curve L1) are based on the origin (the output is 0 when the input is 0).

  As described above, according to the present embodiment, fluctuations in the slope (resolution) of the input / output characteristics can be suppressed regardless of temperature fluctuations and fluctuations in the characteristics of the transistors constituting the pulse delay circuit. Further, the input / output characteristics of the A / D converter can be used as the origin reference, and the intercept does not become an error factor even if the A / D conversion result is directly used for the calculation, so that the calculation accuracy can be improved.

  Further, according to the present embodiment, SP is simultaneously input to the pulse delay circuits 11, 12, and 13, and the sampling of Vmax and Vmin for determining the output timing of LP2 and the sampling of Vin + Vmin are performed in parallel. As a result, the result of suppressing the fluctuation of the slope (resolution) of the input / output characteristics can be obtained by one sampling, and thus the A / D conversion result can be obtained at high speed. For example, instead of determining the timing (LP2 output timing) for ending Vin + Vmin sampling in real time from the sampling results of Vmax and Vmin as in the present embodiment, sampling of Vmax and Vmin is performed for a certain period of time at the first sampling. (T1) is performed, and the sampling time (Ts) of the next Vin + Vmin is determined from the result, the sampling time of Vin + Vmin is determined by two or more samplings, and the fluctuation of the slope (resolution) of the input / output characteristics is suppressed. A method is also conceivable. To explain with a specific example, when the difference between the sampling result of Vmax and the sampling result of Vmin is twice as large as the predetermined value in the sampling at the first fixed time T1, in the second sampling, By applying feedback so that the sampling time of Vin + Vmin is half of T1 (Ts = T / 2), sampling of Vin + Vmin is performed at a sampling time such that the difference between the sampling result of Vmax and the sampling result of Vmin approaches a constant value. As a result, it is also possible to suppress fluctuations in the slope (resolution) of the input / output characteristics. However, since the desired result cannot be obtained unless sampling is repeated, it is not possible to realize high speed A / D conversion. According to the present embodiment, it is possible to obtain a desired result in which fluctuations in the slope (resolution) of the input / output characteristics are suppressed by a single sampling, and it is possible to realize high speed A / D conversion.

<Second Embodiment>
Next, a second embodiment of the present invention will be described. FIG. 4 shows the configuration of the A / D converter according to the present embodiment. In FIG. 4, the A / D conversion device 200 includes a pulse delay circuit 11, 12, 13, a pulse passage stage number detection circuit 21, 22, 23, an arithmetic output circuit 31, a timing output circuit 41, and a level shift circuit 51. And a memory circuit 61 and a control circuit 71. The configurations of the pulse delay circuits 11, 12, 13, the pulse passing stage number detection circuits 21, 22, 23, the arithmetic output circuit 31, the timing output circuit 41, and the level shift circuit 51 are the same as those of the A / D converter according to the first embodiment. 100 is the same as each component. However, the timing output circuit 41 outputs the latch pulse LP2 to the arithmetic output circuit 31 and the memory circuit 61.

  The memory circuit 61 stores a sampling time based on SP and LP2 from the timing output circuit 41. This sampling time is the time from when SP is input to the pulse delay circuits 11, 12, and 13 until LP2 is output from the timing output circuit 41. The control circuit 71 controls the pulse delay circuit 12 and the pulse delay circuit 13.

  Next, the processing procedure of the A / D conversion apparatus 200 will be described with reference to FIG. The processing procedure of steps S1 to S5 shown in FIG. 5 is the same as the processing procedure of steps S1 to S5 shown in FIG. In step S3, the arithmetic output circuit 31 stores the number of stages (count value and output value of each delay unit) detected by the pulse passing stage number detection circuit 23.

  When the latch pulse (LP2) is output from the timing output circuit 41 in step S5, the memory circuit 61 determines the time (sampling time) from the timing of step S1 when SP is input to the timing of step S5 when LP2 is input. (Ts: see FIG. 6) is stored (step S8). Subsequently, the control circuit 71 stops the operations of the pulse delay circuit 12 and the pulse delay circuit 13 (step S9).

  On the other hand, the arithmetic output circuit 31 receives the pulse passing stage number detection circuit 21 and the number of pulse passing stages at the timing when the LP2 is input from the timing output circuit 41 (the timing at which the LP2 level is switched from the “L” level to the “H” level). The number of stages (count value and output value of each delay unit) detected by the detection circuit 23 is latched (step S6), and the difference between the number of stages is encoded into 12 bits and output as the final A / D conversion result (out). (Step S7).

  One A / D conversion is completed by the processing up to step S7. The processing can be completed with this, but in the present embodiment, it is possible to efficiently perform continuous A / D conversion processing. That is, when the continuous process is not performed (step S10), the process is completed, but when the continuous process is performed (step S10), the processes of steps S11 to S17 are performed. Hereinafter, the continuous processing (steps S11 to S17) will be described.

  When performing continuous processing, the value of Vin is first changed (step S11). However, this step is not necessary when the same input signal is A / D converted a plurality of times by oversampling or the like.

  Subsequently, when the SP is input again (step S12), the SP starts the circulation of the delay unit in the pulse delay circuit 11 with the delay time based on Vin + Vmin (step S13). The memory circuit 61 outputs a latch pulse (LP2) after the sampling time Ts stored in step S8 has elapsed since the SP was input again in step S12 (step S14). The arithmetic output circuit 31 receives the LP2 from the memory circuit 61 (the LP2 level is switched from the “L” level to the “H” level) at the timing when the pulse passing stage number detection circuit 21 detects the number of counts (count value and The output value of each delay unit is latched (step S15). Further, the arithmetic output circuit 31 encodes the difference between the number of stages detected by the pulse passage stage number detection circuit 21 and the number of stages detected by the pulse passage stage number detection circuit 21 in step S3 into 12 bits and obtains a final A / D conversion result. (Out) is output (step S16).

  Thereafter, when the continuous process is repeated, the processes of steps S11 to S16 are repeated (step S17).

  Also in the A / D conversion device 200 operating in this way, the slope of the input / output characteristics can be made constant and the input / output characteristics can be used as the origin reference. Therefore, according to this embodiment, a stable A / D conversion result can be obtained, and the calculation accuracy can be improved.

  Also in this embodiment, as in the first embodiment described above, SP is simultaneously input to the pulse delay circuits 11, 12 and 13, and sampling of Vmax and Vmin for determining the output timing of LP2 is performed. Since sampling of Vin + Vmin is performed in parallel, the first A / D conversion result can be obtained at high speed.

  Further, when A / D conversion is repeated continuously, the pulse delay circuits 12 and 13 can be stopped by storing the output timing of LP2 in the memory circuit 61. Therefore, power consumption can be reduced. Note that only one of the pulse delay circuits 12 and 13 may be stopped, and in this case, power consumption can be reduced.

<Third Embodiment>
Next, a third embodiment of the present invention will be described. FIG. 7 shows the configuration of the A / D converter according to the present embodiment. In FIG. 7, an A / D converter 300 includes a pulse delay circuit 12, 14, a pulse passage stage number detection circuit 22, 24, an arithmetic output circuit 31, a timing output circuit 41, a level shift circuit 51, and a memory circuit. 62, a control circuit 71, and a selector 81. The configurations of the pulse delay circuit 12, the pulse passing stage number detection circuit 22, the arithmetic output circuit 31, the timing output circuit 41, the level shift circuit 51, and the control circuit 71 are respectively included in the A / D converter 200 according to the second embodiment. Same as the configuration.

  The configurations of the pulse delay circuit 14 and the pulse passage stage number detection circuit 24 are the same as those of the pulse delay circuit 11 and the pulse passage stage number detection circuit 21 according to the first embodiment, respectively. Further, the pulse passing stage number detection circuit 24 outputs, as an 8-bit + 16-bit digital signal, the number of stages that the SP has passed through the pulse delay circuit 14 configured by a delay unit to which the output voltage of the selector 81 is applied as a power supply voltage. . The selector 81 can switch the voltage to be output, and outputs either Vin or Vin + Vmin.

  The memory circuit 62 stores the sampling time based on SP and LP2 from the timing output circuit 41, and stores the number of stages (count value and output value of each delay unit) detected by the pulse passing stage number detection circuit 24.

  Next, the processing procedure of the A / D conversion apparatus 300 will be described with reference to FIG. First, the output of the selector 81 is switched to Vmin (step S0). Subsequently, the same processing as that in steps S1 to S6 shown in FIG. 5 is performed. After the timing output circuit 41 outputs LP2 in step S6, the memory circuit 62 latches the number of stages (count value and output value of each delay unit) detected by the pulse passing stage number detection circuit 24 at the timing when LP2 is input. In addition, the sampling time Ts is stored (step S18). Subsequently, the control circuit 71 stops the operation of the pulse delay circuit 12 (step S19).

  Subsequently, the output of the selector 81 is switched to Vin + Vmin (step S20). Thereafter, SP is input again, and A / D conversion based on Vin + Vmin is performed (steps S12 to S16). The process of steps S12 to S16 shown in FIG. 8 is the same as the process of steps S12 to S16 shown in FIG. In step S16, the arithmetic output circuit 31 calculates the number of stages detected by the pulse passage stage number detection circuit 24 and the number of stages stored in the memory circuit 62 in step S18 (the number of stages detected by the pulse passage stage number detection circuit 24 in step S3). The difference is encoded to 12 bits and output as the final A / D conversion result (out).

  When repeating the continuous processing (step S17), the value of Vin is changed (step S21), and the processing from steps S12 to S17 is repeated.

  Also in the A / D conversion device 200 operating in this way, the slope of the input / output characteristics can be made constant and the input / output characteristics can be used as the origin reference. Therefore, according to this embodiment, a stable A / D conversion result can be obtained, and the calculation accuracy can be improved.

  Further, when the A / D conversion is continuously repeated, the pulse delay circuit 12 can be stopped by storing the output timing of LP2 in the memory circuit 62. Therefore, power consumption can be reduced.

  Further, since sampling based on Vin + Vmin and sampling based on Vmin are performed by the same pulse delay circuit, errors can be reduced. For example, in the A / D conversion device 100 shown in FIG. 1, if the characteristics of the pulse delay circuit 11 and the pulse delay circuit 13 are different and the delays when the same analog voltage is applied are different, the difference between these characteristics is an error. Appears as However, according to this embodiment, since a common pulse delay circuit is used for two samplings, an error due to this characteristic difference does not occur. In addition, the circuit scale can be reduced by sharing the pulse delay circuit and the pulse passing stage number detection circuit used for sampling twice.

  In the present embodiment, the pulse delay circuit 14 in which the pulse delay circuit 11 and the pulse delay circuit 13 are shared is used. However, even when the characteristics of the pulse delay circuit 11 and the pulse delay circuit 12 are different, these are similarly applied. Therefore, the pulse delay circuit 11 and the pulse delay circuit 12 may be shared.

  In the present embodiment, sampling based on Vmax and Vmin needs to be performed in order to detect the sampling time before sampling based on Vin + Vmin. For this reason, the time from when the A / D conversion is started until the A / D conversion result of Vin + Vmin is obtained is slower than in the first and second embodiments. However, the circuit scale is smaller than in the first embodiment and the second embodiment.

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to the above-described embodiments, and includes design changes and the like without departing from the gist of the present invention. . For example, in the above, it is assumed that Vin is included in the voltage range of Vmax to Vmin. However, analog input voltage not included in the voltage range of Vmax to Vmin is defined as the above Vin, and A / D is the same as above. Conversion may be performed. In the above description, the difference between the number of stages corresponding to Vin + Vmin and the number of stages corresponding to Vmin is output as the final A / D conversion result, but the number of stages corresponding to Vin + Vmax and the number of stages corresponding to Vmax are output. The difference may be output as the final A / D conversion result.

  11, 12, 13, 14 ... pulse delay circuit, 21, 22, 23, 24 ... pulse passing stage number detection circuit, 31 ... arithmetic output circuit, 41 ... timing output circuit, 51 ... Level shift circuit 61, 62 ... Memory circuit, 71 ... Control circuit, 81 ... Selector, 100, 200, 300, 400 ... A / D converter

Claims (3)

An A / D converter for converting an analog input voltage into a digital value,
A first pulse delay circuit in which a first pulse signal is input at a first timing and a plurality of delay units for delaying the first pulse signal by a delay time corresponding to the magnitude of the first analog voltage are connected. When,
A first pulse passage stage number detection circuit for detecting a first stage number in which the first pulse signal has passed through a delay unit in the first pulse delay circuit;
A second pulse signal is input at a second timing that is the same as the first timing, and the second pulse signal has a delay time corresponding to the magnitude of a second analog voltage different from the first analog voltage. A second pulse delay circuit in which a plurality of delay units for delaying are connected,
A second pulse passage stage number detection circuit for detecting a second stage number in which the second pulse signal has passed through a delay unit in the second pulse delay circuit;
A timing output circuit that outputs a timing signal indicating a timing at which a difference between the first stage number and the second stage number becomes a predetermined stage number;
A level shift circuit that outputs a level shift voltage obtained by shifting the voltage level of the analog input voltage by the level of the first analog voltage;
A delay unit that receives a third pulse signal at the same timing as the first timing and the second timing, and delays the third pulse signal by a delay time according to the magnitude of the level shift voltage; A third pulse delay circuit connected in multiple stages;
A third pulse passage stage number detection circuit for detecting a third stage number in which the third pulse signal has passed through a delay unit in the third pulse delay circuit;
An output that calculates information about the difference between the third stage number and the first stage number detected at the timing indicated by the timing signal, and outputs the result of the calculation as the digital value corresponding to the analog input voltage Circuit,
An A / D conversion device. A memory circuit for storing a sampling time corresponding to the timing indicated by the timing signal;
The third pulse delay circuit further receives a fourth pulse signal at the first timing, the second timing, and a fourth timing after the third timing,
The third pulse passage stage number detection circuit further receives the third pulse signal at the timing when the sampling time stored in the memory circuit has elapsed after the fourth pulse signal is input. Detecting the fourth stage number that has passed through the delay unit in the pulse delay circuit of
The output circuit further calculates information related to a difference between the fourth stage number and the first stage number, and outputs a result of the calculation as the digital value corresponding to the analog input voltage. A / D converter.   3. The A / D conversion according to claim 2, further comprising a control unit configured to stop the operation of the first pulse delay circuit and / or the second pulse delay circuit after the sampling time is stored in the memory circuit. apparatus.

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