JP2010246010A - A/d converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an A/D converter including origin-based I/O characteristics (when input is 0, its output is 0). <P>SOLUTION: Pulse delay circuits 12, 13 are configured by connecting a plurality of stages of delay units for delaying pulse signals with delay times corresponding to the levels of analog voltages to be input. Detection circuits 22, 23 detect the number of stages of delay units in the pulse delay circuits 12 and 13 through which pulse signals have passed. An operation output circuit unit 41 computes information on a difference between the first number of stages detected by the detection circuit 23 when reference voltages are input to the pulse delay circuit 13 and the second number of stages detected by the detection circuit 22 when a voltage obtained by adding analog input voltages to the reference voltages is input to the pulse delay circuit 12, and outputs the operation results as digital values corresponding to the analog input voltages. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an A / D converter that converts an analog input voltage into a digital value using a pulse delay circuit that delays a pulse signal by a delay time corresponding to the magnitude of the analog input voltage.

  2. Description of the Related Art Conventionally, an A / D conversion apparatus that can obtain a high-resolution digital value with a simple configuration is known as shown in FIG. 7 (see Patent Document 1). In the A / D converter 300 shown in FIG. 7, the pulse delay circuit 11 has a configuration in which a plurality of delay units (NAND1, BUF1,..., BUF15) each consisting of various gate circuits are connected in a ring shape. ing. An analog input voltage Vin to be A / D converted is supplied as a power supply voltage for each delay unit.

  When a sampling pulse (SP) is input to the pulse delay circuit 11, the SP sequentially passes through each delay unit with a delay time corresponding to the power supply voltage, and circulates in the pulse delay circuit 11. The number of stages of delay units through which the SP passes is determined by the delay time of each delay unit, that is, the analog input voltage Vin supplied as the power supply voltage. The pulse passage stage number detection circuit 21 detects the number of passage stages (and the number of turns).

  The arithmetic output circuit unit 31 captures the detection result of the number of passage stages by the pulse passage stage number detection circuit 21 at the timing when the latch pulse (LP) is inputted after the sampling time has elapsed since the SP input was started. Further, the arithmetic output circuit unit 31 outputs a value obtained by encoding the number of passing stages as a digital value (out) after A / D conversion.

  In the A / D conversion device 300 described above, the relationship between the delay time of the delay unit and the power supply voltage cannot be expressed by a linear function. Therefore, as shown in FIG. 8, the input / output characteristic indicating the relationship between the analog input voltage Vin and the digital value (out) as a result of the A / D conversion becomes a curve (curve L10 in FIG. 8).

  On the other hand, Patent Document 2 discloses a method for bringing the input / output characteristics closer to an ideal straight line. In the method disclosed in Patent Document 2, the voltage range that the analog input voltage can take is divided into a plurality of regions, and the input / output characteristics are approximated by a straight line for each region. In FIG. 8, the analog input voltage Vin is in a predetermined input voltage range (Vmin to Vmax), and the input voltage range is divided into two regions.

  Furthermore, in the method disclosed in Patent Document 2, the digital expression after A / D conversion is performed using a conversion equation for converting the coordinate points on the approximate straight line of each region into points on the ideal characteristic (the straight line L11 in FIG. 8). The value is corrected. The input / output characteristics (relationship between Vin and out) of the A / D converter corrected in this way are as follows. When the analog input voltage Vin is within a predetermined input voltage range (Vmin to Vmax), the straight line L12 in FIG. It becomes linear as shown.

JP-A-5-259907 JP 2004-274157 A

  However, as indicated by the broken line L13 in FIG. 9, even if the linear portion of the input / output characteristics is extended to the position of Vin = 0 [V], the output out does not become 0 [stage], and the intercept b remains. That is, the relationship between Vin and out is not proportional but is represented by a linear function. For this reason, in the above A / D conversion apparatus, if the result of A / D conversion is directly used for calculation, the intercept b may be an error factor.

For example, when the input / output characteristics are expressed by a linear function out = Vin × a + b, the ratio of the output out2 when Vin is 2 [V] and the output out1 when Vin is 1 [V] is calculated. Then, the following equation (1) is obtained.
out2 / out1 = (2a + b) / (a + b) ≠ 2 (1)
That is, the ratio before A / D conversion (= 2) does not match the ratio after A / D conversion. In addition, the intercept b largely fluctuates due to environmental factors such as temperature, which causes deterioration in accuracy.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide an A / D conversion device having input / output characteristics based on the origin (characteristics in which the output is also zero when the input is zero). To do.

  The present invention has been made in order to solve the above-described problem, and is an A / D conversion device that converts an analog input voltage into a digital value, and is pulsed with a delay time corresponding to the magnitude of the input analog voltage. A pulse having a pulse delay circuit unit having a pulse delay circuit in which a plurality of delay units for delaying signals are connected, and a pulse passing stage number detecting circuit for detecting the number of stages in which the pulse signal has passed through the delay unit in the pulse delay circuit unit A first stage number detected by the pulse passage stage number detection circuit unit when a reference voltage is input to the pulse delay circuit unit; and the reference stage for the pulse delay circuit unit. When the voltage obtained by adding the analog input voltage to the voltage is input, it is detected by the pulse passage stage number detection circuit unit. That second calculating information related to the difference between the number of stages, the result of the calculation, the arithmetic output circuit unit for outputting as the digital value corresponding to the analog input voltage, an A / D converter having a.

  In the A / D converter according to the present invention, the reference voltage and a voltage obtained by adding the analog input voltage to the reference voltage are sequentially input to the same pulse delay circuit.

  The A / D converter according to the present invention further includes a level shift circuit that outputs a level shift voltage obtained by shifting the voltage level of the analog input voltage by the level of the reference voltage, and the pulse delay circuit unit includes: A first pulse delay circuit in which a plurality of first delay units for delaying a first pulse signal with a delay time corresponding to the magnitude of the reference voltage are connected; and a delay time corresponding to the magnitude of the level shift voltage And a second pulse delay circuit in which a plurality of second delay units for delaying the second pulse signal are connected. The pulse passing stage number detection circuit unit has the first pulse signal as the first pulse signal. A first pulse passing stage number detection circuit for detecting the first stage number that has passed through the delay unit; and the second stage number in which the second pulse signal has passed through the second delay unit. A second pulse passage stage number detection circuit for detecting, and having a.

  In the A / D converter according to the present invention, the first stage number when the reference voltage is input to the pulse delay circuit unit and the voltage obtained by adding the analog input voltage to the reference voltage are input to the pulse delay circuit unit. Information about the difference from the second stage number is calculated, and the result of the calculation is output as a digital value corresponding to the analog input voltage. Since the difference between the first stage number and the second stage number is 0 when the analog input voltage is 0, according to the A / D converter of the present invention, the input / output characteristics can be based on the origin.

1 is a block diagram showing a configuration of an A / D conversion device according to a first embodiment of the present invention. It is a reference figure which shows the input / output characteristic of the A / D converter by the 1st Embodiment of this invention. It is a reference figure which shows the input / output characteristic of the A / D converter by the 1st Embodiment of this invention. It is a block diagram which shows the structure of the A / D converter by the 2nd Embodiment of this invention. It is a flowchart which shows the process sequence of the A / D converter by the 2nd Embodiment of this invention. It is a flowchart which shows the process sequence of the A / D converter by the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the conventional A / D converter. It is a reference figure which shows the input / output characteristic of the conventional A / D converter. It is a reference figure which shows the input / output characteristic of the conventional A / D converter.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
First, a first embodiment of the present invention will be described. FIG. 1 shows the configuration of the A / D converter according to the present embodiment. In FIG. 1, the A / D converter 100 includes a pulse delay circuit unit 1, a pulse passage stage number detection circuit unit 2, an arithmetic output circuit unit 41, and a level shift circuit 51.

  The pulse delay circuit unit 1 includes a pulse delay circuit 12 and a pulse delay circuit 13. The pulse delay circuit 12 has a configuration in which a plurality of delay units that delay the sampling pulse (SP) with a delay time corresponding to the magnitude of Vin (analog input voltage) + Vref (reference voltage) are connected. The pulse delay circuit 13 has a configuration in which a plurality of delay units that delay the SP with a delay time corresponding to the magnitude of Vref are connected.

  The pulse passage stage number detection circuit unit 2 includes a pulse passage stage number detection circuit 22 and a pulse passage stage number detection circuit 23. The pulse passage stage number detection circuit 22 detects the number of stages that the SP has passed through the delay unit in the pulse delay circuit 12. The pulse passage stage number detection circuit 23 detects the number of stages that the SP has passed through the delay unit in the pulse delay circuit 13.

  The arithmetic output circuit unit 41 latches the output signals of the pulse passing stage number detection circuit 22 and the pulse passing stage number detection circuit 23 based on the latch pulse (LP), calculates each output signal, and outputs a digital value corresponding to Vin. (Out) is output. The level shift circuit 51 outputs Vref and a voltage (Vin + Vref) obtained by adding Vin and Vref.

  Hereinafter, the detailed configuration of the pulse delay circuit 12 will be described. The pulse delay circuit 12 is a ring delay line (RDL) that has a configuration in which 16 stages of delay units that give an input signal a delay amount corresponding to the power supply voltage are connected in a ring shape, and this configuration circulates the SP. . The first-stage delay unit NAND has two input terminals, SP is input to one input terminal, and the output of the 16th-stage delay unit BUF15 is input to the other input terminal. The delay unit NAND inverts the logic of the output of the 16th stage delay unit BUF15 whenever the pulse delay circuit 12 is operating.

  Each delay unit from the second-stage delay unit BUF1 to the sixteenth-stage delay unit BUF15 has a gate circuit that outputs the value input to the input terminal to the output terminal (for example, a buffer in which two stages of NOT gates are connected). Circuit). Vin + Vref is applied as a power supply voltage to each delay unit (NAND1, BUF1,..., BUF15). Each delay unit delays the SP input from the preceding delay unit by a delay time corresponding to the voltage level of the power supply voltage (Vin + Vref) and outputs the delayed SP to the subsequent delay unit. Each delay unit connected in a ring shape operates in the same manner, and SP is sequentially transmitted from the preceding stage to the subsequent delay unit, so that the SP circulates in the pulse delay circuit 12.

  The process in which the SP circulates in the pulse delay circuit 12 will be specifically described as follows. When SP is not input to one input terminal of the first-stage delay unit NAND (when SP is at “L” level), the level of the output terminal of the delay unit NAND does not depend on the input of the other input terminal, Becomes “H” level. The level of the output terminal of each delay unit after the second-stage delay unit BUF1 also becomes “H” level.

  Subsequently, SP is input to one input terminal of the first-stage delay unit NAND (SP becomes “H” level). Since the level of the other input terminal of the delay unit NAND is “H” level by the SP output from the delay unit BUF15 in the final stage, the level of the output terminal of the delay unit NAND is the power supply voltage (Vin + Vref). It switches to the “L” level with a delay time corresponding to the voltage level. The level of the output terminal of each delay unit after the second-stage delay unit BUF1 is also sequentially switched to the “L” level with a delay time corresponding to the voltage level of the power supply voltage (Vin + Vref).

  When the level of the output terminal of the last-stage delay unit BUF15 is switched to the “L” level, the level of the output terminal of the first-stage delay unit NAND is “H” over a delay time corresponding to the voltage level of the power supply voltage (Vin + Vref). “Switch to level. The level of the output terminal of each delay unit after the second-stage delay unit BUF1 is also sequentially switched to the “H” level with a delay time corresponding to the voltage level of the power supply voltage (Vin + Vref).

  When the level of the output terminal of the final delay unit BUF15 is switched to the “H” level, the level of the output terminal is switched to the “L” level in order from the first delay unit NAND in the next round. Thereafter, while the SP is being input, an operation in which the level of the output terminal is sequentially switched from the first delay unit NAND to the opposite level every time the level of the output terminal of the delay unit BUF15 of the final stage is switched is repeated. As a result, the SP continues to circulate in the pulse delay circuit 12.

  The time required from when the level of the input terminal of each delay unit is switched to when the level of the output terminal is switched is a delay time corresponding to Vin + Vref which is the power supply voltage of each delay unit. For this reason, the number of stages of the delay unit through which the SP passes within a predetermined time depends on the analog voltage (Vin + Vref).

  The pulse passage stage number detection circuit 22 is a circuit that detects the number of stages that the SP has passed through the delay unit in the pulse delay circuit 12. An output signal of each delay unit in the pulse delay circuit 12 is input to the pulse passage stage number detection circuit 22.

  The pulse passing stage number detection circuit 22 is the number of times that the level of the output terminal of the 16th delay unit BUF15 in the pulse delay circuit 12 is switched from "H" level to "L" level or from "L" level to "H" level. Is output as an 8-bit count value. The pulse passing stage number detection circuit 22 outputs 16-bit data representing a state in which the level of the output terminal of each of the 16 delay units of the pulse delay circuit 12 is “H” level or “L” level. To do.

  The above 8-bit count value and 16-bit data output from the pulse passage stage number detection circuit 22 indicate how many rounds the SP has traveled through the pulse delay circuit 12 and to which delay unit has been advanced. . For example, when the count value is 4 times, the output of the delay unit BUF4 at the fifth stage is “L” level, and the output of the delay unit BUF5 at the sixth stage is “H” level, the SP sets the delay unit. The number of stages passed is 16 stages × 4 times + 5 stages = 69 stages.

  As described above, the pulse passing stage number detection circuit 22 is an 8-bit + 16-bit digital signal indicating the number of stages through which the SP has passed through the pulse delay circuit 12 constituted by a delay unit to which an analog voltage (Vin + Vref) is applied as a power supply voltage. Output.

  The configurations of the pulse delay circuit 13 and the pulse passage stage number detection circuit 23 are the same as those of the pulse delay circuit 12 and the pulse passage stage number detection circuit 22, respectively. The pulse passing stage number detection circuit 23 outputs, as a digital signal of 8 bits + 16 bits, the number of stages that the SP has passed through the pulse delay circuit 13 composed of a delay unit to which an analog voltage (Vref) is applied as a power supply voltage.

  Next, a processing procedure of the A / D conversion apparatus 100 will be described. First, Vin is input to the level shift circuit 51, and Vin + Vref and Vref are output from the level shift circuit 51. Vref only needs to be a voltage with little fluctuation, and need not be a specific voltage (it is not necessary to know a detailed voltage value and may be an arbitrary voltage value). However, it is considered to be optimal for obtaining the effect of the present invention that the voltage near the minimum voltage (Vmin in FIG. 9) within the input voltage range in which the input / output characteristics of the pulse delay circuit are linear is Vref. The inventor thinks.

  Subsequently, SP is simultaneously input to the pulse delay circuit 12 and the pulse delay circuit 13 (the SP level is switched from the “L” level to the “H” level). The SP circulates in the pulse delay circuit 12 and the pulse delay circuit 13 with different delay times (a delay time based on Vin + Vref in the pulse delay circuit 12 and a delay time based on Vref in the pulse delay circuit 13). The pulse passage stage number detection circuit 22 and the pulse passage stage number detection circuit 23 detect the number of stages that the SP passes through the respective delay units.

  Subsequently, LP is input to the output arithmetic circuit unit 41 after a predetermined time (sampling time) has elapsed since the SP was input (the LP level is switched from the “L” level to the “H” level). The output arithmetic circuit unit 41 latches the number of stages (count value and output value of each delay unit) detected by the pulse passage stage number detection circuit 22 and the pulse passage stage number detection circuit 23 at the timing when LP is inputted, The difference is encoded to 12 bits and output as the final A / D conversion result (out).

For example, the output (out_Vin) of the pulse passage stage number detection circuit 22 becomes 1000 stages (the output value of each delay unit of 1 to 16 stages = “0000000011111111”, the count value = “00111110”). When the output (out_Vref) becomes 100 stages (output value of each delay unit of 1 to 16 stages = “000011111111111”, count value = “00000110”), the output out is expressed by the following equation (2).
out = out_Vin−out_Vref = 900 stages (decimal number) = “001110000001” (binary number) (2)
That is, the output arithmetic circuit unit 41 outputs a 12-bit digital signal “001110000001”.

  Next, input / output characteristics of the A / D converter 100 according to the present embodiment will be described. FIG. 2 shows input / output characteristics of the A / D converter 100. FIG. 3 shows the input / output characteristics when the A / D conversion result is corrected so that the input / output characteristics of the A / D converter 100 are linear. 2 and 3 respectively correspond to FIGS. 8 and 9 showing the input / output characteristics of the above-described conventional A / D converter 300 (FIG. 7).

  When Vin is 0, the power supply voltage (Vin + Vref) applied to each delay unit in the pulse delay circuit 12 is equal to the power supply voltage (Vref) applied to each delay unit in the pulse delay circuit 13. For this reason, the number of stages detected by the pulse passage stage number detection circuit 22 and the pulse passage stage number detection circuit 23 becomes equal, and the A / D conversion result (out), which is the difference between each stage number, becomes zero. Therefore, as shown in FIG. 2, the input / output characteristic (curve L1) is based on the origin (the output is 0 when the input is 0).

  When the A / D conversion result is corrected so that the input / output characteristic is a straight line, the relationship between the input signal (analog input voltage Vin) and the output signal (out) is proportional as shown in FIG. 2 shows a straight line L2 corresponding to the input / output characteristics shown in FIG. 3 so that the difference in effect due to the correction can be understood.

  As described above, according to the present embodiment, the input / output characteristics of the A / D converter can be set as the origin reference, and the intercept does not become an error factor even when the A / D conversion result is directly used in the calculation. The calculation accuracy can be improved.

  Moreover, according to this embodiment, the following effects are also acquired. In order to correct the A / D conversion result so that the input / output characteristic is a straight line, in the conventional A / D conversion apparatus 300 (FIG. 7), when performing linear approximation at n points, sampling at n points is required. For example, when performing linear approximation with three points, sampling of three points of Vin = Vmin, Vmax, (Vmin + Vmax) / 2 is required as shown in FIG.

  On the other hand, according to the present embodiment, one of the n points can be set as the origin. Therefore, if sampling at n−1 points is performed, correction equivalent to that at the time of sampling at n points is performed. It becomes possible. For example, when linear approximation is performed at three points, correction is possible by sampling at two points Vin = Vmax and Vmax / 2 as shown in FIG. Therefore, since the number of samplings is reduced, the correction time can be shortened.

  Further, with the decrease in the number of samplings, it is possible to reduce the correction error that appears at the time of correction. For example, when sampling is performed under the condition Vin = Vmin in order to perform correction, if the actual voltage is Vin = Vmin + Δα, Δα becomes a factor of correction error. The effect of. However, according to the present embodiment, the number of samplings is smaller than in the prior art, so that the influence of correction errors can be suppressed.

<Second Embodiment>
Next, a second embodiment of the present invention will be described. FIG. 4 shows the configuration of the A / D converter according to the present embodiment. In FIG. 4, the A / D conversion device 200 includes a pulse delay circuit unit 1, a pulse passage stage number detection circuit unit 2, an arithmetic output circuit unit 42, and a level shift circuit 52.

  The pulse delay circuit unit 1 includes a pulse delay circuit 14. The pulse delay circuit 14 has a configuration in which a plurality of delay units that delay the sampling pulse (SP) by a delay time corresponding to the magnitude of the output voltage of the level shift circuit 52 are connected. The pulse passage stage number detection circuit unit 2 includes a pulse passage stage number detection circuit 24. The pulse passage stage number detection circuit 24 detects the number of stages that the SP has passed through the delay unit in the pulse delay circuit 14.

  The arithmetic output circuit unit 42 latches the output signal of the pulse passing stage number detection circuit 24 based on the latch pulse (LP), and calculates and outputs the output signal. The level shift circuit 52 switches and outputs Vref and a voltage (Vin + Vref) obtained by adding Vin and Vref. In this embodiment, Vref and Vin + Vref are sequentially input to the same pulse delay circuit 14, and A / D conversion corresponding to each voltage is sequentially performed.

  The configurations of the pulse delay circuit 14 and the pulse passage stage number detection circuit 24 are the same as the configurations of the pulse delay circuit 12 and the pulse passage stage number detection circuit 22 according to the first embodiment, respectively. The pulse passing stage number detection circuit 24 uses an 8-bit + 16-bit digital signal to indicate the number of stages that the SP has passed through the pulse delay circuit 14 configured by a delay unit to which the output voltage of the level shift circuit 52 is applied as a power supply voltage. Output.

  Next, the processing procedure of the A / D conversion apparatus 200 will be described with reference to FIG. First, the output voltage of the level shift circuit 52 is switched to Vref (step S1).

  Subsequently, when SP is input to the pulse delay circuit 14 (the SP level is switched from “L” level to “H”), the SP circulates around the delay unit in the pulse delay circuit 14 with a delay time based on Vref. To do. The pulse passage stage number detection circuit 24 detects the number of stages that the SP passes through the delay unit. After a predetermined time (sampling time) has elapsed from the SP input, LP is input to the output arithmetic circuit unit 42 (the LP level is switched from the “L” level to the “H” level). The output arithmetic circuit unit 42 latches and stores the number of stages (out_Vref) detected by the pulse passing stage number detection circuit 24 at the timing when LP is input (step S2).

  Subsequently, the output voltage of the level shift circuit 52 is switched to Vin + Vref (step S3). Immediately after this, SP is input again to the pulse delay circuit 14, and the output arithmetic circuit unit 42 latches the number of stages (out_Vin) through which the SP passes through the delay unit at the timing when LP is input again, as in step S2. (Step S4).

  Subsequently, the output arithmetic circuit unit 42 subtracts out_Vin detected in step S2 from out_Vin stored in step S4, encodes it to 12 bits, and outputs the result as the final A / D conversion result (out) (step). S5).

  In the present embodiment, when the A / D conversion process is performed continuously, as shown in FIG. 6, the out_Vref is detected only once (steps S1 and S2), and the out_Vin detection operation (steps S3 to S3) is performed. Only S7) may be repeated. As a result, the processing speed of continuous A / D conversion can be improved and the current consumption can be reduced.

  The input / output characteristics of the A / D converter 200 according to the present embodiment are also the same as those in the first embodiment, and are based on the origin (the output is 0 when the input is 0). Therefore, according to the present embodiment, the input / output characteristics of the A / D converter can be set as the origin reference, and the same effect as that of the first embodiment can be obtained.

  Furthermore, in the present embodiment, sampling based on Vref and sampling based on Vin + Vref are performed by the same pulse delay circuit, so that an error in the A / D conversion result can be reduced. For example, in the A / D conversion device 100 shown in FIG. 1, if the characteristics of the pulse delay circuit 12 and the pulse delay circuit 13 are different and the delay time when the same analog voltage is applied is different, the difference between these characteristics is Appears as an error. However, according to this embodiment, since a common pulse delay circuit is used for two samplings, an error due to this characteristic difference does not occur. In addition, the circuit scale can be reduced by sharing the pulse delay circuit and the pulse passing stage number detection circuit used for sampling twice.

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to the above-described embodiments, and includes design changes and the like without departing from the gist of the present invention. .

  DESCRIPTION OF SYMBOLS 1 ... Pulse delay circuit unit, 2 ... Pulse passage stage number detection circuit unit, 11, 12, 13, 14 ... Pulse delay circuit, 21, 22, 23, 24 ... Pulse passage stage number detection circuit, 31, 41, 42 ... arithmetic output circuit unit, 51, 52 ... level shift circuit, 100, 200, 300 ... A / D converter

Claims (3)

An A / D converter for converting an analog input voltage into a digital value,
A pulse delay circuit unit having a pulse delay circuit in which a plurality of delay units for delaying a pulse signal with a delay time corresponding to the magnitude of an input analog voltage are connected;
A pulse passage stage number detection circuit unit having a pulse passage stage number detection circuit for detecting the number of stages that the pulse signal has passed through the delay unit in the pulse delay circuit unit;
A first stage number detected by the pulse passing stage number detection circuit unit when a reference voltage is input to the pulse delay circuit unit, and the analog input voltage as the reference voltage for the pulse delay circuit unit. When the added voltage is input, information on the difference from the second stage number detected by the pulse passing stage number detection circuit unit is calculated, and the result of the calculation is output as the digital value corresponding to the analog input voltage An arithmetic output circuit unit to
An A / D conversion device.   The A / D converter according to claim 1, wherein the reference voltage and a voltage obtained by adding the analog input voltage to the reference voltage are sequentially input to the same pulse delay circuit. A level shift circuit for outputting a level shift voltage obtained by shifting the voltage level of the analog input voltage by the level of the reference voltage;
The pulse delay circuit unit includes:
A first pulse delay circuit in which a plurality of first delay units that delay the first pulse signal with a delay time corresponding to the magnitude of the reference voltage are connected;
A second pulse delay circuit comprising a plurality of stages of second delay units that delay the second pulse signal by a delay time corresponding to the level shift voltage;
Have
The pulse passage stage number detection circuit unit is:
A first pulse passage stage number detection circuit that detects the first stage number that the first pulse signal has passed through the first delay unit;
A second pulse passage stage number detection circuit that detects the second stage number that the second pulse signal has passed through the second delay unit;
Having
The A / D converter according to claim 1.

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