JP2010239304A - A/d conversion device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an A/D conversion device that has input/output characteristics of proper linearity, without actually A/D-converting many reference voltages so as to linearly approximate input/output characteristics. <P>SOLUTION: The A/D conversion device includes a control function of changing the timing of latching the number of passing stages of delay units (and the number of times of circulations) according to the level of an analog input voltage, so that the timing of latching the number of passing stages of delay units (and the number of times of circulations) can be changed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an A / D converter that converts an analog input voltage into a digital value using a pulse delay circuit that delays a pulse signal by a delay time corresponding to the magnitude of the analog input voltage.

2. Description of the Related Art Conventionally, as an A / D conversion device that can obtain a high-resolution digital value with a simple configuration, a configuration shown in FIG. 9 is known (see Patent Document 1).
In the A / D converter of FIG. 9, the pulse delay circuit 1 has a configuration in which a plurality of delay units (NAND1, BUF1,..., BUF15) each consisting of various gate circuits are connected in a ring shape. An analog input signal (voltage) Vin to be A / D converted is supplied as a power supply voltage for each delay unit.
When the pulse signal SP is input to the pulse delay circuit 1, the pulse signal SP sequentially passes through each delay unit with a delay time corresponding to the power supply voltage, and circulates in the pulse delay circuit 1.
The number of stages of the delay unit through which the pulse signal SP has passed is determined by the delay time of the delay unit, that is, the analog input signal Vin supplied as the power supply voltage. ) Is detected.
The output encoder 4 takes in the detection result of the pulse passing stage number detection circuit 2 at the input timing of the latch pulse LP input after the sampling time of A / D conversion from the start of input of the pulse signal SP, and the pulse signal SP passes at that time. A value obtained by encoding the number of stages is output as a digital value Cout after A / D conversion.

  Here, in the above A / D conversion device, the delay time of the delay unit and the power supply voltage are not in a linear function relationship, so the input / output characteristics of the analog input signal and the digital value after A / D conversion become a curve. . Therefore, as a method of bringing the input / output characteristics closer to an ideal straight line, the voltage range of the analog input signal is divided into a plurality of areas, and the input / output characteristics are linearly approximated for each divided area, and the coordinate points on the approximated straight line are used. It has been proposed to correct a digital value after A / D conversion using a conversion formula (see Patent Document 2).

JP-A-5-259907 JP 2004-274157 A

  However, in order to obtain a conversion formula for approximately correcting the data after A / D conversion, a large number of reference voltages are actually A / D converted, and A / D conversion at coordinate points corresponding to each reference voltage is performed. There is a problem that it is complicated to set the conversion formula because it is necessary to set the conversion formula using the obtained A / D conversion data.

  The present invention has been made on the basis of the above-mentioned problem recognition, and in order to approximate the input / output characteristics linearly, input / output characteristics close to an ideal straight line without actually performing A / D conversion on a large number of reference voltages. It is an object of the present invention to provide an A / D conversion device that can obtain the above.

  In order to solve the above-described problem, an A / D conversion device according to the present invention is an A / D conversion device that converts an analog input voltage into a digital signal, and has a first delay time corresponding to the magnitude of the analog input voltage. A first pulse delay circuit in which a plurality of delay units for delaying the pulse signal are connected in a plurality of stages, and a second in which a plurality of delay units for delaying the second pulse signal with a delay time corresponding to the magnitude of the analog reference voltage are connected. A pulse delay circuit, a first pulse passing stage number detecting circuit for detecting the number of stages in which the first pulse signal has passed through the delay unit in the first pulse delay circuit in a predetermined time, and the second pulse signal Includes a second pulse passage stage number detection circuit that detects the number of stages that have passed through the delay unit in the second pulse delay circuit in a predetermined time, and a delay unit detected by the first pulse passage stage number detection circuit. An output unit that outputs a digital signal representing the difference in the number of stages of the delay unit detected by the second pulse passing stage number detection circuit, and the predetermined time is determined according to the magnitude of the analog input voltage And a timing control unit.

  The timing control unit of the present invention outputs the third pulse signal with a delay time corresponding to the magnitude of the level shift voltage level-shifted so as to increase or decrease in a linear function with respect to the analog input voltage. A third pulse delay circuit in which a plurality of delay units to be delayed are connected, and a third pulse for detecting the number of stages in which the third pulse signal passes through the delay unit in the third pulse delay circuit in a predetermined time The predetermined time so that the difference between the number of stages of the delay unit detected by the first stage and the number of delay units detected by the third pulse passage stage number detection circuit is constant. And a timing determination unit for determining.

  Further, the output unit of the present invention is characterized in that the number of stages of the delay unit is detected a plurality of times and a digital signal obtained by calculating the detection results of the plurality of times is output.

  Further, the A / D conversion device of the present invention that performs the detection of the number of stages a plurality of times uses the predetermined time determined at the m-th time as a predetermined time after the (m + 1) -th time.

  According to the present invention, the time for latching the number of passing stages (and the number of laps) of the delay unit is changed according to the magnitude of the analog input voltage so as to compensate for the conventional curve (nonlinearity) of the input / output characteristics. An effect of providing an A / D conversion device having excellent linearity input / output characteristics without actually A / D converting a large number of reference voltages in order to approximate the input / output characteristics linearly. Is obtained.

It is the block diagram which showed the structure of the A / D converter by embodiment of this invention. It is the flowchart which showed the process sequence of the A / D converter by embodiment of this invention. It is the graph which showed the relationship of the A / D conversion result by embodiment of this invention. It is the block diagram which showed the example of the level shift circuit by embodiment of this invention. It is the block diagram which showed the structure in the case of calculating and outputting the A / D conversion result by embodiment of this invention. It is the flowchart which showed the process sequence which performs n oversampling by the A / D converter by embodiment of this invention. It is the block diagram which showed the structure in the case of memorize | storing the several A / D conversion result by embodiment of this invention. It is the figure which showed the output timing of the latch pulse in the A / D converter of embodiment of this invention. It is the block diagram which showed the structure of the conventional A / D converter.

<First Embodiment>
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the A / D converter according to the present embodiment. In FIG. 1, an A / D converter 10 includes a first pulse delay circuit 1, a second pulse delay circuit 7, a first pulse passage stage number detection circuit 2, a second pulse passage stage number detection circuit 8, a latch timing. It comprises a control unit 3 (timing control unit) and an output encoder 4 (output unit). The latch timing control unit 3 includes a third pulse delay circuit 31, a third pulse passing stage number detection circuit 32, a level shift circuit 33, and an output stage number comparison circuit 34 (timing determination unit). , A first latch & encoder 41, a second latch & encoder 42, and a subtractor 43.

The first pulse delay circuit 1 is a ring delay line (RDL) that circulates a pulse SP by connecting a 16-stage gate circuit (hereinafter referred to as a delay unit) having a delay amount corresponding to a power supply voltage in a ring shape. is there.
In the first-stage delay unit NAND1, the pulse SP is input to one input terminal, the output of the 16th-stage delay unit BUF15 is input to the other input terminal, and the first pulse delay circuit 1 operates. In some cases, it is constituted by a gate circuit (for example, a NAND circuit: NAND gate) that logically inverts the output of the 16th delay unit BUF15.
The delay unit BUF15 from the second stage delay unit BUF1 to the 16th stage delay unit BUF15 outputs a value input to the input terminal to the output terminal (for example, a negative circuit: a buffer circuit in which NOT gates are connected in two stages). Consists of.

  The analog input voltage Vin is applied as a power supply voltage to the delay units (NAND1, BUF1,..., BUF15), and each delay unit applies the pulse SP input from the preceding delay unit to the power supply voltage (analog input). The voltage Vin) is output to the next delay unit with a delay time corresponding to the voltage level. The delay units connected in a ring shape operate in the same manner, and the pulse SP is sequentially transmitted from the preceding stage to the subsequent delay unit, so that the pulse SP circulates in the first pulse delay circuit 1.

The process in which the pulse SP circulates in the first pulse delay circuit 1 will be specifically described as follows.
When the pulse SP is not input (when the SP signal 70 is at “L” level), the output terminal of the first-stage delay unit NAND1 is the power supply voltage (analog input voltage Vin) regardless of the input of the other input terminal. It becomes "H" level with a delay time corresponding to the voltage level of the output, and the output terminals of the delay units after the second delay unit BUF1 also sequentially have a delay time according to the voltage level of the power supply voltage (analog input voltage Vin). Becomes “H” level.
When the pulse SP is input (SP signal 70 becomes “H” level), the output terminal of the first-stage delay unit NAND1 is at the “H” level where the other input terminal is output from the last-stage delay unit BUF15. Is switched to “L” level with a delay time corresponding to the voltage level of the power supply voltage (analog input voltage Vin) by the input of the pulse SP, and the output of each delay unit after the second delay unit BUF1 The terminals are also sequentially switched to the “L” level with a delay time corresponding to the voltage level of the power supply voltage (analog input voltage Vin).
When the output terminal of the last-stage delay unit BUF15 is switched to the “L” level, the output terminal of the first-stage delay unit NAND1 is now powered by the input terminal to which the output of the last-stage delay unit BUF15 is input. It switches to “H” level with a delay time corresponding to the voltage level of (analog input voltage Vin), and the output terminal of each delay unit after the second delay unit BUF1 is also set to the voltage level of the power supply voltage (analog input voltage Vin). The level is sequentially switched to the “H” level with a corresponding delay time.
When the signal at the output terminal of the delay unit BUF15 at the final stage is switched to “H”, it is switched to “L” in turn from the first delay unit NAND1 in the next round.
Thereafter, while the pulse SP is being input, the operation of sequentially switching from the first delay unit NAND1 to the reverse output level is performed by switching the output terminal of the final delay unit BUF15. 1 circulates in the pulse delay circuit 1.

  The delay time from when the input terminal level of each delay unit is switched to when the output terminal level is switched is a delay time corresponding to the analog input voltage Vin that is the power supply voltage of each delay unit. The number of stages of delay units through which the pulse SP circulating in one pulse delay circuit 1 passes depends on the analog input voltage Vin.

The first pulse passage stage number detection circuit 2 is a circuit that detects the number of stages that the pulse SP has passed through the delay unit in the first pulse delay circuit 1.
The output signal of each delay unit of the first pulse delay circuit 1 is input to the first pulse passage stage number detection circuit 2.
The first pulse passing stage number detection circuit 2 is configured such that the signal at the output terminal of the 16th delay unit BUF15 in the first pulse delay circuit 1 changes from “H” level to “L” level or from “L” level to “L” level. The result of the counter 21 counting the number of times of switching to the H level is output as an 8-bit count value, and the “H” level input from each of the 16 delay units of the input first pulse delay circuit 1 or 16-bit data representing each state of the “L” level is output.

Here, the count value and the 16-bit data output from the first pulse passing stage number detection circuit 2 are the number of rounds in which the pulse SP circulates in the first pulse delay circuit 1 and to which delay unit. Shows how advanced.
For example, if the count value is 4 times, the output of the delay unit BUF4 at the fifth stage is “L” level, and the output of the delay unit BUF5 at the sixth stage is “H” level, the delay unit has passed. The number of stages is 16 stages × 4 times + 5 stages = 69 stages.

  The latch timing control unit 3 is a circuit that controls the timing at which the output encoder 4 latches the count value and 16-bit data output from the first pulse passage stage number detection circuit 2 by the output of the latch pulse LP.

The level shift circuit 33 is a power supply voltage for each delay unit of the third pulse delay circuit 31, which is a level shift voltage (hereinafter, Vin−ΔVin) obtained by shifting the level so as to decrease linearly with respect to the analog input voltage Vin. Output as.
Here, for example, ΔVin is set so as to have a relationship represented by the following expression (1) with respect to Vin.
ΔVin = b + a × Vin (b> 0, a> 0) (1)
In this embodiment, the level shift voltage is set to a voltage that decreases linearly with respect to Vin, but it may be set to a voltage that increases linearly with respect to Vin (Vin + ΔVin). Good.

The third pulse delay circuit 31 and the third pulse passage stage number detection circuit 32 of the latch timing control unit 3 have the same configurations as the first pulse delay circuit 1 and the first pulse passage stage number detection circuit 2 described above, respectively. The only difference is that the power supply voltage supplied to each delay unit of the third pulse delay circuit 31 is the level shift voltage (Vin−ΔVin) output from the level shift circuit 33.
Therefore, the number of stages in which the pulse SP passes through the delay unit in the third pulse delay circuit 31 and the number of stages in which the pulse SP passes through the delay unit in the first pulse delay circuit 1 are the shifted voltage value ΔVin. The number of stages differs by the corresponding number of stages.
The second pulse delay circuit 7 and the second pulse passage stage number detection circuit 8 have the same configuration as the first pulse delay circuit 1 and the first pulse passage stage number detection circuit 2 described above, respectively. The only difference is that the power supply voltage supplied to each delay unit of the pulse delay circuit 31 is an analog reference voltage (Vref).

The output stage number comparison circuit 34 is a circuit that generates a latch pulse LP that causes the output encoder 4 to latch data in order to output the digital data Cout A / D converted by the A / D converter 10.
The output stage number comparison circuit 34 is based on the analog input voltage Vin output from the first pulse passage stage number detection circuit 2 and the level shift voltage output from the third pulse passage stage number detection circuit 32. The delay unit passage stage number of the pulse SP based on (Vin−ΔVin) is compared, and when the difference becomes a preset difference, the first pulse passage stage number detection circuit 2 and the second pulse passage stage number detection circuit 8 is output to the first latch & encoder 41 and the second latch & encoder 42 of the output encoder 4.

  For example, the set value of the difference between the number of delay unit passage stages in the first pulse passage stage number detection circuit 2 and the number of delay unit passage stages in the third pulse passage stage number detection circuit 32 is 72 stages (= 16 stages × 4 rounds + 8 stages). In this case, the output stage number comparison circuit 34 counts the count value and the count value output from the first pulse passage stage number detection circuit 2 every time the count value output from the third pulse passage stage number detection circuit 32 is updated. After the calculation result is 4, the 16-bit data output from the first pulse passing stage number detection circuit 2 and the 16 bits output from the third pulse passing stage number detection circuit 32 are calculated. The corresponding data are compared with each other, and the latch pulse LP is output when the number of bits having different values exceeds 8.

  In the above description, the number of bits having different values is compared and the latch pulse LP is output. However, if the calculation result of the difference in the count value is an odd number, it is output from the first pulse passage stage number detection circuit 2. The 16-bit data and the 16-bit data output from the third pulse passage stage number detection circuit 32 are compared with each other corresponding bits, the number of bits having the same value is compared, and the latch pulse LP is output. .

  For example, the set value of the difference between the delay unit passage stage number in the first pulse passage stage number detection circuit 2 and the delay unit passage stage number in the third pulse passage stage number detection circuit 32 is 88 stages (= 16 stages × 5 rounds + 8 stages). In this case, the output stage number comparison circuit 34 counts the count value and the count value output from the first pulse passage stage number detection circuit 2 every time the count value output from the third pulse passage stage number detection circuit 32 is updated. After the calculation result is 5, the 16-bit data output from the first pulse passing stage number detection circuit 2 and the 16 bits output from the third pulse passing stage number detection circuit 32 are calculated. The corresponding data are compared with each other, and the latch pulse LP is output at the timing when the number of bits having the same value exceeds 8.

  Further, when accuracy is not required for A / D conversion, the timing of outputting the latch pulse LP is determined by the difference between the count value of the third pulse passage stage number detection circuit 32 and the count value of the first pulse passage stage number detection circuit 2. Alternatively, the latch pulse LP may be output when the difference becomes the difference between the preset number of turns.

  The output encoder 4 includes an 8-bit count value and 16 bits output from the first pulse passing stage number detection circuit 2 at the rising edge of the latch pulse LP input from the output stage number comparison circuit 34 in the first latch & encoder 41. Is output to the subtracter 43 based on the latched data, and is input from the output stage number comparison circuit 34 in the second latch & encoder 42. The 8-bit count value and 16-bit data output from the second pulse passing stage number detection circuit 8 at the rising edge of the latch pulse LP are latched, and a digital signal (Cout2) representing the 12-bit passing stage number based on the latched data. ) Is output to the subtracter 43, and the subtracter 43 subtracts the two 12-bit signals described above. The result (Cout1-Cout2) is output as the A / D conversion result (Cout) of the analog input voltage Vin with the analog reference voltage (Vref) as a reference.

  Here, the 8-bit count value output from the first pulse passing stage number detection circuit 2 is assigned to the upper 8 bits of the output of the first latch & encoder 41, and the first 4 bits are assigned to the first 4 bits. 4-bit data obtained by encoding the output value of each of the 16 stages of delay units in the pulse delay circuit 1 (representing the position of the pulse SP that has passed through the delay unit) is assigned.

For example, when the output of the fifth delay unit is “L” level and the output of the sixth delay unit is “H” level, the number of stages that the pulse SP has passed through the delay unit is five. “5” (1′b0101) is assigned to the lower 4 bits of data.
Similarly, if the number of passing stages is 1, the lower 4 bits of data are “1” (1′b0001), 15 stages are “F” (1′b1111), and 16 stages are “0” (1 'b0000).
Similarly, an 8-bit count value output from the second pulse passing stage number detection circuit 8 is assigned to the upper 8 bits of the output of the second latch & encoder 42, and the lower 4 bits are assigned to the first bit. 4-bit data obtained by encoding the output values of the 16 delay units in the 2 pulse delay circuit 7 is assigned.

  The latching timing of the output encoder 4 does not depart from the spirit of the present invention even when the latch pulse LP input from the output stage number comparison circuit 34 falls.

  Next, a processing procedure of the A / D conversion device will be described. FIG. 2 is a flowchart showing a processing procedure in the A / D conversion apparatus according to the present embodiment.

  First, in step S1, the analog input voltage Vin is input to the first pulse delay circuit 1 and the level shift circuit 33, and the analog reference voltage Vref is input to the second pulse delay circuit 2. Next, when the pulse SP is input to the first pulse delay circuit 1, the second pulse delay circuit 7, and the third pulse delay circuit 31 in step S2, the pulse SP is converted into the first pulse delay circuit. Different delay times for the first, second pulse delay circuit 7 and third pulse delay circuit 31 (the first pulse delay circuit 1 has a delay time depending on the voltage value of the analog input voltage Vin, a second pulse delay circuit) 7 is a delay time based on the voltage value of the analog reference voltage Vref, and the third pulse delay circuit 31 is a delay time based on the voltage value of the level shift voltage Vin−ΔVin). The detection circuit 2, the second pulse passage stage number detection circuit 8, and the third pulse passage stage number detection circuit 32 determine the number of stages that the pulse SP passes through each delay unit. Out to.

  Next, the output stage number comparison circuit 34 compares the difference between the delay unit passage stage numbers detected by the first pulse passage stage number detection circuit 2 and the third pulse passage stage number detection circuit 32 in step S3. It is determined whether or not becomes a preset value. If the difference in the number of passing stages reaches the set value, in step S4, a latch pulse LP is output for the output encoder 4 to latch the number of delay unit passing stages detected by the first pulse passing stage number detecting circuit 2. . If the difference in the number of passage stages is not the set value, step S3 is repeated.

  Next, in step S5, the output encoder 4 determines the count value detected by the first pulse passing stage number detection circuit 2 in the first latch & encoder 41 in accordance with the latch pulse LP input from the output stage number comparison circuit 34 and each of the count values. The output value of the delay unit is latched and encoded into a 12-bit digital signal (Cout1). The count value detected by the second pulse passage stage number detection circuit 8 in the second latch & encoder 42 and the output value of each delay unit Is encoded into a 12-bit digital signal (Cout2), and the result (Cout) obtained by subtracting the digital signal (Cout2) from the digital signal (Cout1) in the subtractor 43 is output to complete the processing.

  Next, input / output characteristics of the A / D conversion device having the above-described configuration will be described. FIG. 3 is a graph showing the relationship between the A / D conversion results of the present invention. In FIG. 3, the X axis indicates the analog input voltage Vin (Vin−Vref) with the analog reference voltage Vref as a reference, and the Y axis indicates the A / D converted digital data Cout.

  In FIG. 3, an A curve (thick solid line) is an input / output characteristic of the A / D converter according to the present invention. The input / output characteristic will be described using other B straight lines, C curves, and D curves. Originally, the ideal characteristics required by the A / D converter are the input / output characteristics that do not bend as shown by the B straight line (dotted line), but the input / output characteristics (analogue) of the conventional A / D converter shown in FIG. The input / output characteristics when the reference voltage Vref is used as a reference and the origin is set as a reference is, for example, a C curve (two-dot chain line), and a large deviation from the B straight line occurs. Therefore, if the difference in the number of passing stages with respect to a constant ΔVin differential voltage is made constant, the time for detecting the number of passing stages of the pulse becomes longer as Vin increases, and Cout rises upward. On the contrary, as Vin increases, the deviation from the B line increases. Therefore, in the present invention, ΔVin is not fixed, but is set so that ΔVin increases linearly with respect to Vin. For example, as described above, setting is made so as to satisfy the relationship of Expression (1). As a result, the upward deviation of the D curve from the B straight line is reduced, and the input / output characteristics shown in the A curve can be realized.

  Next, the level shift circuit 33 of the A / D converter according to the present embodiment will be described. FIG. 4 is a block diagram showing an example of the configuration of the level shift circuit 33. 4, the level shift circuit 33 includes an operational amplifier 100, a PMOS transistor 101, a resistor 102, NMOS transistors 103 and 104, and a current source 105. The level shift circuit 33 receives the analog input voltage Vin and outputs a level-shifted level shift voltage Vin−ΔVin.

In the level shift circuit 33 of FIG. 4, the analog input voltage Vin appears between the drain of the PMOS transistor 101 and the resistor 102 due to the virtual short-circuit effect of the operational amplifier 100. A current I2 that is turned back through a current mirror circuit constituted by the NMOS transistors 104 and 103 flows, and an analog input voltage Vin is obtained by the following equation (2) between the resistor 102 and the drain of the NMOS transistor 103. A voltage level shifted by ΔVin appears, and this voltage is output as a level shift voltage.
ΔVin = R × I2 (2)
In the above equation (2), R represents the resistance value of the resistor 102, and I2 represents the current value of the current I2.
Here, because the current I2 increases linearly with respect to the analog input voltage Vin due to the Early effect of the NMOS transistor, ΔVin obtained by the above equation (2) also increases linearly with respect to Vin. It will be.

  As described above, according to the mode for carrying out the present invention, the number of stages of the delay unit (and the frequency) is set according to the magnitude of the analog input voltage so as to compensate for the curve (nonlinearity) of the input / output characteristics. A / D having good linearity input / output characteristics without actually A / D converting a large number of reference voltages in order to approximate the input / output characteristics linearly. A conversion device can be provided.

  Further, in the conventional A / D converter, the latch pulse signal input from the outside needs to input a highly accurate pulse signal with respect to the pulse signal, but the difference in the number of stages of the pulse delay circuit should be compared. Thus, since the latch pulse LP is generated, it is not necessary to input a highly accurate pulse signal, and it is possible to easily provide a highly accurate A / D converter.

<Second Embodiment>
Hereinafter, as a second embodiment of the present invention, a case where an A / D conversion result is calculated and output will be described. FIG. 5 is a block diagram showing the configuration of the A / D converter according to the present embodiment. 5, the A / D converter 20 includes a first pulse delay circuit 1, a second pulse delay circuit 7, a first pulse passage stage number detection circuit 2, a second pulse passage stage number detection circuit 8, a latch timing. It comprises a control unit 3 (timing control unit), an output encoder 4 (output unit), and a signal processing unit 5 (output unit). The latch timing control unit 3 includes a third pulse delay circuit 31, a third pulse passing stage number detection circuit 32, a level shift circuit 33, and an output stage number comparison circuit 34 (timing determination unit). , A first latch & encoder 41, a second latch & encoder 42, and a subtractor 43. The signal processing unit 5 includes a storage circuit 51 and an arithmetic circuit 52.

  In FIG. 5, the first pulse delay circuit 1, the second pulse delay circuit 7, the first pulse passage stage number detection circuit 2, the second pulse passage stage number detection circuit 8, and the latch timing control of the A / D converter 20 are illustrated. 3, output encoder 4, third pulse delay circuit 31, third pulse passing stage number detection circuit 32, level shift circuit 33, output stage number comparison circuit 34, first latch & encoder 41, second latch & encoder 42 and the subtractor 43 perform the same operation with the same configuration as the first embodiment shown in FIG.

  The signal processing unit 5 stores the digital data output from the output encoder 4 in the storage circuit 51 in accordance with the latch pulse LP, performs an operation in the operation circuit 52 based on the stored digital data, and outputs the calculated digital data Cout. Circuit.

  The operation of the A / D converter 20 includes the first pulse delay circuit 1 that uses the analog input voltage Vin as a power supply voltage, the second pulse delay circuit 7 that uses the analog reference voltage Vref as the power supply voltage, and the analog input voltage Vin. A pulse SP is inputted a plurality of times to the third pulse delay circuit 31 using the level shift voltage Vin−ΔVin level-shifted by the shift circuit 33 as a power supply voltage, and the pulse SP is used as a delay unit in the first pulse delay circuit 1. All digital data output with a plurality of latch pulses LP output when the number of stages passing and the number of stages that the pulse SP passes through the delay unit in the third pulse delay circuit 31 is a preset difference. Is stored in the signal processing unit 5, and final digital data Cout obtained as a result of calculating each stored digital data is stored. And outputs it as A / D conversion result of the A / D converter 10.

  For example, when oversampling is performed with this configuration, a plurality of A / D conversion results based on the analog input voltage Vin are stored in the storage circuit 51, and a plurality of stored digital data Cout are added and averaged by the arithmetic circuit 52. The result is output as the final A / D conversion result.

  Next, the processing procedure of the present embodiment will be described by taking oversampling as an example. FIG. 6 is a flowchart showing a processing procedure for performing oversampling n times by the A / D converter according to the present embodiment.

  First, in step S1, the analog input voltage Vin is input to the first pulse delay circuit 1 and the level shift circuit 33, and the analog reference voltage Vref is input to the second pulse delay circuit 2. In step S2, the oversampling counter is set to the number of times oversampling (= n), and in steps S3 to S6, the first digital data is obtained by the same processing procedure as the flowchart of FIG. 2 (steps S2 to S5). .

Next, the signal processing unit 5 stores the digital data output by the output encoder 4 in the storage circuit 51 in step S7.
Next, the A / D converter subtracts “1” from the oversampling counter in step S8, and checks in step S9 whether or not the value of the oversampling counter has become “0”. When the value of the oversampling counter becomes “0”, the arithmetic circuit 52 performs an addition average of the n pieces of digital data stored in the storage circuit 51 in step S10, and in step S11, the arithmetic circuit 52 The A / D converter outputs the final digital data Cout calculated by the above as an A / D conversion result. If the value of the oversampling counter is not “0” in step S9, the process returns to step S3, and the second and subsequent A / D conversions are repeated when the pulse SP is input.

  As described above, according to the embodiment for carrying out the present invention, it is possible to obtain a more accurate A / D conversion result by oversampling.

  In this embodiment, the A / D conversion results of a plurality of times are stored in the storage circuit 51, the calculation is performed by the calculation circuit 52, and the final A / D conversion result is output. It is also possible to output all the stored digital data from the A / D conversion device 20 and perform the calculation by an external calculation device such as a CPU.

  In this embodiment, the calculation performed by the calculation circuit 52 is an addition average, but any calculation processing method may be used.

<Third Embodiment>
Hereinafter, as a third embodiment of the present invention, another mode in which a plurality of A / D conversion results are stored will be described. FIG. 7 is a block diagram showing the configuration of the A / D converter according to the present embodiment. In FIG. 5, the A / D converter 30 includes a first pulse delay circuit 1, a second pulse delay circuit 7, a first pulse passage stage number detection circuit 2, a second pulse passage stage number detection circuit 8, and a latch timing. It comprises a control unit 3 (timing control unit), an output encoder 4 (output unit), and a signal processing unit 5 (output unit). The latch timing control unit 3 includes a third pulse delay circuit 31, a third pulse passing stage number detection circuit 32, a level shift circuit 33, and an output stage number comparison circuit 341 (timing determination unit). , A first latch & encoder 41, a second latch & encoder 42, and a subtractor 43. The signal processing unit 5 includes a storage circuit 51 and an arithmetic circuit 52.

  In FIG. 7, the first pulse delay circuit 1, the second pulse delay circuit 7, the first pulse passage stage number detection circuit 2, the second pulse passage stage number detection circuit 8 of the A / D converter according to the present embodiment, Latch timing control unit 3, output encoder 4, third pulse delay circuit 31, third pulse passing stage number detection circuit 32, level shift circuit 33, first latch & encoder 41, second latch & encoder 42, subtraction The device 43 performs the same operation with the same configuration as the first embodiment shown in FIG. 1 and the second embodiment shown in FIG.

  The output stage number comparison circuit 341 receives the same pulse SP as the pulse SP received by the first to third pulse delay circuits 1, 7, 31 and outputs the first latch pulse LP1 from the input of the first pulse SP. The time T (T = T1) is measured, and the sth (second and subsequent) latch pulse LPs is output after T1 has elapsed from the input of the sth pulse SP. That is, the first latch pulse LP1 is output in the same operation as the output stage number comparison circuit 34 according to the first embodiment shown in FIG. 1 and the second embodiment shown in FIG. The latch pulse LPs is output at a predetermined time (T1) from the pulse SP input.

  FIG. 8 is a diagram illustrating timing at which a latch pulse is output from the output stage number comparison circuit 341. When the first pulse SP is input, the time until the first latch pulse LP1 is output is measured, and when the second and subsequent pulses SP are input, the same time as the first latch pulse LP1 (the pulse SP is changed). The latch pulse LPs is output at the time after input).

  The processing procedure when oversampling is performed in the A / D converter according to the present embodiment is the same as that of the second embodiment except for the output timing of the latch pulse, and detailed description thereof is omitted.

  As described above, according to the mode for carrying out the present invention, the timing of the first latch pulse LP1 at the time of oversampling is applied to the timing of the second and subsequent latch pulses LPs, and the signal of the output stage number comparison circuit Since the process can be simplified, it is possible to suppress an increase in power consumption accompanying oversampling.

  In addition, after the first output of the latch pulse LP1, it is possible to further reduce power consumption by adding a function of stopping the third pulse delay circuit, the third pulse stage number detection circuit, and the level shift circuit. It becomes.

  In this embodiment, the timing of the first latch pulse LP1 is applied to the second and all subsequent timings. However, the present invention is not limited to a specific number, and the latch pulse calculated by comparing the number of output stages. Anything that applies this timing to the timing of a later latch is included in the present invention.

  As described above, according to the mode for carrying out the present invention, the number of passing stages of the delay unit (in accordance with the magnitude of the analog input voltage (in order to compensate for the curve (nonlinearity)) of the conventional input / output characteristics) A) having good linearity input / output characteristics without actually A / D converting a large number of reference voltages in order to approximate the input / output characteristics linearly. A / D conversion device can be provided.

Further, by calculating and outputting the result of continuous A / D conversion, it is possible to obtain a more accurate A / D conversion result.
It is also possible to reduce power consumption when performing continuous A / D conversion.

  The embodiment of the present invention has been described above with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes various modifications within the scope of the present invention. It is.

DESCRIPTION OF SYMBOLS 10 A / D converter 1 1st pulse delay circuit 2 1st pulse passage stage number detection circuit 3 Latch timing control part 4 Output encoder 31 3rd pulse delay circuit 32 3rd pulse passage stage number detection circuit 33 Level shift circuit 34 Output stage number comparison circuit 41 1st latch & encoder 42 2nd latch & encoder 43 Subtractor 7 2nd pulse delay circuit 8 2nd pulse passage stage number detection circuit 5 Signal processing part 51 Memory circuit 52 Operation circuit 6 Latch Pulse generation circuit 100 Operational amplifier 101 PMOS transistor 102 Resistance 103, 104 NMOS transistor 105 Current source 20 A / D converter 30 A / D converter 341 Output stage number comparison circuit

Claims (4)

An A / D converter that converts an analog input voltage into a digital signal,
A first pulse delay circuit in which a plurality of delay units for delaying the first pulse signal with a delay time corresponding to the magnitude of the analog input voltage are connected;
A second pulse delay circuit in which a plurality of delay units for delaying the second pulse signal with a delay time corresponding to the magnitude of the analog reference voltage are connected;
A first pulse passage stage number detection circuit that detects the number of stages that the first pulse signal has passed through a delay unit in the first pulse delay circuit in a predetermined time;
A second pulse passage stage number detection circuit that detects the number of stages that the second pulse signal has passed through the delay unit in the second pulse delay circuit at a predetermined time;
An output unit that outputs a digital signal indicating a difference in the number of stages of the delay unit detected by the first pulse passing stage number detection circuit and the number of stages of the delay unit detected by the second pulse passing stage number detection circuit;
A timing control unit for determining the predetermined time according to the magnitude of the analog input voltage;
An A / D conversion device comprising: The timing controller is
A third stage in which a plurality of delay units that delay the third pulse signal with a delay time corresponding to the magnitude of the level shift voltage level-shifted so as to increase or decrease linearly with respect to the analog input voltage is provided. A pulse delay circuit of
A third pulse passage stage number detection circuit that detects the number of stages that the third pulse signal passes through the delay unit in the third pulse delay circuit in a predetermined time;
Timing determination unit for determining the predetermined time so that a difference between the number of delay unit stages detected by the first pulse passing stage number detection circuit and the number of delay unit stages detected by the third pulse passing stage number detection circuit is constant. When,
The A / D converter according to claim 1, comprising: The output unit is
The number of stages of the delay unit is detected a plurality of times, and a digital signal obtained by calculating the detection results of the plurality of times is output.
The A / D converter according to claim 1 or 2, wherein diverting the predetermined time determined at the m-th time as a predetermined time after the (m + 1) -th time,
The A / D converter according to claim 3.

Images