JPH077431A - A/d conversion circuit - Google Patents

Abstract

PURPOSE:To eliminate the necessity of an analog switch or the like and to attain high speed processing by executing signal processing in a serial type A/D conversion system based upon a current mode. CONSTITUTION:A V-I converter 11 converts input analog voltage Vin into a current signal Iin and V-I converters 121 to 12n respectively convert reference voltage Vref corresponding to the full scale value of the input voltage Vin into current signals 2<-1>.Iref to 2<-n>.Iref. The input current Iin is subtracted from 2<-1>.Iref, the subtracted result is converted into an absolute value, the absolute value output is subtracted from 2<-2>.Iref, the operation is repeated n-bit times, the polarity judging results of respective subtracted results are logically converted to obtain an n-bit digital signal. The absolute value of the digital signal is obtained by circuits 161 to 16n consisting of the 1st current mirror enabled to enter the current of a subtracted result with one polarity and disabled from entering the subtracted result of the other polarity, the 2nd current mirror for inverting the polarity of an output from the 1st current mirror and the 3rd current mirror for entering the output of the 2nd current mirror and a current to be the subtracted result of the other polarity and outputting the current as a current with the same polarity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to an A / D conversion circuit that encodes a bit digital signal.

[0002]

2. Description of the Related Art Various A / D conversion systems have been proposed in the past, and one of them is a serial A / D conversion system. This is because the input analog voltage V _in is set to a level corresponding to MSB, that is, 2 as shown in FIG.
⁻¹ · V _ref, and if V _in <2 ⁻¹ · V _ref (1), it is MSB a ₁ = “0”, otherwise a ₁
= "1". V _ref is a reference voltage corresponding to the full scale of the input analog voltage V _in . The raw voltage value in the former case as the output voltage V _out1, also in the latter case, passes the V _out1 = V _in -2 output voltage V _out1 of ^-1 · V _ref (2) to the next stage.

Then, in the next stage, this output voltage V _out1 is
Compare with the level corresponding to SB-1, that is, 2 ⁻² · V _ref, and if V _out1 <2 ⁻² · V _ref (3), the bit a ₂ of MSB-1 is “0”, otherwise 1 ”. In the former case, the voltage value as it is is used as the output voltage V _out2 , and in the latter case, the voltage value V _out2 of V _out2 = V _out1 −2 ⁻² · V _ref (4) is passed to the next stage.

[0004] Hereinafter, the same processing is repeatedly, a _1, a ₂ is a comparison result, ........, obtain a _n. This becomes the digital values b ₁ , b ₂ , ..., B _{n of the} MSB to LSM that should be obtained as they are.

That is, in the system shown in FIG. 9, the input analog voltage is compared with a voltage which is 2 ⁻¹ times the reference voltage corresponding to the full scale of the input analog voltage, and the comparison result is compared with the reference voltage. Input voltage as it is or 2 of reference voltage
^{The minus} voltage and the subtracted voltage are sent to the subsequent stage as a new input voltage, which is repeated for n bits, and each comparison result is converted into an n bit digital signal.

FIG. 10 is a functional block diagram for realizing this serial A / D conversion system. Here, the input analog voltage V _in is the MSB level of 2 by the comparator 1 ₁ .
Is compared with ^-1 · V _ref, the comparison result becomes a digital value b ₁ of temporarily stored in the latch 2 ₁ MSB.

At this time, when the comparison result satisfies the above expression (1), that is, when a ₁ = “0”, the input analog voltage V _in passes through the subtractor 3 ₁ as it is and is input to the next stage. However, when the formula (1) is not satisfied, that is, a ₁ =
When the value is "1", the analog switch 4 ₁ is turned on, the above formula (2) is executed in the subtractor 3 ₁ , and the voltage value V _out1 obtained here is input to the next stage.

The analog voltage input to the next stage is the comparator 1 ₂
Is compared with the level corresponding to MSB-1 of 2 ⁻² · V _ref, and the result is temporarily held in latch 2 ₂
It becomes the digital value b ₂ of B-1.

At this time, when the comparison result satisfies the above expression (3), that is, when a ₂ = “0”, the voltage V _out1 input to the relevant stage passes through the subtractor 4 ₂ as it is and further. When inputting to the next stage, when the expression (3) is not satisfied, that is, when a ₂ = “1”, the analog switch 4 ₂ is turned on and the subtracter 4 ₂ executes the above expression (4). .

In the same manner, when a resolution of n bits is provided, similar processing is performed up to n stages, and digital values b ₁ , b ₂ corresponding to MSB to LSB obtained by A / D converting the input analog voltage Vin. ..., so that b _n is obtained.

[0011]

However, the above-mentioned conventional A / D conversion method performs the processing in the voltage mode, and in particular, the circuit shown in FIG. 10 requires the analog switch 4. There was a significant delay in this part, and it was difficult to increase the speed.

The present invention has been made in view of the above circumstances, and an object thereof is to provide an A / D conversion circuit capable of achieving high speed.

[0013]

To this end, the present invention subtracts an input analog current by a current which is 2 ^-1 times the reference current corresponding to the full scale of the input analog current, and the subtraction result is an absolute value. The absolute value output, subtraction is performed with a current that is 2 ^-2 times the reference current, and this is repeated for n bits, the polarity of each subtraction result is determined, and the determination result is logically determined. An A / D conversion circuit, characterized by converting to obtain an n-bit digital signal, wherein:
A first current mirror that takes in the current of the subtraction result of one polarity and does not take in the result of the subtraction of the other polarity;
A second current mirror for inverting the polarity of the output of the current mirror, and a third current mirror for taking in the output of the second current mirror and the current of the subtraction result of the other polarity and outputting it as a current of the same polarity. It is configured to be executed by a circuit consisting of.

[0014]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is an explanatory view of the operation of the embodiment. In this embodiment,
The input analog current I _in is first subtracted by 2 ⁻¹ · I _ref which is a level corresponding to MSB. I _ref is a reference current corresponding to the full scale value of the input analog current I _in . I _out1 = I _in −2 ⁻¹ · I _ref (5) The output current I _out1 which is the result of this calculation is obtained as a positive or negative analog current value, but its polarity is positive, that is, I _in
If it is> 2 ⁻¹ · I _ref , a ₁ = “1”, and if it is negative, a ₁ = “0”. And when it is positive, it is as it is,
When the value is negative, the value is inverted to be an absolute value, that is, converted into a positive value, and in any case, it is sent to the next stage.

In the next stage, subtraction is performed to calculate I _out2 = I _out1 -2 ^-2 · I _ref (6) and the same processing as above is performed. If the polarity is positive, a ₂ = " 1 ”, and if negative, a ₂ =“ 0 ”
And Then, when it is positive, it is as it is, and when it is negative, the value is inverted to be an absolute value, and in any case, it is sent to the next stage.

The above processing is repeated, and the comparison result a ₁
~ A _n , decode this value, MSB ~ LS
Get the digital value of M.

FIG. 2 is an explanatory diagram in which this is logically formulated. Here, the input analog current I _in is expressed as b ₁ 2 ^-1 + b ₂ 2 ^-2 + b ₃ 2 ^-3 + ... + b _n 2 ^-n +
.alpha. (.alpha .: arbitrary value), each subtraction output and absolute value output are sequentially shown from the MSB. There are always two types of absolute value output of processed analog values, and they do not change even if the number of bits increases. This is clear from the principle of 0's complement.

FIG. 3 shows the digital values to be obtained from this logical expression. Here, the comparison result a ₁ ~
The relationship between a _n and the digital values b _{1 to} b _n corresponding to the MSB to LSM to be finally obtained is clear. this is,
After being once converted into a voltage signal, b _{1 to} b _n are derived by continuous processing of the EX / NOR gate. in this way,
An accurate digital value can be derived by the logical conversion of the continuous and comparison outputs of the series of processing of subtraction and absolute value conversion from the MSB.

FIG. 4 is a block diagram of a specific circuit of the n-bit A / D converter to do this based on the theory described above, 11 V-I converting an input analog voltage V _in into a current signal converter, 12 ₁ to 12 _n is V-I converter for converting the reference voltage V _ref corresponding to the full-scale value of the input voltage V _in to a current signal of a predetermined ratio, _131-134
n is a differential current detector that performs subtraction, 14 _{1 to} 14 _n is an IV converter that converts the obtained differential current into a voltage, 15 ₁ to 15
_n is a comparator with a latch function, 16 _{1 to} 16 _n are absolute value conversion circuits, and 17 is an encoder.

In this circuit, the difference current detector 13 ₁ performs the subtraction of the equation (5), and the resulting output current I _out1 is converted into a voltage signal by the IV converter 14 ₁ , The logical judgment is made by the comparator 15 ₁ . Output current I _out1
Is positive, the output of the comparator 15 ₁ is a ₁ =
To "1", the negative when a ₁ = becomes "0", input to the encoder 17.

This output current I _out1 passes through the absolute value circuit 16 ₁ as it is when it is positive, and is converted into a positive value by the absolute value circuit 16 ₁ when it is negative. From
The difference current detector 13 ₂ in the next stage is input and the equation (6) is calculated.

After that, when the same operation is performed up to the LSB level and the outputs a ₁ to a _n of the comparators 15 ₁ to 15 _n are obtained, the outputs a _{1 to} a _n are encoded by the encoder 17, Digital outputs b _{1 to} b _n are obtained. b ₁ is a value corresponding to MSB, and b _n is a value corresponding to LSB.

FIG. 5 is a concrete circuit diagram of the differential current detector 12 ₁ and the absolute value conversion buffer circuit 15 ₁ described above. Here, D1 and D2 are diodes, Q1 to Q3 are transistors forming a current mirror circuit, Q4 to Q6 are transistors forming another current mirror, and Q7 to Q9 are transistors forming another current mirror, Q10 and Q3.
Reference numeral 11 is a transistor forming a push-pull circuit, 30
Is a conversion comparator having the functions of the IV converter 14 ₁ and the comparator 15 ₁ , R1 to R8 are resistors, and Ia ₁ , Ia ₂ , and Ib are constant current sources. The constant current source is Ia ₁ = Ia
₂ and Ib = Ia ₁ + Ia ₂ .

In this circuit, when I _in > 2 ⁻¹ · I _ref , the diode D1 is turned on, the diode D2 is turned off, and the difference current i _d1 (= I _in −) is applied to the diode D1 and the collector of the transistor Q1. 2 ⁻¹ · I _ref ) and Ia ₁ flow, and these become collector currents of the transistors Q2 and Q5. The current Ia ₂ is applied to the collector of the transistor Q8.
Flows. Therefore, at the point A, Ib = i _out1 + _{id 1} + Ia ₁ + Ia ₂ . Since Ib = Ia ₁ + Ia ₂ , I _out1 = −id ₁ (7).

Further, at this time the collector of transistor Q10 flows current "i _d1 + Ia _1", since the collector of the transistor Q11 flows through the constant current Ia _2, current i _s flowing out from the conversion comparator 30, i _s = −i _d1 (8).

On the other hand, when I _in <2 ^-1 · I _ref , the diode D1 is turned off, the diode D2 is turned on, and the differential current i _d2 flows through the diode D2, so that the transistor Q
The collector currents of 7 and Q8 are Ia + _id2 . Therefore A
In point, the _{Ib = i out1 + i d2 +} Ia 1 + Ia 2, I out1 = -i d2 (9) , and becomes the same as the same polarity current and i _d1 shown in equation (7).

At this time, Ia ₁ flows through the collector of the transistor Q10 and a current "Ia ₂ + id ₂ " flows through the collector of the transistor Q11. Therefore, the conversion comparator 3
The current i _s flowing from 0 becomes i _s = id ₂ (10), the input to the logic converter 30 is inverted with respect to the expression (8), and the logic judgment can be performed.

FIG. 6 is a circuit diagram of another example of the differential current detector 13 ₁ . D3 and D4 are diodes, Q12 to Q15 are transistors forming a current mirror, and Q16 to Q1.
9 is a transistor forming another current mirror, Q2
0 to Q23 are transistors forming another current mirror circuit, and Ic and Id are constant current sources. Note that Ic = I
d.

In the differential current detector of FIG. 6, I _in > 2 ^-1
When I _ref , the diode D3 is turned on, the diode D4 is turned off, a differential current i _d3 flows through the diode D3, and the collector currents of the transistors Q18, Q19, Q20, and Q21 are i _d3 + Ic. Therefore, the point B, but the _{Id = I out1 + i d3 +} Ic, since it is Ic = Id, the I _out1 = -i _d3.

When I _in > 2 ⁻¹ · I _ref , the diode D3 is turned off, the diode D4 is turned on, and the differential current i _d4 flows through the diode D4, so that the transistor Q
The collector currents of 19, Q20 and Q21 are i _d4 + Ic. Therefore, also at this time, I _out1 = −i _d4 .

FIG. 7 is a circuit diagram of the internal configuration of the encoder 17. This circuit has an EX-NOR gate 171 ₂
, 171 _n , and latch circuits 172 _{1 to} 172 _n ,
The code conversion shown in FIG. 3 is performed. In the encoder 17, the latch circuits 142 _{1 to} 142 _n operate with the same clock, and the output timings of the digital outputs are matched.

By the way, in the A / D converter explained in FIG. 4, the reference current input to the differential current detector 13 ₁ , ... Is L.
The closer it is to the SB side, the smaller it becomes, and the level of the output current to be compared also becomes smaller. Therefore, a highly accurate element is required to detect the difference current, and
The same applies to the circuit that generates the reference current.

FIG. 8 is a block diagram of a concrete circuit of an A / D converter according to another embodiment which is intended to improve such a point.
Here, the input current I _in is multiplied by K ₁ and input, and M
The reference current 2 ⁻¹ · I _ref corresponding to SB is also input K ₁ times, and the difference current detector 13 ₁ detects the difference. In the absolute value conversion circuit 16 ₁ , the output current I _out1 obtained by amplifying with the gain K ₂ is passed to the next MSB-1 stage regardless of the polarity of the polarity.

In this stage, the reference current 2 ^-2 · I _ref input to the differential current detector 13 ₂ is multiplied by K ₂ ′ and input. At this time, the gain of the output current I _out1 is K ₁ · K ₂ times that of the original level (the level at I _in ), so that the gain K ₂ ′ of the reference current 2 ^-2 · I _ref is also increased. Correspondingly, K ₂ ′ = K ₁ · K ₂ . The above operation is similarly performed up to the LSB. Others are the same as those described in FIG.

According to this embodiment, it is not necessary to perform subtraction with a minute voltage, and highly accurate processing can be performed.
At this time, the magnifications of the absolute value conversion circuits 16 _{1 to} 16 _n are arbitrary and are not affected by the reference voltage of the preceding stage or the following stage.

As described above, according to the present invention, since the signal processing is performed in the current mode, an analog switch or the like is not necessary and the overall operation speed can be increased. Also, by giving the same gain to both current signals in the portion for extracting the difference current, it is possible to convert a minute signal into a large signal and handle it, so that highly accurate processing can be performed,
It becomes possible to perform accurate A / D conversion.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of signal processing of an A / D converter of the present invention.

FIG. 2 is an explanatory diagram of logic expansion of the same A / D converter.

FIG. 3 is an explanatory diagram of logic conversion of the same A / D converter.

FIG. 4 is a functional block diagram of a circuit configuration of the same A / D converter.

FIG. 5 is a circuit diagram of a specific circuit of a differential current detector and an absolute value conversion circuit of the same A / D converter.

FIG. 6 is a specific circuit diagram of another example of the absolute value conversion circuit of the A / D converter.

FIG. 7 is a circuit diagram of a specific circuit of an encoder.

FIG. 8 is a functional block diagram of another circuit configuration of the same A / D converter.

FIG. 9 is an explanatory diagram of signal processing of a conventional A / D conversion method.

FIG. 10 is a functional block diagram of a circuit configuration of a conventional A / D conversion system.

[Explanation of symbols]

_{1 1 ~1 n, 2 1 ~2} n: comparator, 3 ₁ to 3 _n: subtracter, 4 ₁ to 4 _n: an analog switch, 11, 12 ₁ to 1
2 _n : V-I converter, 13 _{1 to} 13 _n : differential current detector,
14 _{1 to} 14 _n : I-V converter, 15 ₁ to 15 _n : comparator with latch function, 16 _{1 to} 16 _n : absolute value buffer circuit, 17: encoder.

Claims (2)

[Claims] 1. An input analog current is subtracted by a current that is 2 ⁻¹ times the reference current corresponding to the full scale of the input analog current, and the result of the subtraction is absolute valued, and the absolute value output is obtained. And subtracting with a current of 2 ^-2 times the reference current, repeating this for n bits, determining the polarity of each subtraction result, and logically converting the determination result to obtain an n-bit digital signal. An A / D conversion circuit characterized by: a first current mirror for capturing the current of the subtraction result of one polarity and not capturing the subtraction result of the other polarity for the above absolute value conversion; A second current mirror that inverts the polarity of the output of the current mirror; and a third current mirror that takes in the output of the second current mirror and the current of the subtraction result of the other polarity and outputs it as a current of the same polarity. Run in the circuit A / D converter circuit according to claim Rukoto 2. The A according to claim 1, wherein the subtracted currents have the same gain of more than one.
/ D conversion circuit.