JP2010243988A - Driving circuit and driving method, and electrooptical dive and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To display a high quality image in an electrooptical device such as a liquid crystal device. <P>SOLUTION: A driving circuit drives the electrooptical device (100) by outputting an image signal serial-parallel converted to m-series via m pieces of image signal lines to a plurality of data lines 6a. The driving circuit includes: an image signal output means for outputting m-series of image signals to the m pieces of image signal lines 300; and an image signal distribution means 7 by supplying the m-series of image signals by distributing them for each data line group including m pieces of data lines, to the plurality of data lines. Here, the image signal distribution means distributes the m-series of image signals so that they are supplied in different timing to adjacent data lines of the plurality of data lines. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a driving circuit and a driving method for driving an electro-optical device such as a liquid crystal display device, an electro-optical device including the driving circuit, and an electronic apparatus such as a liquid crystal projector including the electro-optical device. Technical field.

  As an electro-optical device to which this type of drive circuit is applied, for example, there is a device that distributes and supplies an image signal serial-parallel converted into a plurality of series to each data line (so-called phase expansion drive). . When phase expansion driving is performed, series unevenness may occur in the displayed image due to parasitic capacitance, pushdown, or the like of the image signal line. For this reason, for example, a technique has been proposed in which an image signal supplied to a data line located at the boundary of a phase development series block is corrected so as to reduce unevenness according to a gradation value (Patent Document 1). reference).

JP 2006-47971 A

  However, in the above-described technique, since it is required to perform a predetermined correction process on the image signal, the processing on the image signal increases, and the load on the processing capability of the apparatus increases. In addition, since it is required to provide a correction circuit for performing correction processing, the circuit configuration of the apparatus is also highly complicated. That is, the above-described technique has a technical problem that various inconveniences may occur instead of improving the image quality.

  SUMMARY An advantage of some aspects of the invention is that it provides a driving circuit and a driving method capable of displaying a high-quality image, an electro-optical device, and an electronic apparatus. To do.

  In order to solve the above problems, the drive circuit according to the present invention performs serial-parallel conversion into m series via m (where m is a natural number of 2 or more) image signal lines for a plurality of data lines. A driving circuit for driving the electro-optical device by outputting a signal, the image signal output means for outputting the m-sequence image signal to the m image signal lines, and the m-sequence image signal, An image signal distribution unit that distributes and supplies the plurality of data lines for each data line group including m data lines, and the image signal distribution unit includes: The m-sequence image signals are distributed so that they are supplied to data lines adjacent to each other at different timings.

  According to the driving circuit of the present invention, at the time of the operation, the image signal that has been serial-parallel converted into m series by the image signal output means is output to the m image signal lines. That is, the data signal is divided into m series and output to the electro-optical device. The image signals output to the m image signal lines are distributed by the image signal distribution unit, and are supplied to the plurality of data lines for each data line group including m data lines. Note that “m” is a natural number of 2 or more, and is a value smaller than the total number of data lines, preferably a multiple of m is the total number of data lines.

  With the above-described configuration, the electro-optical device can simultaneously write data signals to a plurality of pixels, and can sufficiently secure a time for writing a data voltage to each pixel. Therefore, for example, even in an electro-optical device having a high-resolution panel, stable display is possible.

  In the present invention, in particular, the m-sequence image signal is distributed by the image signal distribution means so as to be supplied to the adjacent data lines among the plurality of data lines at different timings. In other words, image signals are not supplied to adjacent data lines at the same timing. Here, “different timing” does not mean that there is no period in which image signals are simultaneously supplied to mutually adjacent data lines, but the start and end of supply of image signals. It is assumed that at least one of timings is different from each other.

  Here, if image signals are supplied to adjacent data lines at the same timing, for example, due to capacitive coupling between the data line located at the end of each series in the display area and the other data lines. There may be a difference in the write voltage and a difference in the amount of pushdown.

  However, in the present invention, in particular, as described above, the image signals are not supplied to the adjacent data lines at the same timing. As a result, it is possible to extremely effectively reduce the influence of capacitive coupling of the image signal lines, variations in pushdown, and the like. Therefore, it is possible to prevent the occurrence of uneven stripes along the boundaries of each series due to capacitive coupling and pushdown.

  If the supply timings for the odd-numbered data lines and the even-numbered data lines are different from each other, the timing for supplying the image signal is not different for all the data lines. The above-described image signal distribution can be realized. That is, the image signals may be supplied simultaneously by skipping one data line. Further, even if the image signals are supplied simultaneously at a predetermined interval such as two jumps or three jumps, the same effect can be obtained even if they are not skipped by one.

  As described above, according to the drive circuit of the present invention, it is possible to reduce the series unevenness in the phase expansion drive and display a high-quality image.

  In one aspect of the drive circuit of the present invention, the timings at which the m-sequence image signals are supplied to the adjacent data lines at least partially overlap each other.

  According to this aspect, since the timings at which m-sequence image signals are supplied overlap, the period for supplying each image signal can be set longer. Accordingly, it is possible to prevent an image signal writing period from being insufficient. Here, “overlapping” means that supply of image signals to one data line is started, and supply of image signals to other data lines is started before this supply is completed. It means a case. That is, it means that there is at least a period in which image signals are simultaneously supplied in adjacent data lines.

  By preventing the writing period from being insufficient, display unevenness caused by insufficient writing can be reduced. Therefore, in this aspect, it is possible to display a higher quality image.

  In another aspect of the drive circuit of the present invention, the image signal distribution means includes a transistor whose opening / closing is controlled by a gate signal, and an inverted signal obtained by inverting the gate signal is provided on the drain side of the transistor. Capacitively coupled.

  According to this aspect, the image signal distribution unit includes the transistor, and the image signal is distributed by controlling the opening and closing of the transistor. Specifically, conduction to each data line is controlled by opening and closing the transistor, and an image signal can be selectively supplied to each data line. The opening and closing of the transistor is controlled, for example, by supplying a pulsed gate signal.

  Particularly in this embodiment, an inverted signal obtained by inverting the gate signal is capacitively coupled to the drain side (that is, the side opposite to the source) of the transistor. Therefore, it is possible to prevent the occurrence of pushdown due to the parasitic capacitance generated between the gate signal line to which the gate signal is supplied and the data line. That is, the pushdown amount can be reduced.

  By reducing the push-down amount, display unevenness due to push-down can be reduced. Therefore, in this aspect, it is possible to display a higher quality image.

  In another aspect of the drive circuit of the present invention, the image signal distribution means includes a CMOS (Complementary Metal Oxide Semiconductor) type circuit.

  According to this aspect, since the image signal distribution means includes the CMOS circuit, the push-down amount can be reduced similarly to the aspect in which the inverted signal is capacitively coupled. Therefore, in this aspect, it is possible to display a higher quality image.

  In order to solve the above problems, an electro-optical device according to the present invention includes the above-described drive circuit according to the present invention (including various aspects thereof).

  According to the electro-optical device of the present invention, since the drive circuit according to the present invention described above is provided, it is possible to effectively reduce the series unevenness in the phase expansion drive. Therefore, it is possible to display a high quality image.

  In the electro-optical device of the present invention, the drive circuit may be provided, for example, on an element substrate that sandwiches an electro-optical material, or provided on another substrate that is electrically connected to the element substrate. It may be.

  In order to solve the above problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention.

  According to the electronic apparatus of the present invention, since the electro-optical device according to the present invention described above is included, a projection display device, a television set, a mobile phone, an electronic notebook, a word processor capable of performing high-quality display. Various electronic devices such as a viewfinder type or a monitor direct view type video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized. In addition, as an electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper can be realized.

  In order to solve the above-described problem, the driving method of the present invention performs serial-parallel conversion to m series via m (where m is a natural number of 2 or more) image signal lines for a plurality of data lines. A driving method of driving an electro-optical device by outputting a signal, the image signal output step of outputting the m-sequence image signal to the m image signal lines, and the m-sequence image signal, An image signal distribution step that distributes and supplies the plurality of data lines for each data line group composed of m data lines, and in the image signal distribution step, among the plurality of data lines, The m-sequence image signals are distributed so as to be supplied to mutually adjacent data lines at different timings.

  According to the driving method of the present invention, as in the case of the driving circuit of the present invention described above, it is possible to effectively reduce series unevenness in phase expansion driving. Therefore, it is possible to display a high quality image.

  In the driving method of the present invention, it is possible to adopt various aspects similar to the various aspects of the driving circuit of the present invention described above.

  The effect | action and other gain of this invention are clarified from the form for implementing invention demonstrated below.

1 is a plan view illustrating an overall configuration of an electro-optical device according to an embodiment. It is the HH 'sectional view taken on the line of FIG. 1 is a block diagram illustrating an electrical configuration of an electro-optical device according to an embodiment. FIG. 3 is an equivalent circuit diagram of a pixel unit of the electro-optical device according to the embodiment. It is a timing chart which shows the drive method concerning a 1st embodiment. It is a timing chart which shows the drive method concerning a comparative example. It is a top view which shows notionally the display nonuniformity in an image display area. FIG. 6 is a block diagram illustrating a specific configuration of an electro-optical device according to a second embodiment. It is a timing chart which shows the drive method concerning a 2nd embodiment. It is a circuit diagram which shows the structure of the drive circuit which concerns on 3rd Embodiment. It is a top view which shows the structure of the projector which is an example of the electronic device to which the electro-optical apparatus is applied.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<Electro-optical device>
First, an electro-optical device driven by the drive circuit of the present invention will be described with reference to FIGS. In the following embodiments, a drive circuit built-in TFT (Thin Film Transistor) active matrix drive type liquid crystal device, which is an example of the electro-optical device of the present invention, is taken as an example.

  The overall configuration of the electro-optical device according to this embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the overall configuration of the electro-optical device according to this embodiment, and FIG. 2 is a cross-sectional view taken along the line HH ′ of FIG.

  1 and 2, in the electro-optical device 100 according to this embodiment, the TFT array substrate 10 and the counter substrate 20 are disposed to face each other. The TFT array substrate 10 is, for example, a transparent substrate such as a quartz substrate or a glass substrate, a silicon substrate, or the like. The counter substrate 20 is a transparent substrate such as a quartz substrate or a glass substrate. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between a pair of alignment films.

  The TFT array substrate 10 and the counter substrate 20 are bonded to each other by a sealing material 52 provided in a sealing region located around the image display region 10a provided with a plurality of pixel electrodes.

  The sealing material 52 is made of, for example, an ultraviolet curable resin, a thermosetting resin, or the like for bonding the two substrates, and is applied on the TFT array substrate 10 in the manufacturing process and then cured by ultraviolet irradiation, heating, or the like. It is. In the sealing material 52, a gap material such as glass fiber or glass beads for dispersing the distance between the TFT array substrate 10 and the counter substrate 20 (that is, the inter-substrate gap) to a predetermined value is dispersed. Note that the gap material may be arranged in the image display region 10a or a peripheral region located around the image display region 10a in addition to or instead of the material mixed in the seal material 52.

  A light-shielding frame light-shielding film 53 that defines the frame area of the image display area 10a is provided on the counter substrate 20 side in parallel with the inside of the seal area where the sealing material 52 is disposed. A part or all of the frame light shielding film 53 may be provided as a built-in light shielding film on the TFT array substrate 10 side.

  A sampling circuit 7 that samples the image signal on the image signal line and supplies the data line to the data line, a data line driving circuit 101, and an external circuit in an area located outside the seal area where the seal material 52 is disposed in the peripheral area Connection terminals 102 are provided along one side of the TFT array substrate 10. The scanning line driving circuit 104 is provided along two sides adjacent to the one side so as to be covered with the frame light shielding film 53. Further, in order to connect the two scanning line driving circuits 104 provided on both sides of the image display area 10 a in this way, a plurality of the pixel lines are covered along the remaining side of the TFT array substrate 10 and covered with the frame light shielding film 53. Wiring 105 is provided.

  In regions facing the four corners of the counter substrate 20 on the TFT array substrate 10, vertical conduction terminals 106 for connecting the two substrates with the vertical conduction material 107 are disposed. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  In FIG. 2, on the TFT array substrate 10, a laminated structure in which pixel switching TFTs as drive elements, wiring lines such as scanning lines and data lines are formed is formed. Although the detailed configuration of this laminated structure is not shown in FIG. 2, pixel electrodes 9a made of a transparent material such as ITO (Indium Tin Oxide) are provided on the laminated structure with a predetermined pattern for each pixel. It is formed in an island shape.

  The pixel electrode 9 a is formed in the image display area 10 a on the TFT array substrate 10 so as to face the counter electrode 21. On the surface of the TFT array substrate 10 facing the liquid crystal layer 50, that is, on the pixel electrode 9a, an alignment film 16 is formed so as to cover the pixel electrode 9a.

  A light shielding film 23 is formed on the surface of the counter substrate 20 facing the TFT array substrate 10. For example, the light shielding film 23 is formed in a lattice shape when viewed in plan on the facing surface of the facing substrate 20. In the counter substrate 20, a non-opening area is defined by the light shielding film 23, and an area partitioned by the light shielding film 23 is an opening area through which light emitted from, for example, a projector lamp or a direct viewing backlight is transmitted. The light shielding film 23 may be formed in a stripe shape, and the non-opening region may be defined by the light shielding film 23 and various components such as data lines provided on the TFT array substrate 10 side.

  On the light shielding film 23, a counter electrode 21 made of a transparent material such as ITO is formed so as to face the plurality of pixel electrodes 9a. Further, in order to perform color display in the image display area 10a, a color filter (not shown in FIG. 2) may be formed on the light shielding film 23 in an area including a part of the opening area and the non-opening area. Good. An alignment film 22 is formed on the counter electrode 21 on the counter surface of the counter substrate 20.

  In addition to the above-described driving circuits such as the data line driving circuit 101 and the scanning line driving circuit 104, a plurality of data lines are precharged at a predetermined voltage level on the TFT array substrate 10 shown in FIGS. A precharge circuit for supplying a signal prior to an image signal, an inspection circuit for inspecting quality, defects, and the like of the electro-optical device 100 during manufacture or at the time of shipment may be formed.

  Next, an electrical configuration of the electro-optical device according to the present embodiment will be described with reference to FIGS. 3 and 4. FIG. 3 is a block diagram showing an electrical configuration of the electro-optical device according to this embodiment, and FIG. 4 is an equivalent circuit diagram of a pixel portion of the electro-optical device according to this embodiment.

  In FIG. 3, as described above, the electro-optical device 100 according to the present embodiment is configured by arranging the scanning line driving circuit 104, the data line driving circuit 101, and the sampling circuit 7 around the image display region 10a. Yes.

  The image display area 10a is an area in which the pixel portions 600 are arranged. In this embodiment, 1088 rows of scanning lines 11a are provided in the horizontal direction (that is, the X direction), and 1984 columns of data lines 6a are provided. It is provided in the vertical direction (that is, the Y direction). A pixel portion 600 is provided so as to correspond to each intersection of the scanning line 11a and the data line 6a. Therefore, in the present embodiment, the pixel units 600 are arranged in a matrix of 1088 rows x 1984 columns in the image display region 10a, but the present invention is not limited to this arrangement.

  As shown in FIG. 4, the pixel portion 600 includes a pixel switching TFT 30, a liquid crystal element 72, and a storage capacitor 70.

  The pixel switching TFT 30 has a source electrically connected to the data line 6a, a gate electrically connected to the scanning line 11a, and a drain electrically connected to a pixel electrode 9a of a liquid crystal element 72 described later. The pixel switching TFT 30 is turned on and off by a scanning signal supplied from the scanning line driving circuit 104.

  The liquid crystal element 72 includes a pixel electrode 9 a, a counter electrode 21, and a liquid crystal sandwiched between the pixel electrode 9 a and the counter electrode 21. In the liquid crystal element 72, a data signal of a predetermined level written in the liquid crystal via the data line 6a and the pixel electrode 9a is held with the counter electrode 21 for a certain period. The liquid crystal modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel, and in the normally black mode, the light is incident according to the voltage applied in units of each pixel. The light transmittance is increased, and light having a contrast corresponding to the image signal is emitted from the liquid crystal device 100 as a whole.

  The storage capacitor 70 is added in parallel with a liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode in order to prevent the held image signal from leaking.

  Since the pixel portions 600 as described above are arranged in a matrix in the image display region 10a, active matrix driving is possible. The configurations and operations of the scanning line driving circuit 104, the data line driving circuit 101, and the sampling circuit 7 will be described in detail below.

<Drive circuit and drive method>
Next, a driving circuit and a driving method for driving the above-described electro-optical device will be described with reference to FIGS. 5 to 10 in addition to FIG. In the following description, three types of drive circuits having different configurations will be described as examples.

<First Embodiment>
First, the configuration of the drive circuit according to the first embodiment will be described with reference to FIG.

  3, the scanning line driving circuit 104 has a shift register, and the scanning signals G1, G2, G3,... G1088 is supplied. Specifically, the scanning line driving circuit 104 sequentially selects the scanning lines 11a in the first, second, third,..., 1088 rows over a period of one frame and selects a scanning signal to the selected scanning line. The H level corresponding to the voltage is set, and the scanning signals to the other scanning lines are set to the L level corresponding to the non-selection voltage.

  The data line driving circuit 101 includes a shift register 400, an enable signal supply line 510 that supplies enable signals ENB1 to ENB4, a plurality of AND circuits 520, an NRG supply line 530 that supplies a signal NRG, and a plurality of OR circuits. 540.

  The AND circuit 520 first obtains a logical product of the signals output from the shift register 400 with the enable signals ENB1 to ENB4, and as a result, the logical product signal is output to the OR circuit 540 in the subsequent stage. The OR circuit 540 obtains a logical sum of the logical product signal and the signal NRG, and outputs the logical sum signal to the sampling circuit 7 as a result.

  The sampling circuit 7 is an example of the “image signal distribution unit” of the present invention, and includes a plurality of image signal lines 300 for supplying an image signal output from an image signal output circuit (not shown) and a transistor 71. Has been.

  Twelve image signal lines 300 are provided corresponding to the image signals VID1 to VID12. That is, in this embodiment, the image signal is serial-parallel converted into 12 series. Such serial-parallel conversion may be performed by a circuit provided on the TFT array substrate 10 or by a circuit provided outside (for example, on a flexible substrate connected to the electro-optical device). Also good.

  The transistor 71 is, for example, an n-channel thin film transistor (TFT), and is provided for each of the data lines 6a in 1 to 1984 columns. The transistors 71 are controlled by signals supplied from the data line driving circuit 101 and function as sampling switches.

  In the present embodiment, the logical sum signal output from one OR circuit 540 is supplied to the plurality of transistors 71 one by one.

  Here, particularly in the present embodiment, in the sampling circuit 7, the image signal is distributed so as to be supplied to the adjacent data lines among the plurality of data lines 6a at different timings. That is, the data lines are distributed so that the image signals are not supplied to the adjacent data lines at the same timing. Specifically, sampling is performed by a logical sum signal output from different OR circuits 540 between one data line and another data line adjacent to the one data line.

  More specifically, in FIG. 5, first, the image signals VID2, VID4, and VID6 are the second data line from the left in FIG. 3 and the fourth data signal at the timing of the logical sum signal EN (2, 4, 6), respectively. This is supplied to the data line and the sixth data line.

  Subsequently, the image signals VID1, VID3, VID5, VID7, VID9, and VID11 are the first data line and the third from the left, respectively, at the timing of the logical sum signal EN (1, 3, 5, 7, 9, 11). , 5th data line, 7th data line, 9th data line and 11th data line.

  Subsequently, the image signals VID2, VID4, VID6, VID8, VID10, and VID12 are the 14th data line from the left and the 16th at the timing of the logical sum signal EN (8, 10, 12, 14, 16, 18), respectively. , 18th data line, 8th data line, 10th data line and 12th data line.

  Subsequently, the image signals VID1, VID3, VID5, VID7, VID9, and VID11 are the 13th data line and 15th from the left, respectively, at the timing of the logical sum signal EN (13, 15, 17, 19, 21, 23). , 17th data line, 19th data line, 21st data line and 23rd data line.

  Subsequently, the image signals VID2, VID4, VID6, VID8, VID10, and VID12 are the 26th data line and 28th from the left at the timing of the logical sum signal EN (20, 22, 24, 26, 28, 30), respectively. , 30th data line, 20th data line, 22nd data line and 24th data line.

  As described above, in this embodiment, the odd series image signals (that is, VID1, VID3, VID5, VID7, VID9, and VID11) and the even series image signals (that is, VID2, VID4, VID6, VID8, VID10, and VID12). ) Are sampled alternately. Therefore, image signals are supplied to the adjacent data lines at different timings.

  Here, let us consider a case where driving as shown in FIG. 6 is performed. In this case, the image signals VID1 to VID12 are sequentially supplied at the same timing. Therefore, image signals are supplied to the adjacent data lines at the same timing.

  In FIG. 7, in the drive as shown in FIG. 6, there is a risk that sequence unevenness along the sequence boundary may occur on the image display area 10a. This series unevenness causes a reduction in the quality of an image displayed in the electro-optical device.

  For example, when the image signal is sequentially supplied to each data line group including a plurality of data lines 6a, the series unevenness described above is performed after the writing to the block corresponding to one data line group is completed. This is because writing to a block corresponding to another data line group adjacent to the line group is started. That is, since the writing of the image signal is performed in units of blocks, display unevenness occurs at the locations located at the block boundaries.

  In addition, series unevenness may also occur due to push-down when the transistor 71 (see FIG. 3) is turned on and off.

  On the other hand, in the present embodiment, as described above, the image signals are not supplied to the adjacent data lines at the same timing. As a result, it is possible to extremely effectively reduce the influence of capacitive coupling of the image signal lines, variations in pushdown, and the like. Therefore, it is possible to prevent the occurrence of series unevenness as shown in FIG. 7 due to capacitive coupling or pushdown.

  As described above, according to the driving circuit and the driving method according to the present embodiment, it is possible to reduce sequence unevenness in phase expansion driving and display a high-quality image.

<Second Embodiment>
Next, a driving circuit and a driving method according to the second embodiment will be described with reference to FIGS. FIG. 8 is a block diagram illustrating a specific configuration of the electro-optical device according to the second embodiment, and FIG. 9 is a timing chart illustrating a driving method according to the second embodiment. The second embodiment differs from the first embodiment described above in part of the circuit configuration, and the other configurations are substantially the same. Therefore, in the second embodiment, portions different from the first embodiment will be described in detail, and descriptions of other overlapping portions will be omitted as appropriate.

  In FIG. 8, the drive circuit according to the second embodiment is configured such that the OR signal output from one OR circuit 540 is supplied to the plurality of transistors 71 in two jumps. That is, the connection configuration of the OR circuit 540 and the transistor 71 is different from that of the first embodiment described above.

  9, in the drive circuit according to the second embodiment, first, the image signal VID2 is supplied to the second data line from the left in FIG. 8 at the timing of the logical sum signal EN (2).

  Subsequently, the image signals VID3 and VID6 are supplied to the third data line and the sixth data line from the left, respectively, at the timing of the logical sum signal EN (3, 6).

  Subsequently, the image signals VID1, VID4, VID7, and VID10 are the first data line, the fourth data line, and the seventh data from the left, respectively, at the timing of the logical sum signal EN (1, 4, 7, 10). And the 10th data line.

  Subsequently, the image signals VID2, VID5, VID8, and VID11 are the 14th data line, the 5th data line, and the 8th data from the left respectively at the timing of the logical sum signal EN (5, 8, 11, 14). And the eleventh data line.

  Subsequently, the image signals VID3, VID6, VID9, and VID12 are the 15th data line, 18th data line, and 9th data from the left, respectively, at the timing of the logical sum signal EN (9, 12, 15, 18). And the 12th data line.

  Subsequently, the image signals VID1, VID4, VID7, and VID10 are the 13th data line, the 16th data line, and the 19th data from the left at the timing of the logical sum signal EN (13, 16, 19, 22), respectively. And the 22nd data line.

  Thus, in this embodiment, the image signals of each series are divided and supplied simultaneously to VID1, VID4, VID7, VID10, VID2, VID5, VID8, and VID11, and VID3, VID6, VID9, and VID12. . Therefore, image signals are supplied to the adjacent data lines at different timings.

  As a result, it is possible to extremely effectively reduce the influence of capacitive coupling of the image signal lines, variations in pushdown, and the like. Therefore, it is possible to prevent the occurrence of series unevenness as shown in FIG. 7 due to capacitive coupling or pushdown.

  As described above, according to the drive circuit and the drive method according to the second embodiment, it is possible to reduce the series unevenness in the phase expansion drive and display a high-quality image, as in the first embodiment. Become.

<Third Embodiment>
Next, a driving circuit and a driving method according to the third embodiment will be described with reference to FIG. FIG. 10 is a circuit diagram showing the configuration of the drive circuit according to the third embodiment. Note that the third embodiment differs from the first and second embodiments described above in the configuration of a part of the sampling circuit 7, and the other configurations are substantially the same. Therefore, in the third embodiment, portions different from those in the first and second embodiments will be described in detail, and description of other overlapping portions will be omitted as appropriate.

  10, in the drive circuit according to the third embodiment, the gate signal (that is, the logical sum signal supplied from the OR circuit 540) is supplied to the drain side of the transistor 71 in the sampling circuit 7 (see FIG. 3 or FIG. 8). The inverted signal is capacitively coupled. Specifically, an inverted signal is supplied from the inverted signal generation circuit 710 to the drain side of the transistor 71, whereby the capacitor 720 is formed.

  According to the above-described configuration in which the inverted signal is capacitively coupled, pushdown when the transistor 71 is turned on / off can be almost or completely eliminated. Therefore, it is possible to effectively reduce sequence unevenness due to pushdown.

  Similar effects can be expected by using a CMOS type circuit instead of capacitively coupling the inverted signal.

  As described above, according to the driving circuit and the driving method according to the third embodiment, not only the variation in pushdown is eliminated, but also the pushdown itself can be reduced, so that a higher quality image can be displayed. It becomes.

<Electronic equipment>
Next, the case where the liquid crystal device which is the above-described electro-optical device is applied to various electronic devices will be described. FIG. 11 is a plan view showing a configuration example of the projector. Hereinafter, a projector using the liquid crystal device as a light valve will be described.

  As shown in FIG. 11, a lamp unit 1102 including a white light source such as a halogen lamp is provided inside the projector 1100. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal device described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In the dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Therefore, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R and 1110B.

  Since light corresponding to the primary colors R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

  In addition to the electronic device described with reference to FIG. 11, a mobile personal computer, a mobile phone, an LCD TV, a viewfinder type, a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic device Examples include notebooks, calculators, word processors, workstations, videophones, POS terminals, and devices with touch panels. Needless to say, the present invention can be applied to these various electronic devices.

  In addition to the liquid crystal devices described in the above embodiments, the present invention includes a reflective liquid crystal device (LCOS), a plasma display (PDP), a field emission display (FED, SED), an organic EL display, and a digital micromirror device. (DMD), electrophoresis apparatus and the like are also applicable.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or concept of the invention that can be read from the claims and the entire specification. The driving method, the electro-optical device, and the electronic apparatus are also included in the technical scope of the present invention.

  6a ... data line, 7 ... sampling circuit, 9a ... pixel electrode, 10 ... TFT array substrate, 10a ... image display area, 11a ... scanning line, 20 ... counter substrate, 30 ... TFT, 50 ... liquid crystal layer, 70 ... storage capacitor , 71 ... transistor, 72 ... liquid crystal element, 100 ... electro-optical device, 101 ... data line driving circuit, 102 ... external circuit connection terminal, 104 ... scanning line driving circuit, 300 ... image signal line, 400 ... shift register, 510 ... Enable signal supply line, 520 ... AND circuit, 530 ... NRG supply line, 540 ... OR circuit, 600 ... pixel unit, 710 ... inverted signal generation circuit, 720 ... capacitance

Claims (7)

A drive circuit for driving an electro-optical device by outputting m-series serial-parallel converted image signals via m image signal lines to a plurality of data lines (where m is a natural number of 2 or more). Because
Image signal output means for outputting the m series of image signals to the m image signal lines;
Image signal allocating means for distributing and supplying the m series of image signals to the plurality of data lines for each data line group including m data lines;
The drive circuit according to claim 1, wherein the image signal distribution unit distributes the m-sequence image signals so as to be supplied to data lines adjacent to each other among the plurality of data lines.   The drive circuit according to claim 1, wherein timings at which the m-sequence image signals are supplied to the adjacent data lines are at least partially overlapped with each other. The image signal distribution means includes a transistor whose opening and closing is controlled by a gate signal,
The drive circuit according to claim 1, wherein an inverted signal obtained by inverting the gate signal is capacitively coupled to a drain side of the transistor.   The drive circuit according to claim 1, wherein the image signal distribution unit includes a complementary metal oxide semiconductor (CMOS) type circuit.   An electro-optical device comprising the drive circuit according to claim 1.   An electronic apparatus comprising the electro-optical device according to claim 5. Driving method for driving the electro-optical device by outputting image signals that are serial-parallel converted into m series via m image signal lines to a plurality of data lines (where m is a natural number of 2 or more) Because
An image signal output step of outputting the m-sequence image signal to the m image signal lines;
An image signal distribution step of distributing and supplying the m series of image signals to the plurality of data lines for each data line group including m data lines,
In the image signal allocating step, the m-sequence image signals are distributed so as to be supplied to adjacent data lines among the plurality of data lines at different timings.

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