JP2010239814A - Motor control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a motor control device wherein synchronous rectification can be effectively carried out even when a target duty ratio is high. <P>SOLUTION: The motor control device 1 includes a duty ratio comparison means 46 that determines whether a target duty ratio is equal to or higher than a predetermined duty ratio, a carrier frequency setting means 48 that, when the target duty ratio is equal to or higher than the predetermined duty ratio, increases or decreases the carrier frequency of a positive-phase PWM control signal according to the target duty ratio, an off time setting means 50 that, when the target duty ratio is equal to or higher than the predetermined duty ratio, fixes the off time of the positive-phase PWM control signal to a predetermined time, a negative-phase PWM signal generating means 52 that is turned on at the off time of the positive-phase PWM control signal, and a delaying means 62 that delays the positive-phase PWM control signal and the negative-phase PWM control signal. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a motor control device that performs pulse width modulation (hereinafter referred to as “PWM”) control.

  2. Description of the Related Art Conventionally, a motor control device that performs control of current supplied to a motor by PWM control is known (see, for example, Patent Document 1). The motor control device includes an inverter circuit that supplies current from a DC power source to an electric winding provided in the motor, and the inverter circuit is a half-bridge circuit including high-side and low-side switch elements connected in series. There are multiple. The high-side switch element of the half-bridge circuit is connected to a DC power supply, and the low-side switch element is connected to the ground. Then, by PWM control performed by the motor control device, either the high-side or low-side switch element provided in each half-bridge circuit is selectively turned on / off, and the motor from the power source is controlled by the on / off control of the switch element. The current value of the current supplied to the electrical winding is controlled.

  In the PWM control in this motor control device, the carrier cycle, which is the switching cycle for controlling the on / off of the switch element of the inverter circuit, remains unchanged and the ratio between the on time and the off time of the switch element. By changing the (duty ratio), the current value of the current supplied to the motor is controlled.

JP 2003-324928 A

  As described above, when one of the high-side switch element and the low-side switch element is selectively turned on / off by PWM control, an electric circuit in which current flows back when one switch element is in the off state Otherwise, due to the current supplied to the electrical winding when one of the switch elements is in the on state, the voltage between the terminals of the electrical winding becomes a high voltage and energy loss occurs in the electrical winding. For this reason, field effect transistors (hereinafter referred to as “FETs”) in which body diodes are parasitic are generally used as the high-side and low-side switch elements. When one switch element is turned off, the current supplied to the electric winding flows back in the electric circuit formed by the body diode parasitic on the other switch element.

  However, when a current flows back in the electric circuit formed by the body diode, a forward voltage is generated in the body diode, and a loss occurs in the switch element due to the forward voltage and the flowing current. The value of this loss is the product of the voltage value of the forward voltage and the current value of the circulating current. For example, if the voltage value of the forward voltage is 0.6 V, the current value of the circulating current is 2A. In this case, a loss of 1.2 W occurs.

  In order to reduce the loss generated in the body diode when the current is circulated, a control method may be used in which the other switch element is turned on and the current is circulated immediately after the one switch element is turned off. This control method is called synchronous rectification control. Here, in order to supply current from a DC power source, one switch element that is on / off controlled by PWM control is called positive phase PWM control, and the other switch element is used to recirculate the current supplied to the motor. What is turned on / off by PWM control is called reverse-phase PWM control.

  In the case of such synchronous rectification control, if the high-side switch element and the low-side switch element included in each half-bridge circuit are simultaneously turned on, a through current flows through the half-bridge circuit and the switch element is damaged. There is a fear. As a countermeasure, a dead time in which the switching elements on the high side and the low side are simultaneously turned off is provided. This dead time is set to an optimum value depending on the switch elements used, circuit constants such as voltage and current.

  However, when the dead time is provided, when the duty ratio is high, the off-time in the normal-phase PWM control signal is shortened, and the on-time in the reverse-phase PWM control signal can be provided only slightly. In some cases, the synchronous rectification control cannot be sufficiently performed. For example, if the PWM control carrier period is 50 μs and the dead time is 2 μs, there is a total dead time of 4 μs at the rise and fall. In this case, if the duty ratio is 90%, the off time is 5 μs (= 50 μs × (1−0.9)). Therefore, if the dead time of 4 μs is subtracted, the on time in the reverse phase PWM control signal is 1 μs. Since the effect of synchronous rectification appears only for 1 μs, there is a problem that the loss of the switch element due to the forward voltage generated in the body diode in the PWM control cannot be effectively reduced.

In the present invention, in order to solve such a problem and realize a reduction in loss due to PWM control in synchronous rectification control at a high duty ratio, in the motor control device for supplying current to the motor by PWM control, A plurality of half-bridge circuits comprising a high-side switch element connected to a DC power source and a low-side switch element connected to ground, and the current from the DC power source is turned on and off by the high-side or low-side switch element. A positive phase PWM control signal is supplied to one of the switching elements selected from the high-side or low-side switching elements provided in each half-bridge circuit. The high side or low side switch provided in the bridge circuit. Control signal generating means for supplying a reverse phase PWM control signal to the other switch element selected from the elements, the control signal generating means, if the target duty ratio signal is less than a predetermined duty ratio, A predetermined first count time is repeatedly measured, and when the target duty ratio signal is equal to or greater than the predetermined duty ratio, the target duty ratio signal is equal to or greater than the first count time. Carrier period setting means for repeatedly measuring a second count time that increases in response to an increase in the target duty ratio signal and decreases in response to a decrease in the target duty ratio signal, and wherein the target duty ratio signal is the predetermined duty ratio. If it is less than the second, the first duty ratio signal decreases in response to an increase in the target duty ratio signal, and increases in response to a decrease in the target duty ratio signal. Counting time is started substantially simultaneously with the start of the measurement of the carrier cycle setting means, and when the target duty ratio signal is equal to or greater than the predetermined duty ratio, is equal to or less than the third count time, And the measurement of the predetermined fourth count time is started substantially simultaneously with the start of the measurement of the first or second count time of the carrier cycle setting means, and the third or fourth count time is measured. The off-time setting means that outputs the first notification signal when the third or fourth count time is measured and the second notification signal after the measurement of the third or fourth count time is completed, and the off-time setting means A positive-phase PWM control signal that is turned off when the first notification signal is supplied and turned on when the second notification signal is supplied from the off-time setting means is generated. Based on the positive phase PWM control signal supplied from the positive phase PWM control signal generation means and the reverse phase PWM control signal that is an inverted signal with respect to the positive phase PWM control signal Phase PWM control signal generation means, and delay means for delaying either the rising signal or falling signal of the positive phase and negative phase PWM control signals.

  According to the present invention, when the target duty ratio signal is greater than or equal to a predetermined duty ratio, the PWM control carrier period is lengthened according to the target duty ratio and reversed with the off-time of the normal phase PWM control signal. The ON time of the phase PWM control signal is fixed to a predetermined time. Even when the target duty ratio increases, the on-time of the negative-phase PWM control signal is fixed at a predetermined time, so that synchronous rectification can be effectively performed even when the target duty ratio is high. The loss of the element can be reduced.

It is a block diagram of a motor device in an embodiment of the present invention. It is a figure which shows the relationship between a duty ratio and a carrier period in embodiment of this invention. 4 is a timing chart showing a positive phase PWM control signal formed by a control signal generation means in the embodiment of the present invention. It is a timing chart which shows the normal phase PWM control signal and negative phase PWM control signal which are formed in the control signal production | generation means in embodiment of this invention. 6 is a timing chart showing a normal phase PWM control signal and a negative phase PWM control signal that have been subjected to delay processing by the control signal generation means in the embodiment of the present invention. It is a flowchart which shows the process performed by the control signal production | generation means in embodiment of this invention. It is a timing chart which shows the normal phase PWM control signal and negative phase PWM control signal which are produced | generated by the control signal production | generation means in embodiment of this invention. It is a timing chart which shows the normal phase PWM control signal and negative phase PWM control signal which are produced | generated by the control signal production | generation means in embodiment of this invention.

  Next, an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of a motor device according to an embodiment of the present invention. The motor device 100 includes a three-phase brushless motor (motor) M having U-phase, V-phase, and W-phase electric windings used as a prime mover of an electric vehicle, and a motor that supplies current from the DC power supply BT to the motor M. And a control device 1.

  The motor control device 1 includes a rotation sensor 10 as a rotation angle measuring means for measuring a rotation angle of a rotor (not shown) provided in the motor M, and a connection line L connecting the motor control device 1 and the DC power source BT. Current sensor 20, inverter circuit 30 and control signal generation as current value measuring means for measuring the current values of the currents arranged and supplied to the U-phase, V-phase and W-phase electrical windings (U, V, W) Means 40 are provided.

  The inverter circuit 30 includes three half-bridge circuits (31, 32, 33) connected in parallel to the DC power supply BT. The half-bridge circuit 31 includes a high-side switch element 31a connected to the DC power supply BT and a low-side switch element 31b connected to the ground GND, and the half-bridge circuit 32 includes a high-side switch element 31b connected to the DC power supply BT. Switch element 32a and a low-side switch element 32b connected to the ground GND. The half-bridge circuit 33 includes a high-side switch element 33a connected to the DC power supply BT and a low-side switch element connected to the ground GND. 33b. Further, the switch elements (31a, 31b, 32a, 32b, 33a, 33b) of the present embodiment are FETs in which the body diode D is parasitic.

  Then, by turning on or off the high-side or low-side switch elements (31a, 31b, 32a, 32b, 33a, 33b), the inverter circuit 30 causes the current from the DC power supply BT to be supplied to the motor M in the U phase and V phase. And supply to W-phase electrical windings (U, V, W). In addition, a capacitor C is connected to the inverter circuit 30 in parallel, and the current supplied to the U-phase, V-phase, and W-phase electrical windings (U, V, W) is smoothed by the capacitor C. Done.

  Next, the control signal generation means 40 will be described with reference to FIG. The control signal generation means 40 includes a current value command means 41, a current value detection means 42, a current value comparison means 43, a target duty ratio determination means 44, a duty ratio memory 45, a duty ratio comparison means 46, a division value calculation means 47, a carrier First timer 48 as period setting means, initial value setting means 49, second timer 50 as off time setting means, PWM signal generation means 500, rotation angle detection means 60, energization signal generation means 61 and delay means 62 It has. The control signal generation means 40 is connected to the inverter circuit 30 and supplies a PWM control signal to the inverter circuit 30.

  The current value command means 41 reads the accelerator signal supplied from the accelerator operation means A attached to the vehicle, and outputs a current value command signal based on the read accelerator signal. The current value detection means 42 reads the current value signal supplied from the current sensor 20 and outputs the read current value signal. The current value comparison unit 43 calculates a difference between the current value command signal supplied from the current value command unit 41 and the current value signal supplied from the current value detection unit 42, and a difference signal corresponding to the calculated difference. Is output.

  The target duty ratio determining means 44 determines the target duty ratio D1 based on the difference signal supplied from the current value comparing means 43, and outputs a target duty ratio signal corresponding to the target duty ratio D1. The duty ratio memory 45 stores a predetermined duty ratio D0. In the present embodiment, the duty ratio “60%” (D0 = 60) is stored as the predetermined duty ratio D0.

  The duty ratio comparison means 46 compares the target duty ratio signal supplied from the target duty ratio determination means 44 with a predetermined duty ratio D0 stored in the duty ratio memory, and compares the target duty ratio signal with the target duty ratio signal. When the duty ratio DUTY is less than the predetermined duty ratio D0, this is output as a first signal, and the target duty ratio D1 corresponding to the target duty ratio signal is equal to or greater than the predetermined duty ratio D0. If so, the fact is output as the second signal.

  The division value calculation means 47 sets and sets the division value d based on the target duty ratio signal supplied from the target duty ratio determination means 46 and the first or second signal supplied from the duty ratio comparison means 46. A division value signal corresponding to the division value d is output. The division value d is used as a reference value for setting the carrier period of the positive phase PWM control signal in the control signal generation means 40 of the present embodiment.

When the target duty ratio D1 is less than a predetermined duty ratio D0 and the first signal is supplied from the duty ratio comparison means 43, the division value d in the division value calculation means 47 is expressed by the following equation (1). Set to a value.
d = (100−D0) × 2 (1)
Since the duty ratio D0 is a constant value, when the target duty ratio D1 is less than a predetermined duty ratio D0, the division value d is set to a constant value. In this embodiment, since the duty ratio D0 is set to “60”, the division value d is set to “80”.

When the target duty ratio D1 is equal to or greater than a predetermined duty ratio D0 and the second signal is supplied from the duty ratio comparison means 46, the division value d in the division value calculation means 47 is expressed by the following equation (2). Set to a value.
d = (100−D1) × 2 (2)
The target duty ratio D1 is a value that is changed by the target duty ratio determination means 41, and the division value d is a value that decreases as the target duty ratio D1 increases and increases as the target duty ratio D1 decreases.

  The first timer 48 as the carrier cycle setting means is a down counter in which an initial count value T1max is set in advance. The division value signal is supplied from the division value calculation means 44 to the first timer 48, and the first timer 48 decrements the division value d corresponding to the division value signal from the initial count value T1max every clock cycle Tcl. An operation is performed, and when the count value T1 becomes zero, a count-up signal is output. Then, without delay after the count value T1 becomes zero, the first timer 48 again starts the operation of decrementing the count value T1 from the initial count value T1max, and repeatedly outputs the first count-up signal.

When the target duty ratio D1 is less than the predetermined duty ratio D0, the first timer 48 decrements the count value T1 from the initial count value T1max by the division value d in each clock cycle Tcl according to the equation (1). The first count time ΔT1 from when the operation starts until the count value T1 becomes zero and the count-up signal is output is the time indicated by the following expression (3) according to the expression (1).
ΔT1 = (T1max / d) × Tcl
= (T1max / ((100−D0) × 2)) × Tcl (3)

  Since the duty ratio D0 is a predetermined constant value, the first count time ΔT1 is a constant value. In this embodiment, the division value d is set to “80”, the initial count value T1max is set to “16000”, and the clock cycle Tcl that performs the operation of decrementing the division value d from the initial count value T1max is performed. Is “250 ns”. Accordingly, the first count time ΔT1 when the target duty ratio D1 is less than the duty ratio D0 is a constant value “50 μs”.

On the other hand, when the target duty ratio D1 is greater than or equal to the predetermined duty ratio D0, the division value d whose value calculated by the equation (2) varies is supplied from the division value calculation means 47 to the first timer 48. The Therefore, when the target duty ratio D1 is equal to or greater than the predetermined duty ratio D0, the operation of starting to decrement the count value T1 from the initial count value T1max by the division value d is started, and then the count value T1 becomes zero, and the count up The second count time ΔT2 until the signal is output is a time represented by the following equation (4).
ΔT2 = (T1max / d) × Tcl
= (T1max / ((100−D1) × 2)) × Tcl (4)

  In the present embodiment, when the target duty ratio D1 is equal to or greater than a predetermined duty ratio D0, the value of the division value d varies and the division value d is less than the predetermined duty ratio D0. Smaller than Therefore, the second count time ΔT2 is equal to or longer than the first count time ΔT1 (ΔT2 ≧ ΔT1), the target duty ratio D1 increases, and the second count time ΔT2 increases as the division value d decreases. To do. On the other hand, the second count time ΔT2 decreases as the target duty ratio D1 decreases and the division value d increases.

  The initial value setting means 49 sets and sets the initial value T2max based on the target duty ratio signal supplied from the target duty ratio determination means 44 and the first or second signal supplied from the duty ratio comparison means 46. An initial value signal corresponding to the initial value T2max is output. The initial value T2max is used as a reference value for setting the off time of the positive phase PWM control in the control signal generation means 40 of the present embodiment.

When the target duty ratio D1 is less than a predetermined duty ratio D0 and the first signal is supplied from the duty ratio comparison unit 46, the initial value T2max in the initial value setting unit 49 is expressed by the following equation (5). Set to a value.
T2max = (100−D1) × 2 (5)
The target duty ratio D1 is a value that is changed by the target duty ratio determination means 44. When the target duty ratio D1 is less than a predetermined duty ratio D0, the initial value T2max increases with an increase in the target duty ratio D1. The value decreases and increases as the target duty ratio D1 decreases.

On the other hand, when the target duty ratio D1 is greater than or equal to the predetermined duty ratio D0 and the second signal is supplied from the duty ratio comparison means 43, the initial value setting means 49 sets the initial value T2max to the following formula (6 ).
T2max = (100−D0) × 2 (6)

  Since the duty ratio D0 is a constant value, the initial value T2m is set to a constant value when the target duty ratio D1 is greater than or equal to a predetermined duty ratio D0. In the present embodiment, since the duty ratio D0 is set to “60”, the initial value T2m is set to “80”.

  The second timer 50 as the off time setting means is a down counter that performs an operation of decrementing the count value T2. The initial value signal supplied from the initial value setting means 49 is supplied to the second timer 50, the initial value T2max corresponding to the initial value signal is set, and the count value T2 is decremented from the initial value T2max. .

  The second timer 50 starts to decrement when the count-up signal is supplied from the first timer 48, and decrements the count value T2 by one from the initial count value T2max every clock cycle Tcl. I do. That is, the second timer 50 starts counting the first or second count time (ΔT1, ΔT2) almost simultaneously with the first timer 48 starting to decrement, in other words, the first timer 48 starts counting. It is set to start an operation of decrementing substantially at the same time.

  When the second timer 50 is counting, the first notification signal is output from the second timer 50, the count value T2 of the second timer 50 becomes zero, and then the first timer Until the count up signal is supplied from 48, the second notification signal is output from the second timer 50.

When the target duty ratio D1 is less than the predetermined duty ratio D0, the second timer 50 starts an operation of decrementing the count value T2 by 1 from the initial count value T2max every clock cycle Tcl. That is, the third count time ΔT3 from when the output of the first notification signal is started until the count value T2 becomes zero and the second notification signal is output is expressed by the following equation (7) according to equation (5): ).
ΔT3 = T2max × Tcl
= (100−D1) × 2 × Tcl (7)

  As described above, when the target duty ratio D1 is less than the predetermined duty ratio D0, the initial value T2max is a value that decreases as the target duty ratio D1 increases and increases as the target duty ratio D1 decreases. is there. Therefore, the third count time ΔT3 also decreases as the target duty ratio D1 increases, and increases as the target duty ratio D1 decreases.

On the other hand, when the target duty ratio D1 is equal to or greater than the predetermined duty ratio D0, the second timer 50 starts an operation of decrementing the count value T2 by 1 from the initial count value T2max every clock cycle Tcl. That is, the fourth count time ΔT4 from when the output of the first notification signal is started until the count value T2 becomes zero and the second notification signal is output is expressed by the following equation (6). This is the time shown in equation (8).
ΔT4 = T2max × Tcl
= (100−D0) × 2 × Tcl (8)

  As described above, when the target duty ratio D1 is greater than or equal to the predetermined duty ratio D0, the initial value T2max is a constant value. Accordingly, the fourth count time ΔT4 is equal to or shorter than the third count time ΔT3 (ΔT4 ≦ ΔT3), and is a constant value regardless of the change in the target duty ratio D1.

  Next, the PWM control signal generation means 500 will be described with reference to FIG. The PWM control signal generation unit 500 includes a normal phase PWM control signal generation unit 51 and a reverse phase PWM control signal generation unit 52.

  The positive phase PWM control signal generating means 51 forms and outputs a positive phase PWM control signal PP0 based on the first and second notification signals supplied from the second timer 50. As described above, the first notification signal is output from the second timer 50 when the second timer 50 is counting, and the second notification signal has a count value T2 of the second timer 50 of zero. After that, the second timer 50 outputs the signal until the count-up signal is supplied from the first timer 48.

  The positive phase PWM control signal generation means 51 is in an OFF state during the time when the first notification signal is supplied from the second timer 50, that is, during the third or fourth count time, and the second timer 50 After the measurement of the third or fourth count time is completed, a positive-phase PWM control signal that is turned on is formed during the time when the second notification signal is supplied.

  The time from when the supply of the first notification signal is started until the positive phase PWM control signal is sequentially turned off is called a carrier cycle Tca, and the first or second count time (ΔT1, ΔT2) is The carrier period is Tca. Also, the time from when the supply of the second notification signal is started until the positive phase PWM control signal is turned from the off state to the on state is called an off time Toff, and the third or fourth count time (ΔT3 , ΔT4) is the off time Toff.

  The relationship between the carrier cycle Tca of the positive phase PWM signal and the target duty ratio D1 will be described with reference to FIGS. As described above, the first or second count time (ΔT1, ΔT2) is the carrier cycle Tca, and the carrier cycle Tca is a constant value when the target duty ratio D1 is less than the predetermined duty ratio D0. Since it is the first count time, the carrier period Tca is also a constant value. In the present embodiment, since the duty ratio D0 is set to “60%”, when the target duty ratio D1 is less than “60%”, the carrier cycle Tca is “50 μs” and has a constant value.

  When the target duty ratio D1 is greater than or equal to the predetermined duty ratio D0, the second count time ΔT2 increases as the target duty ratio D1 increases, as shown in the equation (4). Tca also increases as the target duty ratio D1 increases. In the present embodiment, the duty ratio D0 is set to “60%”. Therefore, when the target duty ratio D1 is “60%” or more, the carrier period Tca increases as the target duty ratio D1 increases. When the target duty ratio D1 is “80%”, the carrier period Tca is “100 μs”. Thus, when the target duty ratio D1 is “90%”, the carrier cycle Tca is “200 μs”.

  Next, the relationship between the off time Toff of the positive phase PWM signal and the target duty ratio D1 will be described with reference to FIG. As described above, the third or fourth count time (ΔT3, ΔT4) becomes the off time Toff, and as shown in the equation (5), the target duty ratio D1 is a predetermined duty ratio. When it is less than D0, it decreases as the target duty ratio D1 increases, so the off time Toff also decreases as the target duty ratio D1 increases. In the present embodiment, when the target duty ratio D1 is “20%”, the off time Toff is “40 μs”, and when the target duty ratio D1 is “40%”, the off time T0ff is “30 μs”.

  When the target duty ratio D1 is equal to or greater than a predetermined duty ratio D0, the fourth count time ΔT4 is a constant value, so the off time Toff is also a constant value. In the present embodiment, since the duty ratio D0 is set to “60%”, when the target duty ratio D1 is “60%” or more, the off time Toff is “20 μs” and becomes a constant value.

  The negative phase PWM signal generation unit 52 forms and outputs a negative phase PWM control signal NP0 based on the positive phase PWM control signal PP0 supplied from the first positive phase PWM signal generation unit 51. As shown in FIG. 4, the negative phase PWM control signal NP0 is formed as an inverted signal of the positive phase PWM control signal PP0. That is, when the normal phase PWM control signal PP0 is in the on state, the reverse phase PWM control signal NP0 is in the off state, and when the normal phase PWM control signal PP0 is in the off state, the reverse phase PWM control signal NP0 is in the on state.

  Next, the rotation angle detection means 60, energization signal generation means 61, and delay means 62 will be described with reference to FIG.

  The rotation angle detection means 60 outputs a rotation angle signal based on the measurement signal supplied from the rotation sensor 10. The energization signal generation unit 61 forms an energization pattern signal based on the rotation angle signal supplied from the rotation angle detection unit 60. Then, the energization signal generation unit 61 performs a process of multiplying the energization pattern signal by the normal phase PWM control signal PP0 and the negative phase PWM control signal NP0 supplied from the PWM signal generation unit 500, and outputs the processed signal.

  The delay means 62 performs a process of providing a predetermined dead time dT for the normal phase PWM control signal PP0 and the negative phase PWM control signal NP0 supplied from the energization signal generating means. By the process of providing the dead time dT, the dead time dT is set to the rising signal that switches from the off state to the on state in the normal phase and reverse phase PWM control signals (PP0, NP0). Even if the dead time dT is set by providing means for advancing the falling signal that switches from the on state to the off state in the normal phase and reverse phase PWM control signals (PP0, NP0) instead of the delay means 62. good.

  A switch in which the inverter circuit 30 is provided with a normal phase PWM control signal PP1 and a negative phase PWM control signal NP1 provided with a dead time dT as a rising signal that is switched from an off state to an on state by the delay means 62. It is supplied to the elements (31a, 31b, 32a, 32b, 33a, 33b).

  Next, the normal phase PWM control signal PP0 and the reverse phase PWM control signal NP0 output from the PWM signal generation unit 500, and the normal phase PWM control signal PP1 and the negative phase PWM control signal NP1 output from the delay unit 62 are shown in FIG. Based on As shown in the figure, the normal phase PWM control signal PP0 and the reverse phase PWM control signal NP0 output from the PWM signal generation unit 500 are switched from the off state (off) to the on state (on) by the delay unit 62. The dead time dT is set as the rising signal to be changed. In the present embodiment, the dead time dT is set to “2 μs”.

  Next, an example of processing for generating the positive phase PWM signal PP0 by the control signal generation means 40 will be described with reference to FIG. When the process is started ("start"), first, the accelerator signal is read by the current command means 41, and the current value signal is read by the current value detection means 42 (process ST1).

  The target duty ratio determining means 44 determines the target duty ratio D1 from the accelerator signal and current value signal read in the process ST1 (process ST2), and the duty ratio comparing means 46 determines the target duty ratio D1 in advance. It is determined whether or not the duty ratio is equal to or greater than D0 (process ST3). When the target duty ratio D1 is equal to or greater than the duty ratio D0, the division value calculation means 47 sets “(100−D1) × 2” as the division value d (processing ST4). On the other hand, when the target duty ratio D1 is less than the duty ratio D0, the division value calculation means 47 sets “(100−D0) × 2” as the division value d (process ST5).

  Next, in order to determine whether or not the first timer 48 is counting up, it is determined whether or not the count value T1 of the first timer 48 is smaller than the division value d (process ST6). Hereinafter, a case where it is determined that the count value T1 of the first timer 48 is smaller than the division value d will be described.

  If the count value T1 is smaller than the division value d, it is determined that the first timer 48 is counting up, and the first timer 48 resets the initial count value T1max as the count value T1 (process ST7). ), An operation of decrementing the count value T1 from the initial count value T1max is started. Then, again, the duty ratio comparison means 46 determines whether or not the target duty ratio D1 is equal to or higher than the duty ratio D0 (process ST8).

  If the target duty ratio D1 is greater than or equal to the duty ratio D0 as a result of the determination in step ST8, “(100−D0) × 2” is the initial count value T2max as the count value T2 of the second timer 50. The second timer 50 starts an operation of decrementing the count value T2 from the set initial count value T2max (ST9), and a series of processing ends (“END”).

  On the other hand, when the target duty ratio D1 is less than the duty ratio D0 as a result of the determination in process ST8, “(100−D1) × 2” is initially set as the count value T2 of the second timer 50. The count value T2max is set, and the second timer 50 starts an operation of decrementing the count value T2 from the set initial count value T2max (ST10), and a series of processing ends (“end”).

  Next, a case will be described in which it is determined in process ST6 that the count value T1 of the first timer 48 is equal to or greater than the division value d. When it is determined that the count value T1 is greater than or equal to the division value d, the first timer 48 performs a process of subtracting the division value d from the count value T1 in one decrement operation (process ST11). Then, whether the count value T2 of the second timer 50 is “zero”, that is, whether the second timer 50 has been counted up, or the second timer 50 performs a decrement operation. It is determined whether it is in a state (ST12).

  In the process ST12, when the second timer 50 has not counted up, the first notification signal is supplied from the second timer 50 to the positive phase PWM control signal generating means 51, and the positive phase PWM control signal generation is performed. The means 51 outputs an “off signal (= 0)” as the normal phase PWM control signal PP0, and the count value T2 of the second timer 50 is decremented by 1 (ST13), and the series of processing ends. ("End").

  On the other hand, in the process ST12, when the second timer 50 has been counted up, the second timer 50 outputs a second notification signal, and the positive phase PWM control signal generating means 51 outputs The “ON signal (= 1)” is output as the normal phase PWM control signal PP0, and the series of processing ends (“END”). The series of processing from “start” to “end” is repeated every clock cycle Tcl. In the present embodiment, the clock cycle Tcl is set to 250 ns.

  Next, the effect which the motor control apparatus 1 of this Embodiment has is demonstrated based on FIG. 7 and FIG. FIG. 7 shows the normal phase and reverse phase PWM control signals (PP1, NP1) when the target duty ratio D1 coincides with the predetermined duty ratio D0, and FIG. 8 shows the target duty ratio D1 determined in advance. The positive phase and negative phase PWM control signals (PP1, NP1) when the duty ratio exceeds D0 are shown.

  As shown in FIG. 7, in the motor control device 1 of the present embodiment, the carrier cycle Tca is fixed at a constant value until the target duty ratio D1 matches the predetermined duty ratio D0, and the positive phase PWM The off time Toff of the control signal PP1 and the on time Ton of the reverse phase PWM control signal NP1 decrease as the target duty ratio D1 increases. The on-time Ton of the reverse phase PWM control signal NP1 is a time obtained by subtracting the dead time dT twice from the off time Toff of the normal phase PWM control signal PP1.

  In a state where the carrier cycle Tca is fixed to a constant value, when the target duty ratio D1 coincides with a predetermined duty ratio D0, the OFF time Toff of the normal phase PWM control signal PP1 and the ON phase of the negative phase PWM control signal NP1 Each time Ton is a minimum value. In the present embodiment, the on-time Ton of the negative phase PWM control signal NP1 when the value becomes the minimum value is set to “18 μs”, and the synchronous rectification is effectively performed.

  As shown in FIG. 8, when the target duty ratio D1 is equal to or greater than a predetermined duty ratio D0, the carrier cycle Tca of the PWM control is increased or decreased according to the target duty ratio D1, and the positive phase PWM control is performed. The off time Toff of the signal PP1 is fixed to a certain time. Therefore, the PWM control according to the target duty ratio D1 can be performed by fixing the off time Toff of the positive phase PWM control signal PP1 to a constant time and increasing / decreasing the carrier cycle Tca.

  Further, when the standard duty ratio D1 is equal to or greater than a predetermined duty ratio D0, the on-time Ton of the negative-phase PWM control signal NP1 together with the off-time Toff of the normal-phase PWM control signal PP1 effectively performs synchronous rectification. Is set to a certain time possible. Therefore, the motor control device 1 according to the present embodiment can effectively perform synchronous rectification even when the target duty ratio D1 increases. As a result, even when the target duty ratio D1 is high, the loss of the switch element due to the PWM control can be reduced.

DESCRIPTION OF SYMBOLS 1 Motor control apparatus 10 Rotation sensor 20 Current sensor 30 Inverter circuit 31 Half bridge circuit 32 Half bridge circuit 33 Half bridge circuit 31a Switch element 31b Switch element 32a Switch element 32b Switch element 33a Switch element 33b Switch element 40 Control signal generation means 41 Current Value command means 42 Current value detection means 43 Current value comparison means 44 Target duty ratio determination means 45 Duty ratio memory 46 Duty ratio comparison means 47 Divisor value calculation means 48 First timer (carrier cycle setting means)
49 Initial value setting means 50 Second timer (off time setting means)
51 Normal-phase PWM signal generation means 52 Reverse-phase PWM signal generation means 60 Rotation angle detection means 61 Energization signal generation means 62 Delay means 100 Motor device 500 PWM signal generation means M Brushless motor U U-phase electric winding V V-phase electricity Winding W W-phase electric winding C Capacitor B Battery A Accelerator operating means D Body diode

Claims (2)

In the motor control device that supplies current to the motor by PWM control,
A plurality of half-bridge circuits comprising a high-side switch element connected to a DC power source and a low-side switch element connected to ground, and the current from the DC power source is turned on and off by the high-side or low-side switch element. An inverter circuit for supplying to the motor;
A positive-phase PWM control signal is supplied to one of the high-side or low-side switch elements provided in each half-bridge circuit, and the high-side provided in each half-bridge circuit. Or a control signal generating means for supplying a reverse-phase PWM control signal to the other switch element selected from the low-side switch elements,
The control signal generating means
When the target duty ratio signal is less than the predetermined duty ratio, the first count time set in advance is repeatedly measured, and when the target duty ratio signal is greater than or equal to the predetermined duty ratio, Carrier cycle setting for repeatedly measuring a second count time that is equal to or longer than the first count time, increases in response to an increase in the target duty ratio signal, and decreases in response to a decrease in the target duty ratio signal Means,
When the target duty ratio signal is less than the predetermined duty ratio, a third count that decreases in response to an increase in the target duty ratio signal and increases in response to a decrease in the target duty ratio signal The measurement of time is started substantially simultaneously with the start of measurement of the carrier cycle setting means, and when the target duty ratio signal is equal to or greater than the predetermined duty ratio, it is equal to or less than the third count time, and The measurement of the predetermined fourth count time is started substantially simultaneously with the start of the measurement of the first or second count time of the carrier cycle setting means, and the third or fourth count time is measured. An off-time setting means for outputting a first notification signal when output, and outputting a second notification signal after finishing the measurement of the third or fourth count time;
A positive phase PWM control signal that is turned off when the first notification signal is supplied from the off time setting means and is turned on when the second notification signal is supplied from the off time setting means. Positive phase PWM control signal generating means for generating;
Based on the positive phase PWM control signal supplied from the positive phase PWM control signal generating means, a negative phase PWM control signal generating means for generating a negative phase PWM control signal that is an inverted signal with respect to the positive phase PWM control signal;
A motor control device comprising delay means for delaying a rising signal of the normal phase and reverse phase PWM control signals. In the motor control device that supplies current to the motor by PWM control,
A plurality of half-bridge circuits comprising a high-side switch element connected to a DC power source and a low-side switch element connected to ground, and the current from the DC power source is turned on and off by the high-side or low-side switch element. An inverter circuit for supplying to the motor;
A positive-phase PWM control signal is supplied to one of the high-side or low-side switch elements provided in each half-bridge circuit, and the high-side provided in each half-bridge circuit. Or a control signal generating means for supplying a reverse-phase PWM control signal to the other switch element selected from the low-side switch elements,
The control signal generating means
When the target duty ratio signal is less than a predetermined duty ratio, the target duty ratio signal is turned on / off at a predetermined first count time, and decreases in response to an increase in the target duty ratio signal, and the target duty ratio signal decreases. In an off state during a third count time that increases in response to, and when the target duty ratio signal is greater than or equal to a predetermined duty ratio, it is greater than or equal to the first count time and the target duty ratio It increases in response to an increase in the signal, turns on / off at a second count time that decreases in response to a decrease in the target duty ratio signal, is equal to or less than the third count time, and is a predetermined fourth time. A positive phase PWM control signal generating means for generating a positive phase PWM control signal that is in an OFF state during the count time of
Based on the positive phase PWM control signal supplied from the positive phase PWM control signal generating means, a negative phase PWM control signal generating means for generating a negative phase PWM control signal that is an inverted signal with respect to the positive phase PWM control signal;
A motor control device comprising delay means for delaying a rising signal of the normal phase and reverse phase PWM control signals.

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