JP2010238917A - Photosensitive resist protecting tape, method of manufacturing semiconductor package substrate, and semiconductor package substrate - Google Patents

Photosensitive resist protecting tape, method of manufacturing semiconductor package substrate, and semiconductor package substrate Download PDF

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JP2010238917A
JP2010238917A JP2009085364A JP2009085364A JP2010238917A JP 2010238917 A JP2010238917 A JP 2010238917A JP 2009085364 A JP2009085364 A JP 2009085364A JP 2009085364 A JP2009085364 A JP 2009085364A JP 2010238917 A JP2010238917 A JP 2010238917A
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layer
semiconductor package
base film
photosensitive resist
package substrate
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JP5104799B2 (en
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Jin Sato
尽 佐藤
Masaaki Chino
正晃 地野
Akihiko Furuya
明彦 古屋
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Toppan Inc
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Toppan Printing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a photosensitive resist protecting tape that is effective for the supply of a semiconductor package substrate not deteriorating a loading yield and connecting reliability, and high in electric reliability even if an aperture diameter of a solder resist is further reduced, and also to provide a method of manufacturing the semiconductor package substrate, and the semiconductor package substrate. <P>SOLUTION: The photosensitive resist protecting tape is formed of a base material film 2a, an adhesive layer 2c, and a supporting film 2b. The protecting tape is characterized in that the base material film 2a, the adhesive layer 2c, and a light-hardening resin of the solder resist are laminated in this order, and the base material film or the adhesive layer is imparted with optical characteristics that: (1) the transmittance of the base material film and the adhesive layer for the exposure light of the solder resist is enough to permit the light of 350 to 450 nm of the exposure light to reach SR; and (2) a ratio of the main peak intensity of the light in a 350 to 380 nm region and the main peak intensity of light in a 400 to 420 nm region is in a range of 1:1 to 1:5. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、電子機器、電気機器、コンピューター、通信機器等に用いられる半導体パッケージ基板、特に、ＦＣ−ＢＧＡ基板（FC-BGA： Flip Chip-Ball Grid Array）、ＣＳＰ基板（CSP： Chip Size Package）に用いるソルダーレジスト層を形成する際に用いる感光性レジスト保護用テープの構造と製造方法に関する。   The present invention relates to semiconductor package substrates used in electronic devices, electrical devices, computers, communication devices, etc., in particular, FC-BGA substrates (FC-BGA: Flip Chip-Ball Grid Array), CSP substrates (CSP: Chip Size Package). The present invention relates to a structure and a manufacturing method of a photosensitive resist protective tape used for forming a solder resist layer used in the manufacturing method.

従来、半導体パッケージ基板は絶縁樹脂の積層による絶縁層形成、レーザー等によるビアの形成、パターンメッキによる配線形成を繰り返すことにより、３次元的に配線パターンを形成する基板である。近年、高性能化、軽薄短小化の要求が進み、配線パターンの細線化、接続端子（ランド、パッド等）の微細化、層間を電気的に接続するビアの小径化が進み、それらが多数存在する複雑な基板が形成されている。更に、ワイヤボンディング用パッドのないＦＣ−ＢＧＡやＣＳＰが開発され、高密度化に対応する為、急速に細線化、微細化が進んできている。   2. Description of the Related Art Conventionally, a semiconductor package substrate is a substrate on which a wiring pattern is formed three-dimensionally by repeating formation of an insulating layer by laminating insulating resins, formation of vias by a laser or the like, and wiring formation by pattern plating. In recent years, there has been a demand for higher performance, lighter, thinner, smaller wiring patterns, finer connection terminals (lands, pads, etc.), and smaller diameters for vias that electrically connect layers, and there are many of these. A complicated substrate is formed. Furthermore, FC-BGA and CSP having no wire bonding pads have been developed, and in order to cope with the higher density, the thinning and miniaturization are rapidly progressing.

半導体パッケージ基板における、実装工程は、半導体パッケージ基板側のソルダーレジスト層の開口部と半導体チップ側の電極パッドをはんだにより接続し、半導体パッケージ基板と半導体チップの間隙をアンダーフィルにより充填する。はんだ接続はそれに接するソルダーレジストの開口形状が適切でない場合、半導体パッケージ基板と半導体チップとを接続するはんだが接続不良を起こす問題があり、微細化に伴う実装時の歩留まりや実装後の接続信頼を維持もしくは向上させるため、ソルダーレジストの開口部を制御しなくてはならない。
半導体パッケージ基板で使用されるソルダーレジストは塗工、乾燥後の未露光状態でタックが発生しており、取り扱い、及び露光時の光硬化反応の関係上、粘着フィルムをソルダーレジスト上に貼付し、ソルダーレジスト表面の保護の役目として使われている。 In the mounting process in the semiconductor package substrate, the opening of the solder resist layer on the semiconductor package substrate side and the electrode pad on the semiconductor chip side are connected by solder, and the gap between the semiconductor package substrate and the semiconductor chip is filled with underfill. When the solder resist opening shape that contacts the solder connection is not appropriate, there is a problem that the solder connecting the semiconductor package substrate and the semiconductor chip may cause a connection failure, and the yield at the time of mounting due to miniaturization and the connection reliability after mounting are reduced. In order to maintain or improve, the opening of the solder resist must be controlled.
The solder resist used in the semiconductor package substrate is tacked in the unexposed state after coating and drying, and the adhesive film is stuck on the solder resist for handling and the photocuring reaction during exposure. It is used to protect the solder resist surface.

例えば、特許文献１では、半導体チップ実装時後の接続信頼性を確保する為に、粘着フィルムの粘着層の表面状態をソルダーレジストに転写し、ソルダーレジストの表面粗さを制御し、実装後の接続信頼性を確保する対策が提案されている。   For example, in Patent Document 1, in order to ensure connection reliability after mounting a semiconductor chip, the surface state of the adhesive layer of the adhesive film is transferred to a solder resist, the surface roughness of the solder resist is controlled, Measures for ensuring connection reliability have been proposed.

また、特許文献２では、高密度化、細線化に対応すべく、ソルダーレジスト層に炭酸ガスレーザー等を用いて、微細な開口を形成する対策が提案されている。   Patent Document 2 proposes a measure for forming a fine opening by using a carbon dioxide laser or the like in the solder resist layer in order to cope with higher density and thinner lines.

そして、特許文献３では、耐衝撃性に優れた半導体パッケージ基板に対応すべく、半導体パッケージ基板で、ソルダーレジスト層の開口径が表層側（上部）より接続端子側（下部）の方が大きな構造にする対策が提案されている。   And in patent document 3, in order to respond | correspond to the semiconductor package board | substrate excellent in impact resistance, the opening diameter of a soldering resist layer is larger on the connection terminal side (lower part) than on the surface layer side (upper part) Measures to make are proposed.

特開２００８−１１７９２９号公報JP 2008-117929 A 特開２００１−２３７３３８号公報JP 2001-237338 A 特開２００７−１７３７３７号公報JP 2007-173737 A

しかし、特許文献１に記載の発明によると、この粘着フィルムでは、ソルダーレジスト層の露光後に、ソルダーレジスト層の表層側（上部）と接続端子側（下部）で光重合の速度差が生じ、ソルダーレジスト層の開口表層部が閉塞する。それにより、開口径が小さく、開口径にバラツキが発生するため、半導体パッケージ基板に半導体チップを実装する際に、はんだの接続不良が発生する。また特許文献１の発明によると、ソルダーレジスト層の表層側（上部）の開口が小さく、接続端子側（下部）が大きくなるため、実装後のはんだがソルダーレジスト層の表層部で凹んだ形状となり、実装後の接続信頼性が著しく低下する。   However, according to the invention described in Patent Document 1, in this adhesive film, after the exposure of the solder resist layer, a difference in the rate of photopolymerization occurs between the surface layer side (upper part) and the connection terminal side (lower part) of the solder resist layer. The opening surface layer portion of the resist layer is blocked. As a result, the opening diameter is small and the opening diameter varies, so that a solder connection failure occurs when the semiconductor chip is mounted on the semiconductor package substrate. Further, according to the invention of Patent Document 1, since the opening on the surface layer side (upper part) of the solder resist layer is small and the connection terminal side (lower part) is large, the solder after mounting becomes a shape recessed at the surface layer part of the solder resist layer. The connection reliability after mounting is significantly reduced.

そして、特許文献２に記載の発明によると、微細化の実現や開口の形状が一定となるが、半導体パッケージ基板と半導体チップの接続端子の数は数百〜千数百にまで及ぶため、接続端子を形成する開口の加工にレーザーを用いるとコスト高となる上に設備投資も更に必要となってしまう。   According to the invention described in Patent Document 2, miniaturization is realized and the shape of the opening is constant. However, since the number of connection terminals of the semiconductor package substrate and the semiconductor chip ranges from several hundred to several thousand, If a laser is used for processing the opening for forming the terminal, the cost is increased and further capital investment is required.

それから、特許文献３に記載の発明によると、このソルダーレジスト層の開口形状で製造を実施すると、まず工程内のウェット処理時の洗浄性が悪化し、開口部に洗浄不足による不純物が残留することで、電気信頼性に大きく影響を及ぼす。また、実装後のはんだがソルダーレジスト層の表層部で凹んだ形状となり、実装後の接続信頼性が著しく低下する。   Then, according to the invention described in Patent Document 3, when manufacturing is performed with the opening shape of the solder resist layer, the cleaning performance at the time of wet processing in the process deteriorates, and impurities due to insufficient cleaning remain in the opening. This greatly affects electrical reliability. In addition, the solder after mounting becomes a concave shape at the surface layer portion of the solder resist layer, so that the connection reliability after mounting is remarkably lowered.

本発明は前記従来の技術の問題点に鑑み成されたものであり、半導体パッケージ基板の配線パターンの細線化、高密度化に伴う、ソルダーレジストの開口径の微細化が進んでも、半導体パッケージ基板と半導体チップの実装歩留まりや接続信頼性が低下せず、電気信頼性を確保した半導体パッケージ基板の供給に有効な、感光性レジスト保護用テープと半導パッケージ基板の製造方法および半導体パッケージ基板を提供することを目的とする。   The present invention has been made in view of the above-described problems of the prior art, and even if the solder resist opening diameter becomes finer as the wiring pattern of the semiconductor package substrate becomes thinner and higher in density, the semiconductor package substrate is improved. Provides a method for manufacturing a photosensitive resist protection tape and a semiconductor package substrate, and a semiconductor package substrate, which are effective in supplying a semiconductor package substrate that ensures electrical reliability without lowering the mounting yield and connection reliability of the semiconductor chip. The purpose is to do.

前記課題を解決するための手段として、請求項１に記載の発明は、少なくとも基材フィルム１ａ、粘着層１ｃ、及び光硬化性樹脂についてこの並びで積層されており、
ソルダーレジストをパターン形成をするための露光に使う露光光に対する、少なくとも該基材フィルム１ａと該粘着層１ｂを含む層の透過率に関して、
（イ）該露光光の少なくとも波長３５０〜４５０ｎｍの領域の光が、少なくとも該基材フィルム１ａと該粘着層１ｂを含む層を透過して該ソルダーレジストに到達できる透過率を有すること、
（ロ）波長３５０〜３８０ｎｍ域の主ピーク強度と、波長４００〜４２０ｎｍ域の主ピーク強度との比が１：１〜１：５の範囲内にあること、
前記（イ）、（ロ）を共に満足することを特徴とする感光性レジスト保護用テープである。 As a means for solving the above-mentioned problem, the invention according to claim 1 is laminated in this order for at least the base film 1a, the adhesive layer 1c, and the photocurable resin,
Regarding at least the transmittance of the layer including the base film 1a and the adhesive layer 1b with respect to the exposure light used for exposure for patterning the solder resist,
(A) Light having a wavelength of at least 350 to 450 nm of the exposure light has a transmittance that can pass through at least the layer including the base film 1a and the adhesive layer 1b to reach the solder resist;
(B) The ratio of the main peak intensity in the wavelength range of 350 to 380 nm and the main peak intensity in the wavelength range of 400 to 420 nm is in the range of 1: 1 to 1: 5.
A photosensitive resist protective tape characterized by satisfying both of the above (a) and (b).

また、請求項２に記載の発明は、前記少なくとも該基材フィルム１ａと該粘着層１ｂを含む層が、少なくとも、３４０ｎｍ以下の紫外線の最大透過率については７０％以下であること、を特徴とする請求項１に記載の感光性レジスト保護用テープである。   The invention according to claim 2 is characterized in that the layer including at least the base film 1a and the adhesive layer 1b has a maximum transmittance of at least 340 nm of ultraviolet rays of 70% or less. The photosensitive resist protective tape according to claim 1.

また、請求項３に記載の発明は、前記基材フィルム１ａと粘着層１ｂのうちいずれか一方か又は両方が、紫外線吸収材を含有していること、を特徴とする請求項１又は２のいずれかに記載の感光性レジスト保護用テープである。   Moreover, invention of Claim 3 WHEREIN: Either one or both of the said base film 1a and the adhesion layer 1b contain the ultraviolet absorber, The feature of Claim 1 or 2 characterized by the above-mentioned. The photosensitive resist protective tape according to any one of the above.

また、請求項４に記載の発明は、前記基材フィルム１ａの片面か又は両面に、１層以上の紫外線吸収層が設けてあること、を特徴とする請求項１又は２のいずれかに記載の感光性レジスト保護用テープである。   The invention according to claim 4 is characterized in that one or more ultraviolet absorbing layers are provided on one side or both sides of the base film 1a. This is a photosensitive resist protective tape.

また、請求項５に記載の発明は、前記紫外線吸収層は、前記基材フィルム１ａ上に紫外線吸収材を含有する樹脂の層を形成したこと、を特徴とする請求項４に記載の感光性レジスト保護用テープである。   The invention according to claim 5 is characterized in that the ultraviolet absorbing layer is formed by forming a resin layer containing an ultraviolet absorbing material on the base film 1a. It is a resist protective tape.

また、請求項６に記載の発明は、前記紫外線吸収層は、単層か又は複数層の誘電体膜が前記基材フィルム１ａ上に形成されていること、を特徴とする請求項４に記載の感光性レジスト保護用テープである。   The invention described in claim 6 is characterized in that the ultraviolet absorbing layer is a single layer or a plurality of layers of dielectric films formed on the base film 1a. This is a photosensitive resist protective tape.

また、請求項７に記載の発明は、前記基材フィルム１ａと粘着層１ｂのうちいずれか一方か又は両方が、紫外線吸収材を含有しており、
且つ、該基材フィルム１ａの片面か又は両面に、１層以上の紫外線吸収層が設けてあること、を特徴とする請求項１又は２のいずれかに記載の感光性レジスト保護用テープである。 In addition, in the invention according to claim 7, either one or both of the base film 1a and the adhesive layer 1b contains an ultraviolet absorber,
The photosensitive resist protecting tape according to claim 1, wherein one or more ultraviolet absorbing layers are provided on one side or both sides of the base film 1 a. .

また、請求項８に記載の発明は、請求項１乃至７のいずれかに記載の感光性レジスト保護用テープを前記粘着層１ｂを介して、作製途中の半導体パッケージ基板上の前記ソルダーレジスト層の面に接触させ、所望するパターンに応じて選択的な露光を行うことにより該ソルダーレジスト層のパターニングを行うこと、を特徴とする半導体パッケージ基板の製造方法である。   Moreover, the invention according to claim 8 is the photosensitive resist protection tape according to any one of claims 1 to 7, wherein the solder resist layer on the semiconductor package substrate being produced is interposed through the adhesive layer 1 b. A method of manufacturing a semiconductor package substrate, comprising: patterning the solder resist layer by contacting a surface and performing selective exposure according to a desired pattern.

また、請求項９に記載の発明は、請求項１乃至７のいずれかに記載の感光性レジスト保護用テープを用いて形成されるソルダーレジスト層の複数有る開口の個々の開口径の個々の大きさの広がり方が、半導体チップと半導体パッケージ基板とが電気的に接続される接続端子部から該半導体チップの方に向かって、径が徐々に大きく広がっていること、を特徴とする半導体パッケージ基板である。   Further, the invention according to claim 9 is an individual size of each opening diameter of a plurality of openings of the solder resist layer formed by using the photosensitive resist protection tape according to any one of claims 1 to 7. The semiconductor package substrate characterized in that the diameter gradually increases from the connecting terminal portion where the semiconductor chip and the semiconductor package substrate are electrically connected toward the semiconductor chip. It is.

本発明によると、基材フィルム１ａと、基材フィルム１ｂの片面に形成される粘着層１ｃと粘着層１ｃに貼合される支持フィルム１ｂとからなる感光性レジスト保護用テープが、粘着層１ｃの支持フィルム１ｂと接する面は、粘着層１ｂがソルダーレジスト層と接触し、ソルダーレジスト層をパターニングするための露光を実施した際に、感光性レジスト保護用テープが光を適度に反射してしまうこと／若しくは吸収してしまうことによって、ソルダーレジスト層に到達する光の分光波長および強度を適度に制御してしまう作用を呈する。   According to the present invention, a photosensitive resist protective tape comprising a base film 1a, an adhesive layer 1c formed on one side of the base film 1b, and a support film 1b bonded to the adhesive layer 1c is an adhesive layer 1c. When the adhesive layer 1b comes into contact with the solder resist layer and the exposure for patterning the solder resist layer is performed, the photosensitive resist protective tape appropriately reflects light on the surface in contact with the support film 1b. By absorbing / absorbing, the spectral wavelength and intensity of light reaching the solder resist layer are appropriately controlled.

その結果として、ソルダーレジスト層の表層部の開口の閉塞を制御することにより、半導体パッケージ基板と半導体チップの実装歩留まりとか、その実装後の接続信頼性の向上とか微細化に伴う実装歩留まり、あるいは接続信頼性の低下を抑制できるソルダーレジスト層の開口形状の形成を実現できる。
また本発明によると、従来の設備での生産も可能で、低コストでの生産も可能となる。 As a result, by controlling the closure of the surface layer opening of the solder resist layer, the mounting yield of the semiconductor package substrate and the semiconductor chip, the improvement of the connection reliability after the mounting, the mounting yield accompanying the miniaturization, or the connection Formation of the opening shape of the solder resist layer that can suppress the decrease in reliability can be realized.
In addition, according to the present invention, it is possible to produce with conventional equipment and to produce at low cost.

本発明に係る感光性レジスト保護用テープは、基材フィルムと粘着層に光（紫外線）を反射する／若しくは吸収する作用を呈することにより、ソルダーレジスト層の露光後の光重合反応を制御してしまうよう作用することで、形成される開口の形状を制御し、半導体パッケージ基板と半導体チップが実装される際の歩留まりの向上とか、実装後の接続信頼性を確保した半導体パッケージ基板を供給することに有効となる。
また、本発明のソルダーレジスト層の開口形状を制御する技術は、感光性レジスト保護用テープを未露光ソルダーレジスト層に貼付すると云う簡便な措置で提供できる。 The tape for protecting a photosensitive resist according to the present invention controls the photopolymerization reaction after exposure of the solder resist layer by reflecting / absorbing light (ultraviolet rays) to the base film and the adhesive layer. In this way, the shape of the opening to be formed is controlled to improve the yield when the semiconductor package substrate and the semiconductor chip are mounted, or to supply a semiconductor package substrate that ensures connection reliability after mounting. Effective.
In addition, the technique for controlling the opening shape of the solder resist layer of the present invention can be provided by a simple measure of attaching a photosensitive resist protective tape to an unexposed solder resist layer.

つまるところ、半導体パッケージ基板と半導体チップが実装される際の歩留まりの向上とか、実装後の接続信頼性の向上を、従来の設備、低コストで提供でき、結果的には半導体パッケージ基板や半導体装置の耐熱性、耐湿性の改善や振動等の耐環境性を向上させることができる。
また本発明は、半導体パッケージ基板だけに限って適用できるものではなく、感光性樹脂材料を用いる部材の感光性樹脂層をパターニングする際の開口形状の制御にも適用できる。 In other words, it is possible to provide improvements in yield when semiconductor package substrates and semiconductor chips are mounted, and improved connection reliability after mounting at low cost with conventional equipment. As a result, semiconductor package substrates and semiconductor devices It is possible to improve heat resistance and moisture resistance and environmental resistance such as vibration.
Further, the present invention is not limited to the semiconductor package substrate, but can also be applied to control of the opening shape when patterning the photosensitive resin layer of a member using a photosensitive resin material.

従来の感光性レジスト保護用テープの一例を、模式的な断面図で示す説明図。Explanatory drawing which shows an example of the conventional tape for photosensitive resist protection with typical sectional drawing. 本発明に係る感光性レジスト保護用テープの一例を、模式的な断面図で示す説明図。BRIEF DESCRIPTION OF THE DRAWINGS Explanatory drawing which shows an example of the photosensitive resist protection tape which concerns on this invention with typical sectional drawing. 本発明に係る感光性レジスト保護用テープの他の一例を、模式的な断面図で示す説明図。Explanatory drawing which shows another example of the photosensitive resist protection tape which concerns on this invention with typical sectional drawing. 本発明に係る感光性レジスト保護用テープのまた他の一例を、模式的な断面図で示す説明図。Explanatory drawing which shows another example of the photosensitive resist protection tape which concerns on this invention with typical sectional drawing. 本発明に係る感光性レジスト保護用テープの更に他の一例を、模式的な断面図で示す説明図。An explanatory view showing still another example of a photosensitive resist protection tape concerning the present invention with a typical sectional view. 一般的な半導体パッケージ基板の一例を、模式的な断面図で示す説明図。Explanatory drawing which shows an example of a common semiconductor package board | substrate with typical sectional drawing. 一般的な半導体パッケージ基板のコア層の一例を、模式的な断面図で示す説明図。Explanatory drawing which shows an example of the core layer of a common semiconductor package board | substrate with typical sectional drawing. 一般的な半導体パッケージ基板のビルドアップ層の製造方法の一例を、模式的な断面図で示す説明図。Explanatory drawing which shows an example of the manufacturing method of the buildup layer of a common semiconductor package board | substrate with typical sectional drawing. 一般的な半導体パッケージ基板の他の一例となる３次元配線基板を、模式的な断面図で示す説明図。Explanatory drawing which shows the three-dimensional wiring board used as another example of a general semiconductor package board | substrate with typical sectional drawing. 一般的な半導体パッケージ基板のソルダーレジスト層の形成方法の一例を、模式的な断面図で示す説明図。Explanatory drawing which shows an example of the formation method of the soldering resist layer of a general semiconductor package board | substrate with typical sectional drawing. 従来のソルダーレジスト層の開口形状の一例を、模式的な断面図で示す説明図。Explanatory drawing which shows an example of the opening shape of the conventional soldering resist layer with typical sectional drawing. 本発明に関係するソルダーレジスト層の開口形状の一例を、模式的な断面図で示す説明図。Explanatory drawing which shows an example of the opening shape of the soldering resist layer relevant to this invention with typical sectional drawing.

本発明を実施するための形態について、以下で図面を参照しながら説明する。
ソルダーレジスト保護用粘着フィルムの基本構造は図１に示すように、基材フィルム１ａと支持フィルム１ｂの間に粘着層１ｃを設けた構造となる。 EMBODIMENT OF THE INVENTION The form for implementing this invention is demonstrated referring drawings below.
As shown in FIG. 1, the basic structure of the solder resist protecting adhesive film is a structure in which an adhesive layer 1c is provided between the base film 1a and the support film 1b.

基材フィルム１ａとしては、光透過性に優れたものであれば良く、例えば、ポリエチレン、ポリプロピレン、ポリブテン等のポリオレフィン、エチレン−ビニルアルコール共重合体、ポリスチレン、ポリエチレンテレフタレート、ポリエステル、ポリブチレンテレフタレート、ポリエチレン−２，６−ナフタレート等のポリエステル、ナイロン６、ナイロン１１、芳香族ポリアミド、ポリカーボネート、ポリ塩化ビニル、ポリ塩化ビニリデン、ポリイミド等の樹脂からなるもの等が挙げられる。特に、透明性の高いフィルムである汎用のポリエチレンテレフタレート、ポリエチレン、ポリエチレンテレフタレート等が好ましい。基材フィルムの厚みは２〜５０μｍ、好ましくは４〜２０μｍが光透過性の観点から適している。   The base film 1a may be any material as long as it is excellent in light transmission, for example, polyolefins such as polyethylene, polypropylene, polybutene, ethylene-vinyl alcohol copolymer, polystyrene, polyethylene terephthalate, polyester, polybutylene terephthalate, polyethylene. Examples thereof include polyesters such as −2,6-naphthalate, nylon 6, nylon 11, aromatic polyamide, polycarbonate, polyvinyl chloride, polyvinylidene chloride, polyimide, and the like. In particular, general-purpose polyethylene terephthalate, polyethylene, polyethylene terephthalate and the like, which are highly transparent films, are preferable. The thickness of the base film is 2 to 50 μm, preferably 4 to 20 μm, from the viewpoint of light transmittance.

支持フィルム１ｂとしては、ソルダーレジスト層に貼付される前に、感光性レジスト保護用テープより剥離されるもので、離型性が高いものであれば特に限定せず、必要に応じて、シリコーン離型材等を用いて離型処理を施してもよい。ポリエチレンテレフタレートやポリエチレン等が汎用的なものであり、適している。厚みは、特に限定されないが、１０〜３０μｍがコスト、取扱い性の観点から適している。   The support film 1b is not particularly limited as long as it is peeled off from the photosensitive resist protection tape before being attached to the solder resist layer, and has high releasability. You may perform a mold release process using a mold material. Polyethylene terephthalate, polyethylene, etc. are general-purpose and suitable. Although thickness is not specifically limited, 10-30 micrometers is suitable from a viewpoint of cost and handleability.

粘着層１ｃとしては、アクリル系接着材、ゴム系接着材等を用い、光透過性、ソルダーレジスト露光時の解像性の等の観点からアクリル系接着材が好ましい。   As the pressure-sensitive adhesive layer 1c, an acrylic adhesive, a rubber adhesive, or the like is used, and an acrylic adhesive is preferable from the viewpoints of light transmittance, resolution at the time of solder resist exposure, and the like.

アクリル系接着材としては、（メタ）アクリル酸アルキルエステルを主成分とし、例えば、アクリル酸ｎ−ブチル、アクリル酸イソブチル、アクリル酸ヘキシル、アクリル酸オクチル、アクリル酸２−エチルヘキシル、アクリル酸イソオクチル、アクリル酸デシル、アクリル酸イソデシル、メタクリル酸２−エチルヘキシル、メタクリル酸イソオクチル、メタクリル酸デシル、メタクリル酸イソデシル、メタクリル酸ラウリル等がある。   As an acrylic adhesive, (meth) acrylic acid alkyl ester as a main component, for example, n-butyl acrylate, isobutyl acrylate, hexyl acrylate, octyl acrylate, 2-ethylhexyl acrylate, isooctyl acrylate, acrylic Examples include decyl acid, isodecyl acrylate, 2-ethylhexyl methacrylate, isooctyl methacrylate, decyl methacrylate, isodecyl methacrylate, and lauryl methacrylate.

このような基本構造を持った感光性レジスト保護用テープに、前記の反射／若しくは吸収の光学特性を付与する為、図２で例示したように、紫外線吸収材が基材フィルム２ａと粘着層２ｃの少なくとも一方に含有されたものである。
紫外線吸収材としては、例えば、ベンゾフェノン系化合物、ベンゾトリアゾール系化合物、環状イミノエステル系、サリチル酸系化合物、ハイドロキノン系化合物、又はヒドロキシフェニルトリアジン系化合物、等がある。これらの中でも特にヒドロキシフェニルトリアジン系化合物が、耐熱性、透明性、又は紫外線吸収性の観点から好ましい。尚、紫外線吸収材は単独で用いても良いが、必要に応じて２種類以上を併用して用いることも可能である。 In order to give the above-mentioned reflection / or absorption optical characteristics to the photosensitive resist protective tape having such a basic structure, as illustrated in FIG. 2, the ultraviolet absorber is made of a base film 2a and an adhesive layer 2c. In at least one of the above.
Examples of the ultraviolet absorber include benzophenone compounds, benzotriazole compounds, cyclic imino ester compounds, salicylic acid compounds, hydroquinone compounds, and hydroxyphenyltriazine compounds. Among these, hydroxyphenyltriazine compounds are particularly preferable from the viewpoints of heat resistance, transparency, and ultraviolet absorption. In addition, although an ultraviolet absorber may be used independently, it is also possible to use it in combination of 2 or more types as needed.

ヒドロキシフェニルトリアジン系化合物としては、以下に限定されるものではないが、2-(4,6-ビス(2,4-ジメチルフェニル)-1,3,5-トリアジン-2-イル)-5-ヒドロキシフェニル、2-(2,4-ジヒドロキシフェニル)-4,6-ビス-(2,4-ジメチルフェニル)-1,3,5-トリアジンと(2-エチルヘキシル)-グリシド酸エステル、2,4-ビス「2-ヒドロキシ-4-ブトキシフェニル]-6-(2,4-ジブトキシフェニル)-1,3-5-トリアジン、又は、2-(4,6-ジフェニル-1,3,5-トリアジン-2-イル)-5-(ヘキシル)オキシフェノール、等が例示として挙げられる。
本発明では、紫外線吸収材の基材フィルム主成分への添加濃度としては、０．０１〜１０重量％が良く、より好ましくは０．０５〜５重量％、更に好ましくは０．０１〜３重量％である。
尚、紫外線吸収材の添加量が０．０１重量％未満の場合は紫外線を吸収する能力が劣る為に、また１０重量％を超える場合にはポリエステルフィルムの機械特性が著しく低下するため、どちらもあまり好ましくない。
これらの紫外線吸収材を基材フィルム２ａもしくは粘着材２ｃを塗工する際に予め適宜含有させることで、所望の光学特性を得ることができる。 The hydroxyphenyltriazine-based compound is not limited to the following, but 2- (4,6-bis (2,4-dimethylphenyl) -1,3,5-triazin-2-yl) -5- Hydroxyphenyl, 2- (2,4-dihydroxyphenyl) -4,6-bis- (2,4-dimethylphenyl) -1,3,5-triazine and (2-ethylhexyl) -glycidic acid ester, 2,4 -Bis "2-hydroxy-4-butoxyphenyl] -6- (2,4-dibutoxyphenyl) -1,3-5-triazine or 2- (4,6-diphenyl-1,3,5- Examples include triazin-2-yl) -5- (hexyl) oxyphenol.
In the present invention, the concentration of the ultraviolet absorber added to the main component of the base film is preferably 0.01 to 10% by weight, more preferably 0.05 to 5% by weight, and still more preferably 0.01 to 3% by weight. %.
In addition, since the ability to absorb ultraviolet rays is inferior when the addition amount of the ultraviolet absorbing material is less than 0.01% by weight, and the mechanical properties of the polyester film are remarkably deteriorated when exceeding 10% by weight, both Not very good.
Desirable optical characteristics can be obtained by appropriately containing these ultraviolet absorbing materials in advance when the base film 2a or the adhesive material 2c is applied.

また、感光性レジスト保護用テープに前記の光学特性を付与する為の、他の有効な手段として、図３や図４に示すように、基材フィルム３ａ、４ａの少なくとも片面に紫外線吸収層３ｄ、４ｄを設ける方法である。紫外線吸収層の種類および形成方法を説明する。   As another effective means for imparting the above-mentioned optical characteristics to the photosensitive resist protective tape, as shown in FIG. 3 and FIG. 4, an ultraviolet absorbing layer 3d is provided on at least one surface of the base films 3a and 4a. 4d. The type and formation method of the ultraviolet absorbing layer will be described.

１つは、紫外線吸収材を含有した高分子層３ｄを基材フィルム３ａ上に形成する方法である。紫外線吸収材は前期基材フィルム１ａに添加する要領で、高分子層３ｄの主成分となるバインダー樹脂に添加する。バインダー樹脂としては、例えば、ポリエチレン、ポリプロピレン、ポリエチレンテレフタレート、ポリスチレン、ポリ塩化ビニル、ポリエステル系の樹脂を形成するためのモノマーがあり、必要に応じて、水系や有機系の溶媒を用いて希釈しても良い。   One is a method of forming a polymer layer 3d containing an ultraviolet absorber on the base film 3a. The ultraviolet absorbing material is added to the binder resin which is the main component of the polymer layer 3d in the manner to be added to the base film 1a. As the binder resin, for example, there are monomers for forming polyethylene, polypropylene, polyethylene terephthalate, polystyrene, polyvinyl chloride, and polyester resins, which can be diluted with an aqueous or organic solvent as necessary. Also good.

上記、高分子層３ｄの基材フィルム３ａ上への塗工は、グラビアコーティング、オフセットコーティング、バーコーティング、エアーナイフコーティング、ロッドブレードコーティング、又はピュアブレードコーティング、等の塗工方法で行うことができ、特に限定されないが、高分子層の厚みとして１０μｍ以下であることが好ましい。   The coating of the polymer layer 3d on the base film 3a can be performed by a coating method such as gravure coating, offset coating, bar coating, air knife coating, rod blade coating, or pure blade coating. Although not particularly limited, the thickness of the polymer layer is preferably 10 μm or less.

１つは、誘電体膜４ｄを上記基材フィルム上４ａ上に形成する方法である。誘電体膜４ｄの材料としては、例えば金属酸化物を材料としたＺｒＯ２、ＴｉＯ２、ＣｅＯ２、Ｔａ２Ｏ５、Ｙ２Ｏ３、ＺｎＳ、Ａｌ２Ｏ３、ＣｅＦ、ＭｇＦ２、又はＳｉＯ２、等を挙げることができ、これらの中から適宜選択し適用して良い。 One is a method of forming the dielectric film 4d on the base film 4a. As a material of the dielectric film 4d, for example, ZrO 2 , TiO 2 , CeO 2 , Ta 2 O 5 , Y 2 O 3 , ZnS, Al 2 O 3 , CeF, MgF 2 , or SiO using a metal oxide as a material. 2 and the like, and may be appropriately selected and applied from these.

前記の誘電体膜４ｄの基材フィルム４ａ上への形成方法としては、例えば、上記、金属酸化物をターゲット材料として、真空蒸着法、プラズマ法、スパッタ法等の方法で形成する。また、誘電体膜は所望の光学特性を得る為に、単層もしくは異なる材料を用いて複数層重ねて形成することも可能である。   As a method for forming the dielectric film 4d on the base film 4a, for example, the above-described metal oxide is used as a target material and formed by a method such as a vacuum deposition method, a plasma method, or a sputtering method. In addition, the dielectric film can be formed as a single layer or a plurality of layers using different materials in order to obtain desired optical characteristics.

更に、図５に示す様に、紫外線吸収材を含有させた基材フィルム２ａ’上に前記の高分子層３ｄ’や、又は誘電体膜４ｄ’を、若しくはそれらの組み合わせで所望の特性を得ることもできる。   Further, as shown in FIG. 5, desired characteristics are obtained by using the polymer layer 3d ′ or the dielectric film 4d ′ on the base film 2a ′ containing the ultraviolet absorber or a combination thereof. You can also.

本発明の上記感光性レジスト保護用テープは支持フィルムを剥離し、基材フィルムと粘着層、更に、紫外線吸収特性を保持する為に設けた、高分子層もしくは誘電体膜とそれらの組合せがソルダーレジスト層側に粘着層が接するように貼付される。   The above-mentioned photosensitive resist protective tape of the present invention peels off the support film, the base film and the adhesive layer, and the polymer layer or dielectric film provided in order to maintain the ultraviolet absorption property and the combination thereof are the solder. It is stuck so that the adhesive layer is in contact with the resist layer side.

半導体パッケージ基板の製造工程で、配線パターンの最外層上にソルダーレジスト層をパターニングするための露光工程で、露光の光が上記ソルダーレジスト層に貼付された感光性レジスト保護用テープを通過し、未硬化のソルダーレジストに到達する際の分光波長の３５０〜３８０ｎｍ域の主ピーク強度と、４００〜４２０ｎｍ域の主ピーク強度の比が １：１〜１：５ となるようにして、前記のように感光性レジスト保護用テープを得る。
尚、感光性レジスト保護用テープの紫外線吸収特性は、露光時に用いる光源の分光波長に応じて適宜調整が必要となる。 In the manufacturing process of the semiconductor package substrate, in the exposure process for patterning the solder resist layer on the outermost layer of the wiring pattern, the exposure light passes through the photosensitive resist protection tape affixed to the solder resist layer, As described above, the ratio of the main peak intensity in the 350 to 380 nm region of the spectral wavelength when reaching the cured solder resist and the main peak intensity in the 400 to 420 nm region is 1: 1 to 1: 5. A photosensitive resist protective tape is obtained.
Note that the ultraviolet absorption characteristics of the photosensitive resist protective tape need to be adjusted as appropriate according to the spectral wavelength of the light source used during exposure.

次に、感光性レジスト保護用テープを半導体パッケージ基板に適用し、本発明の目的である効果を実現させるための工程を図６を用いて説明する。
まず半導体パッケージ基板の構造については、半導体パッケージ基板Ａはコア層６ａ、コア層６ａの両面に絶縁層６ｃとレーザービア６ｄとメッキによる配線パターン６ｅからなるビルドアップ層６ｂ、６ｂ’、ビルドアップ最外層の接続端子部６ｆ、６ｆ’が開口するように形成されたソルダーレジスト層６ｇと半導体チップＢと接続するはんだバンプ（ＦＣバンプ）６ｈ、マザーボード等のプリント基板と接続するはんだバンプ（ＢＧＡバンプ）６ｈ’から構成されている。また、半導体パッケージ基板Ａと半導体チップＢとの接続は、ＦＣバンプ６ｈが半導体パッケージ基板Ａのソルダーレジスト開口部より露出する接続端子６ｆと半導体チップＢの端子を実装工程により電気的に接続する。
尚、本発明で云う、実装時の歩留まり向上とか実装後の接続信頼性に大きく関わるのは、特に図６（Ｃ）となる。 Next, a process for applying the photosensitive resist protection tape to the semiconductor package substrate and realizing the effect of the present invention will be described with reference to FIG.
First, regarding the structure of the semiconductor package substrate, the semiconductor package substrate A has a core layer 6a, build-up layers 6b and 6b 'each including an insulating layer 6c, a laser via 6d, and a plated wiring pattern 6e on both surfaces of the core layer 6a. Solder resist layer 6g formed so that connection terminal portions 6f and 6f 'of the outer layer are opened, solder bump (FC bump) 6h connected to semiconductor chip B, and solder bump (BGA bump) connected to a printed circuit board such as a mother board 6h '. The semiconductor package substrate A and the semiconductor chip B are connected by electrically connecting the connection terminals 6f where the FC bumps 6h are exposed from the solder resist opening of the semiconductor package substrate A and the terminals of the semiconductor chip B by a mounting process.
Note that FIG. 6C particularly relates to the improvement in yield at the time of mounting or the connection reliability after mounting, as referred to in the present invention.

次に、半導体パッケージ基板の製造工程について図７を用いて説明する。
コア層の構造を図７に示す。コア層７ａはガラスクロスにエポキシ樹脂等を含浸させた両面銅張り基板を用い、ドリルによりスルーホール７ｂ形成をし、パネルメッキとエッチングにより配線パターン７ｃを形成する、両面の導通はスルーホール形成後のパネルめっきにより確保する。 Next, the manufacturing process of the semiconductor package substrate will be described with reference to FIG.
The structure of the core layer is shown in FIG. The core layer 7a uses a double-sided copper-clad substrate in which a glass cloth is impregnated with epoxy resin, etc., and through holes 7b are formed by drilling, and wiring patterns 7c are formed by panel plating and etching. Secure by panel plating.

次いで、図８にあるように、コア層８ａの両面に真空プレス機等を用いて、絶縁樹脂８ｂをラミネートする。次いで、絶縁樹脂に埋め込まれた配線パターン８ｃをレーザーにより露出させビアホール８ｄを形成する。ここで、レーザーは炭酸ガスレーザー、ＵＶレーザー等が用いられる。
次いで、露出した配線パターン８ｃと絶縁樹脂上に形成する配線パターンとを電気的に接続する為に、無電解銅メッキ８ｅの形成をし、感光性ドライフィルムレジスト８ｆを配線パターンが形成されない領域に設ける。
次いで、パターンメッキを施し、配線パターン８ｇを形成した後に、感光性ドライフィルムレジストを苛性ソーダにより剥離する。
次いで、配線パターン８ｇを形成しない領域の無電解銅メッキをエッチングにより除去し、ビルドアップ層の１層分が完成する。この工程を所望の層数分繰り返し行い、３次元配線基板（図９）を形成する。 Next, as shown in FIG. 8, the insulating resin 8b is laminated on both surfaces of the core layer 8a by using a vacuum press or the like. Next, the wiring pattern 8c embedded in the insulating resin is exposed by a laser to form a via hole 8d. Here, a carbon dioxide laser, a UV laser, or the like is used as the laser.
Next, in order to electrically connect the exposed wiring pattern 8c and the wiring pattern formed on the insulating resin, the electroless copper plating 8e is formed, and the photosensitive dry film resist 8f is formed in a region where the wiring pattern is not formed. Provide.
Next, after pattern plating is performed to form a wiring pattern 8g, the photosensitive dry film resist is peeled off with caustic soda.
Next, the electroless copper plating in the region where the wiring pattern 8g is not formed is removed by etching, and one build-up layer is completed. This process is repeated for the desired number of layers to form a three-dimensional wiring board (FIG. 9).

次いで、ソルダーレジスト層の形成を図１０を用いて説明する。３次元配線基板の最外層にロールコーターもしくはスクリーン印刷によりソルダーレジストを塗工し、乾燥することで、未硬化ソルダーレジスト１０ａを形成する。また、ソルダーレジストが半硬化樹脂の場合は真空ラミネータ等により、ラミネートにて形成する。
次いで、乾燥した未硬化ソルダーレジスト層上に、本発明に関わる感光性レジスト保護用テープ１０ｂをロールラミネーター等を用いて、貼付する。
次いで、接続端子を露出する為に、所望の露出部分をガラスマスク等の遮光パターン１０ｃにてマスキングし、露光によりマスキング部以外を光硬化させ、露光後に感光性レジスト保護用テープを剥離して、現像を行い、ソルダーレジスト開口部１０ｄを形成する。 Next, the formation of the solder resist layer will be described with reference to FIG. An uncured solder resist 10a is formed by applying a solder resist to the outermost layer of the three-dimensional wiring board by a roll coater or screen printing and drying. When the solder resist is a semi-cured resin, it is formed by lamination using a vacuum laminator or the like.
Next, the photosensitive resist protecting tape 10b according to the present invention is stuck on the dried uncured solder resist layer using a roll laminator or the like.
Next, in order to expose the connection terminal, a desired exposed portion is masked with a light-shielding pattern 10c such as a glass mask, and other than the masking portion is photocured by exposure, and after exposure, the photosensitive resist protection tape is peeled off, Development is performed to form a solder resist opening 10d.

次いで、ソルダーレジストを完全硬化させるために、熱と光の２次処理を実施する。
次いで、開口部に、印刷によりはんだインキを印刷、リフローを実施することにより、はんだバンプ１０ｅを形成し半導体パッケージ基板となる。 Next, in order to completely cure the solder resist, a secondary treatment with heat and light is performed.
Next, solder ink is printed in the opening by printing and reflowing is performed, thereby forming solder bumps 10e to form a semiconductor package substrate.

本発明に使用する半導体パッケージ基板は上記工程により作成し、効果の確認をしたものである。硬化の確認の為、図１０の１０ｂで使用する紫外線吸収機能を付与した感光性レジスト保護用テープを用いて実施した。   The semiconductor package substrate used in the present invention is prepared by the above process and the effect is confirmed. For confirmation of curing, a photosensitive resist protective tape provided with an ultraviolet absorbing function used in 10b of FIG. 10 was used.

ビルドアップ基板に、ロールコーターにてソルダーレジスト（太陽インキ製造（株）製、ＰＳＲ−４０００）を接続端子上の乾燥膜厚が２０〜３０μｍとなるように塗布し、それぞれの紫外線吸収特性を持つ感光性レジスト保護用テープをロールラミネーターによりラミネートし、露光、現像を実施した。光重合反応を収束させる為、露光後に感光性レジスト保護用テープを剥離するまで、１時間エージングを行い、剥離後、現像を実施した。開口させるためのガラスマスクのマスキング部はφ８０μｍのドットパターンにて評価を実施した。   A solder resist (manufactured by Taiyo Ink Mfg. Co., Ltd., PSR-4000) is applied to the build-up substrate so that the dry film thickness on the connection terminal is 20 to 30 μm, and each has ultraviolet absorption characteristics. A photosensitive resist protective tape was laminated with a roll laminator, and exposure and development were performed. In order to converge the photopolymerization reaction, aging was performed for 1 hour until the photosensitive resist protective tape was peeled off after exposure, and development was carried out after peeling. The masking part of the glass mask for opening was evaluated with a dot pattern of φ80 μm.

効果の確認方法としては、完全硬化後に、断面を観察することにより、ソルダーレジストの開口形状を確認した。開口の形状はソルダーレジスト層の表層部（上部）の開口径と接続端子側（下部）の開口径を測定した。   As a method for confirming the effect, the opening shape of the solder resist was confirmed by observing the cross section after complete curing. As for the shape of the opening, the opening diameter of the surface layer part (upper part) and the opening diameter of the connection terminal side (lower part) of the solder resist layer were measured.

感光性レジスト保護用テープについて、ソルダーレジスト層に到達する分光波長の３５０〜３８０ｎｍ域の主ピーク強度と、４００〜４２０ｎｍ域の主ピーク強度の比を １：２ になるよう、紫外線吸収特性を調整したテープを用いて、ソルダーレジスト層を形成した。   Adjust the UV absorption characteristics of the photosensitive resist protection tape so that the ratio of the main peak intensity in the 350 to 380 nm region of the spectral wavelength reaching the solder resist layer and the main peak intensity in the 400 to 420 nm region is 1: 2. A solder resist layer was formed using the tape thus prepared.

感光性レジスト保護用テープについて、ソルダーレジスト層に到達する分光波長の３５０〜３８０ｎｍ域の主ピーク強度と、４００〜４２０ｎｍ域の主ピーク強度の比を １：１．１２ になるよう、紫外線吸収特性を調整したテープを用いた以外は、実施例１の場合と同様にして、ソルダーレジスト層を形成した。   About the photosensitive resist protective tape, the ultraviolet absorption characteristics so that the ratio of the main peak intensity in the 350 to 380 nm region of the spectral wavelength reaching the solder resist layer and the main peak intensity in the 400 to 420 nm region is 1: 1.12. A solder resist layer was formed in the same manner as in Example 1 except that a tape with adjusted was used.

比較例Comparative example

感光性レジスト保護用テープについて、紫外線吸収特性の調整をしないテープを用いてソルダーレジスト層の形成を実施した。この際のソルダーレジスト層に到達する分光波長の３５０〜３８０ｎｍ域の主ピーク強度と、４００〜４２０ｎｍ域の主ピーク強度の比は １．１６：１．０ であった。   With respect to the photosensitive resist protective tape, a solder resist layer was formed using a tape whose ultraviolet absorption characteristics were not adjusted. In this case, the ratio of the main peak intensity in the 350 to 380 nm region of the spectral wavelength reaching the solder resist layer and the main peak intensity in the 400 to 420 nm region was 1.16: 1.0.

Figure 2010238917
Figure 2010238917

実施例１、実施例２、及び比較例の結果を表１に示す。
表１から明らかなように、実施例１、２で得られた開口径は、表層部（上部）と接続端子側（下部）を比較すると、図１１のように上部の開口径の方が大きく仕上がっている。それに対して、比較例の開口径は図１２のように下部の方が大きく仕上がっている。
つまり、実施例１、２の様に露光時にソルダーレジスト層に到達する光を感光性レジスト保護用テープにより制御することにより、比較例の開口径のような、表層部（上部）の開口が閉塞してしまう不具合を抑制することができ、実装時の接続性に有利に働くことが判る。 Table 1 shows the results of Example 1, Example 2, and Comparative Example.
As is clear from Table 1, the opening diameters obtained in Examples 1 and 2 are larger in the upper opening diameter as shown in FIG. 11 when the surface layer part (upper part) and the connection terminal side (lower part) are compared. It is finished. On the other hand, the opening diameter of the comparative example is finished larger in the lower part as shown in FIG.
In other words, by controlling the light reaching the solder resist layer at the time of exposure with the photosensitive resist protective tape as in Examples 1 and 2, the surface layer (upper) opening, such as the opening diameter of the comparative example, is blocked. It can be seen that the problem of the failure can be suppressed, and it is advantageous for the connectivity at the time of mounting.

１ａ、２a、２ａ′３ａ、４ａ ・・・基材フィルム
１ｂ、２ｂ、２ｂ′、３ｂ、４ｂ ・・・支持フィルム
１ｃ、２ｃ、２ｃ′、３ｃ、４ｃ ・・・粘着層
３ｄ、３ｄ′ ・・・・・高分子層
４ｄ、４ｄ′ ・・・・・誘電体層
Ａ ・・・・・・・・・・半導体パッケージ基板
Ｂ ・・・・・・・・・・半導体チップ
Ｃ ・・・・・・・・・・半導体パッケージ基板と半導体チップのはんだ接続部
６ａ、７ａ、８ａ ・・・コア層
６ｂ、６ｂ′ ・・・・・ビルドアップ層
６ｃ、８ｂ ・・・・・・絶縁層
６ｄ ・・・・・・・・・レーザービア
６ｅ、８ｃ、８ｇ ・・・配線パターン
６ｆ ・・・・・・・・・接続端子（ＦＣ側）
６ｆ′ ・・・・・・・・接続端子（ＢＧＡ側）
６ｇ ・・・・・・・・・ソルダーレジスト層
７ｂ ・・・・・・・・・スルーホール
７ｃ ・・・・・・・・・配線
８ｄ ・・・・・・・・・ビアホール
８ｅ ・・・・・・・・・無電解メッキ
８ｆ ・・・・・・・・・感光性ドライフィルム
１０ａ ・・・・・・・・未硬化ソルダーレジスト
１０ｂ ・・・・・・・・感光性レジスト保護用テープ
１０ｃ ・・・・・・・・遮光パターン
１０ｄ ・・・・・・・・ソルダーレジスト開口部
１０ｅ ・・・・・・・・はんだバンプ 1a, 2a, 2a'3a, 4a ... base film 1b, 2b, 2b ', 3b, 4b ... support film 1c, 2c, 2c', 3c, 4c ... adhesive layer 3d, 3d ' ..... Polymer layers 4d, 4d '... Dielectric layer A ... ... Semiconductor package substrate B ... ... Semiconductor chip C ... .... Solder joints 6a, 7a, 8a between the semiconductor package substrate and the semiconductor chip ... Core layers 6b, 6b '... Build-up layers 6c, 8b ... ... Insulating layers 6d ··············· Laser vias 6e, 8c, 8g ··· Wiring pattern 6f ····································· FC
6f '... Connection terminal (BGA side)
6g ... Solder resist layer 7b ... Through hole 7c ... Wiring 8d ... Via hole 8e ...・ ・ ・ ・ ・ ・ ・ ・ ・ Electroless plating 8f ・ ・ ・ ・ ・ ・ ・ ・ ・ Photosensitive dry film 10a ・ ・ ・ ・ ・ ・ ・ ・ Uncured solder resist 10b ・ ・ ・ ・ ・ ・ ・ ・ Photosensitive resist protection Tape 10c for light shielding pattern 10d for solder resist opening 10e for solder bump

Claims (9)

少なくとも基材フィルム１ａ、粘着層１ｃ、及び光硬化性樹脂についてこの並びで積層されており、
ソルダレジストをパターン形成をするための露光に使う露光光に対する、少なくとも該基材フィルム１ａと該粘着層１ｂを含む層の透過率に関して、
（イ）該露光光の少なくとも波長３５０〜４５０ｎｍの領域の光が、少なくとも該基材フィルム１ａと該粘着層１ｂを含む層を透過して該ソルダーレジストに到達できる透過率を有すること、
（ロ）波長３５０〜３８０ｎｍ域の主ピーク強度と、波長４００〜４２０ｎｍ域の主ピーク強度との比が１：１〜１：５の範囲内にあること、
前記（イ）、（ロ）を共に満足することを特徴とする感光性レジスト保護用テープ。 At least the base film 1a, the pressure-sensitive adhesive layer 1c, and the photocurable resin are laminated in this arrangement,
Regarding the transmittance of the layer including at least the base film 1a and the adhesive layer 1b with respect to the exposure light used for exposure for patterning the solder resist,
(A) Light having a wavelength of at least 350 to 450 nm of the exposure light has a transmittance that can pass through at least the layer including the base film 1a and the adhesive layer 1b to reach the solder resist;
(B) The ratio of the main peak intensity in the wavelength range of 350 to 380 nm and the main peak intensity in the wavelength range of 400 to 420 nm is in the range of 1: 1 to 1: 5.
A photosensitive resist protective tape characterized by satisfying both of the above (a) and (b). 前記少なくとも該基材フィルム１ａと該粘着層１ｂを含む層が、少なくとも、３４０ｎｍ以下の紫外線の最大透過率については７０％以下であること、を特徴とする請求項１に記載の感光性レジスト保護用テープ。   2. The photosensitive resist protection according to claim 1, wherein the layer including at least the base film 1 a and the adhesive layer 1 b has a maximum transmittance of at least 340 nm of ultraviolet rays of 70% or less. Tape. 前記基材フィルム１ａと粘着層１ｂのうちいずれか一方か又は両方が、紫外線吸収材を含有していること、を特徴とする請求項１又は２のいずれかに記載の感光性レジスト保護用テープ。   Either one or both of the base film 1a and the pressure-sensitive adhesive layer 1b contains an ultraviolet absorber, The photosensitive resist protecting tape according to claim 1 or 2, . 前記基材フィルム１ａの片面か又は両面に、１層以上の紫外線吸収層が設けてあること、を特徴とする請求項１又は２のいずれかに記載の感光性レジスト保護用テープ。   The photosensitive resist protective tape according to claim 1, wherein one or more ultraviolet absorbing layers are provided on one side or both sides of the base film 1 a. 前記紫外線吸収層は、前記基材フィルム１ａ上に紫外線吸収材を含有する樹脂の層を形成したこと、を特徴とする請求項４に記載の感光性レジスト保護用テープ。   The photosensitive resist protecting tape according to claim 4, wherein the ultraviolet absorbing layer is formed by forming a resin layer containing an ultraviolet absorbing material on the base film 1a. 前記紫外線吸収層は、単層か又は複数層の誘電体膜が前記基材フィルム１ａ上に形成されていること、を特徴とする請求項４に記載の感光性レジスト保護用テープ。   The photosensitive resist protecting tape according to claim 4, wherein the ultraviolet absorbing layer is a single layer or a plurality of layers of dielectric films formed on the base film 1a. 前記基材フィルム１ａと粘着層１ｂのうちいずれか一方か又は両方が、紫外線吸収材を含有しており、
且つ、該基材フィルム１ａの片面か又は両面に、１層以上の紫外線吸収層が設けてあること、を特徴とする請求項１又は２のいずれかに記載の感光性レジスト保護用テープ。 Either one or both of the base film 1a and the adhesive layer 1b contains an ultraviolet absorber,
The photosensitive resist protecting tape according to claim 1, wherein one or more ultraviolet absorbing layers are provided on one side or both sides of the base film 1 a. 請求項１乃至７のいずれかに記載の感光性レジスト保護用テープを前記粘着層１ｂを介して、作製途中の半導体パッケージ基板上の前記ソルダレジスト層の面に接触させ、所望するパターンに応じて選択的な露光を行うことにより該ソルダレジスト層のパターニングを行うこと、を特徴とする半導体パッケージ基板の製造方法。   The photosensitive resist protective tape according to claim 1 is brought into contact with the surface of the solder resist layer on the semiconductor package substrate in the process of production through the adhesive layer 1b, and according to a desired pattern. A method for producing a semiconductor package substrate, comprising patterning the solder resist layer by performing selective exposure. 請求項１乃至７のいずれかに記載の感光性レジスト保護用テープを用いて形成されるソルダレジスト層の複数有る開口の個々の開口径の個々の大きさの広がり方が、半導体チップと半導体パッケージ基板とが電気的に接続される接続端子部から該半導体チップの方に向かって、径が徐々に大きく広がっていること、を特徴とする半導体パッケージ基板。   8. A semiconductor chip and a semiconductor package according to claim 1, wherein each of the plurality of openings of the solder resist layer formed using the photosensitive resist protection tape according to claim 1 has a plurality of openings. A semiconductor package substrate, characterized in that a diameter gradually widens from a connection terminal portion electrically connected to the substrate toward the semiconductor chip.
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JP2016504614A (en) * 2013-06-18 2016-02-12 エルジー・ケム・リミテッド Multilayer optical film, method for producing the same, and polarizing plate including the same
US9804307B2 (en) 2013-06-18 2017-10-31 Lg Chem, Ltd. Multilayer optical film, method of producing the same and polarizer comprising the same

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