JP2010232793A - Resonance circuit, method of manufacturing the same, and electronic device - Google Patents

Resonance circuit, method of manufacturing the same, and electronic device Download PDF

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JP2010232793A
JP2010232793A JP2009075911A JP2009075911A JP2010232793A JP 2010232793 A JP2010232793 A JP 2010232793A JP 2009075911 A JP2009075911 A JP 2009075911A JP 2009075911 A JP2009075911 A JP 2009075911A JP 2010232793 A JP2010232793 A JP 2010232793A
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JP5375251B2 (en
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Toru Watanabe
徹 渡辺
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Seiko Epson Corp
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<P>PROBLEM TO BE SOLVED: To provide a resonance circuit that suppresses variation in resonance frequency due to variance in structural size of a vibrator, and to provide a method of manufacturing the resonance circuit. <P>SOLUTION: The resonance circuit 30 includes a substrate, a MEMS resonator 10 which includes a fixed electrode 12 formed on the substrate and a movable electrode 13 having a movable portion opposed to at least part of the fixed electrode, and a voltage application means 20 of applying a bias voltage to the MEMS resonator, and the voltage application means includes a voltage dividing circuit which includes a resistance R11 for compensation which is composed of the same layer with the movable portion and varies in resistance value with the thickness of the layer, and a reference resistance R12 which is connected to the resistance for compensation and composed of a layer different from the movable portion, and outputs the potential at the connection point between the resistance for compensation and reference resistance to at least one terminal 10b between a first terminal and a second terminal of the MEMS resonator. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は共振回路及びその製造方法並びに電子装置に係り、特に、MEMSレゾネータを用いた共振回路の構成及び製法に関する。   The present invention relates to a resonant circuit, a manufacturing method thereof, and an electronic device, and more particularly, to a configuration and a manufacturing method of a resonant circuit using a MEMS resonator.

最近の電子デバイス市場においては、MEMS(Micro Electro-Mechanical System)技術を用いた製品が加速的に浸透しつつある。MEMS技術を用いた製品とは、半導体製造技術を用いて基板上に形成された微小な構造体(MEMS構造体)を有する電気機械装置(MEMS装置)を言う。MEMS技術を用いたデバイスの具体的な事例としては、加速度センサ、角速度センサ、慣性センサ、圧力センサ等の各種のマイクロセンサ等が挙げられるが、その市場は近年急速に拡大しつつある。このように、MEMS技術は新たなデバイスの創出の可能性を多分に秘めており、今後は微小メカニカルリレー(スイッチ)や可変容量素子等の微小構造体の特徴を生かしたデバイスやそれらの組み合わせが順次実用化されていく見込みである。   In the recent electronic device market, products using MEMS (Micro Electro-Mechanical System) technology are accelerating. A product using MEMS technology refers to an electromechanical device (MEMS device) having a minute structure (MEMS structure) formed on a substrate using semiconductor manufacturing technology. Specific examples of devices using MEMS technology include various types of microsensors such as an acceleration sensor, an angular velocity sensor, an inertial sensor, and a pressure sensor, but the market has been rapidly expanding in recent years. In this way, MEMS technology has the potential to create new devices, and in the future, devices that take advantage of the features of microstructures such as micromechanical relays (switches) and variable capacitance elements, and combinations thereof, will be used. It is expected to be put to practical use one by one.

MEMS技術を用いた新しい応用例としてMEMSレゾネータを備えた共振回路が挙げられる。この種のMEMSレゾネータを備えた共振回路の動作原理としては、静電駆動・検出方式、圧電駆動・検出方式が代表的なものであるが、特に前者はCMOSプロセスのような半導体プロセスとの整合性がよく、小型化や低コスト化に有利な手法といえる。この静電駆動・検出方式は、可動電極と固定電極を有するMEMSレゾネータを形成し、静電力に起因する可動電極の振動を可動電極と固定電極の間の静電容量の変化によって検出するものである。共振回路の一般的な透過特性及び位相特性の例は図3(a)及び(b)に示されている。この種の共振回路を開示する文献としては、以下の特許文献1乃至3がある。   As a new application example using the MEMS technology, there is a resonance circuit including a MEMS resonator. As an operation principle of a resonance circuit provided with this type of MEMS resonator, an electrostatic drive / detection method and a piezoelectric drive / detection method are representative, but the former is particularly compatible with a semiconductor process such as a CMOS process. Therefore, it can be said to be an advantageous technique for downsizing and cost reduction. In this electrostatic drive / detection method, a MEMS resonator having a movable electrode and a fixed electrode is formed, and vibration of the movable electrode caused by electrostatic force is detected by a change in capacitance between the movable electrode and the fixed electrode. is there. Examples of typical transmission and phase characteristics of the resonant circuit are shown in FIGS. 3 (a) and 3 (b). As documents disclosing such a resonance circuit, there are the following patent documents 1 to 3.

米国特許第6249073号明細書US Pat. No. 6,249,073 米国特許第6424074号明細書US Pat. No. 6,424,074 特開2004−58228号公報JP 2004-58228 A

ところで、前述の共振回路においては、MEMSレゾネータの構造寸法がばらつくことで共振周波数が変動する。したがって、共振周波数の精度を確保するには、製造時における構造寸法のばらつきの低減が必要であり、当該ばらつきが低減できなければ製造後のトリミング工程等を設けることで周波数を補正する必要が生ずるなど、製造工程が複雑化し、製造コストが上昇する。   By the way, in the above-described resonance circuit, the resonance frequency varies due to variations in the structural dimensions of the MEMS resonator. Therefore, in order to ensure the accuracy of the resonance frequency, it is necessary to reduce the variation in the structural dimensions at the time of manufacturing. If the variation cannot be reduced, it is necessary to correct the frequency by providing a trimming step after the manufacturing. The manufacturing process becomes complicated and the manufacturing cost increases.

特に、MEMSレゾネータの構造寸法のうち、可動電極の可動部の厚みは共振周波数に直接に大きな影響を及ぼすとともに当該可動部の厚みは数um以下ときわめて薄いため、僅かなばらつきでも共振周波数を大きく変動させることになる。   In particular, among the structural dimensions of MEMS resonators, the thickness of the movable part of the movable electrode has a large effect directly on the resonance frequency and the thickness of the movable part is as thin as several um or less. Will change.

そこで、本発明は上記問題点を解決するものであり、振動子の構造寸法のばらつきに起因する共振周波数の変動を抑制することのできる共振回路及びその製造方法を実現することにある。   Accordingly, the present invention is to solve the above-described problems and to realize a resonance circuit and a method for manufacturing the same that can suppress fluctuations in the resonance frequency caused by variations in the structural dimensions of the vibrator.

斯かる実情に鑑み、本発明の共振回路は、基板と、該基板上に形成された固定電極、及び、該固定電極の少なくとも一部に対向する可動部を備えた可動電極を有するMEMSレゾネータと、該MEMSレゾネータにバイアス電圧を印加する電圧印加手段と、を具備し、前記電圧印加手段は、前記可動部と同じ層で構成され該層の厚みで抵抗値が変化する補償用抵抗と、該補償用抵抗に接続され前記可動部と異なる層で構成される基準抵抗とを備え、前記補償用抵抗と前記基準抵抗の接続点電位を前記MEMSレゾネータの第1の端子と第2の端子のうちの少なくとも一方の端子に出力する分圧回路を有することを特徴とする。   In view of such circumstances, the resonant circuit of the present invention includes a substrate, a fixed electrode formed on the substrate, and a MEMS resonator having a movable electrode provided with a movable portion facing at least a part of the fixed electrode. Voltage applying means for applying a bias voltage to the MEMS resonator, and the voltage applying means includes a compensation resistor that is formed of the same layer as the movable portion and has a resistance value that varies depending on the thickness of the layer. A reference resistor connected to a compensation resistor and composed of a layer different from that of the movable portion, and a potential at a connection point between the compensation resistor and the reference resistor is selected from a first terminal and a second terminal of the MEMS resonator. A voltage dividing circuit for outputting to at least one of the terminals.

本発明によれば、電圧印加手段が可動部と同じ層で構成される補償用抵抗を含み、可動部の層の厚みが変化すると、同じ層の厚みの変化により補償用抵抗の抵抗値が変化する。この補償用抵抗の抵抗値の変化は、分圧回路の出力電位を変化させ、これによってバイアス電圧が変動する。したがって、可動部の厚みの変化による共振周波数の変動分が補償用抵抗の厚みの変化によるバイアス電圧の変動により補償されるように構成すると、共振周波数の変動が自律的に抑制されるため、共振周波数精度の向上及び安定化を図ることができ、共振周波数の精度が許容範囲内となればトリミング工程などを省略することも可能になる。   According to the present invention, the voltage application means includes a compensation resistor composed of the same layer as the movable portion, and when the thickness of the movable portion layer changes, the resistance value of the compensation resistor changes due to the change in the thickness of the same layer. To do. This change in the resistance value of the compensation resistor changes the output potential of the voltage dividing circuit, thereby changing the bias voltage. Therefore, if the change in the resonance frequency due to the change in the thickness of the movable part is compensated by the change in the bias voltage due to the change in the thickness of the compensation resistor, the change in the resonance frequency is suppressed autonomously. The frequency accuracy can be improved and stabilized, and the trimming step can be omitted if the resonance frequency accuracy is within an allowable range.

本発明の一の態様においては、前記電圧印加手段は、前記接続点電位を前記MEMSレゾネータの前記第1の端子と前記第2の端子のうちの一方の端子に出力するとともに、前記MEMSレゾネータの他方の端子に他の電位を出力する。これによれば、電圧印加手段が接続点電位をMEMSレゾネータの一方の端子に出力するとともに他方の端子には他の電位を出力することで、MEMSレゾネータの両端子の電位が共に電圧印加手段によって与えられるので、任意のバイアス電圧を確実にMEMSレゾネータに印加する事が可能となる。   In one aspect of the present invention, the voltage applying means outputs the connection point potential to one of the first terminal and the second terminal of the MEMS resonator, and Another potential is output to the other terminal. According to this, the voltage applying means outputs the connection point potential to one terminal of the MEMS resonator and outputs the other potential to the other terminal, so that the potentials of both terminals of the MEMS resonator are both controlled by the voltage applying means. As a result, an arbitrary bias voltage can be reliably applied to the MEMS resonator.

この場合において、前記分圧回路では、前記補償用抵抗と前記基準抵抗とが高電位と低電位の間に直列に接続され、前記接続点電位が前記他の電位より高い場合には前記補償用抵抗側に前記高電位が接続されるとともに前記基準抵抗側に前記低電位が接続され、前記接続点電位が前記他の電位より低い場合には前記補償用抵抗側に前記低電位が接続されるとともに前記基準抵抗側に前記低電位が接続される。これによれば、前記接続点電位が前記他の電位より高い場合には分圧回路において補償用抵抗側に基準抵抗側よりも高い電位が供給されることにより、補償用抵抗の層の厚みと接続点電位とが負の相関を有するとき(すなわち、抵抗層が薄くなると抵抗値が高くなるとき)に接続点電位が低下するとバイアス電圧が低下するので共振周波数の変動が抑制されることとなる。また、上記とは逆に前記接続点電位が前記他の電位よりも低い場合には補償用抵抗側に基準抵抗側よりも低い電位が供給されることにより、補償用抵抗の層の厚みと接続点電位とが負の相関を有するとき(すなわち、抵抗層が薄くなると抵抗値が高くなるとき)に接続点電位が上昇するとバイアス電圧が低下するので共振周波数の変動が抑制されることとなる。したがって、いずれの場合でも前記補償用抵抗を層の厚みと負の相関を有する抵抗値を備えた抵抗層で構成できるため、通常の抵抗層、すなわち端縁部に一対の接続端子を有する抵抗層で補償用抵抗を構成することが可能になる。   In this case, in the voltage dividing circuit, the compensation resistor and the reference resistor are connected in series between a high potential and a low potential, and when the junction potential is higher than the other potential, the compensation resistor The high potential is connected to the resistance side and the low potential is connected to the reference resistance side. When the connection point potential is lower than the other potential, the low potential is connected to the compensation resistance side. At the same time, the low potential is connected to the reference resistance side. According to this, when the potential at the connection point is higher than the other potential, a potential higher than that at the reference resistance side is supplied to the compensation resistance side in the voltage dividing circuit. When the connection point potential has a negative correlation (that is, when the resistance value increases as the resistance layer becomes thinner), if the connection point potential decreases, the bias voltage decreases, so that fluctuations in the resonance frequency are suppressed. . Contrary to the above, when the potential at the connection point is lower than the other potential, a potential lower than that on the reference resistance side is supplied to the compensation resistance side, thereby connecting to the thickness of the compensation resistance layer. When the point potential has a negative correlation (that is, when the resistance value increases as the resistance layer becomes thinner), if the connection point potential increases, the bias voltage decreases, so that fluctuations in the resonance frequency are suppressed. Therefore, in any case, the compensation resistor can be constituted by a resistance layer having a resistance value having a negative correlation with the thickness of the layer, so that a normal resistance layer, that is, a resistance layer having a pair of connection terminals at the edge portion. This makes it possible to configure a compensation resistor.

本発明の他の態様においては、MEMSレゾネータの前記第1の端子と入力端子の間に接続された入力側結合容量と、前記第2の端子と出力端子の間に接続された出力側結合容量と、をさらに具備する。これによれば、MEMSレゾネータの第1の端子と共振回路の入力端子の間に入力側結合容量が接続されるとともに、MEMSレゾネータの第2の端子と共振回路の出力端子の間に出力側結合容量が接続されることで、MEMSレゾネータと外部回路との間が直流的に分離されるため、外部回路の電位によらず、MEMSレゾネータに所望のバイアス電圧を印加することができ、その結果、共振周波数の変動の抑制効果も高めることができる。   In another aspect of the present invention, an input-side coupling capacitor connected between the first terminal and the input terminal of the MEMS resonator, and an output-side coupling capacitor connected between the second terminal and the output terminal. And further comprising. According to this, the input side coupling capacitor is connected between the first terminal of the MEMS resonator and the input terminal of the resonance circuit, and the output side coupling is connected between the second terminal of the MEMS resonator and the output terminal of the resonance circuit. By connecting the capacitor, the MEMS resonator and the external circuit are separated in a direct current, so that a desired bias voltage can be applied to the MEMS resonator regardless of the potential of the external circuit. The effect of suppressing the fluctuation of the resonance frequency can also be enhanced.

また、本発明の別の共振回路は、基板と、該基板上に形成された固定電極、及び、該固定電極の少なくとも一部に対向する可動部を備えた可動電極を有するMEMSレゾネータと、前記MEMSレゾネータの第1の端子に第1の電位を供給する第1の回路と、第2の端子に第2の電位を供給する第2の回路とを有し、前記MEMSレゾネータに前記第1の電位と前記第2の電位の差に相当するバイアス電圧を印加する電圧印加手段と、を具備し、前記第1の回路と前記第2の回路のうち少なくとも一方は、前記可動部と同じ層で構成され該層の厚みで抵抗値が変化する補償用抵抗と、該補償用抵抗に接続され前記可動部と異なる層で構成される基準抵抗とを備え、前記補償用抵抗と前記基準抵抗の接続点電位を前記第1の電位若しくは前記第2の電位として出力する分圧回路であることを特徴とする。   Another resonant circuit of the present invention includes a substrate, a fixed electrode formed on the substrate, and a MEMS resonator having a movable electrode having a movable portion facing at least a part of the fixed electrode, A first circuit for supplying a first potential to a first terminal of the MEMS resonator; and a second circuit for supplying a second potential to a second terminal. The MEMS resonator includes the first circuit. Voltage applying means for applying a bias voltage corresponding to the difference between the potential and the second potential, and at least one of the first circuit and the second circuit is the same layer as the movable part. A compensation resistor having a resistance value that varies depending on the thickness of the layer; and a reference resistor that is connected to the compensation resistor and is composed of a layer different from the movable portion. The connection between the compensation resistor and the reference resistor The point potential is the first potential or the first potential. Characterized in that it is a dividing circuit for outputting a potential.

また、本発明の異なる態様においては、上記各発明において、前記可動部及び前記補償用抵抗が同一の材料で形成された導体層で構成され、前記基準抵抗は前記可動部及び前記補償用抵抗と異なる材料で形成された導体層で構成される。ここで、可動部と補償用抵抗はポリシリコン層で構成されることが好ましい。   Further, in a different aspect of the present invention, in each of the above-described inventions, the movable portion and the compensation resistor are configured by a conductor layer formed of the same material, and the reference resistance is the movable portion and the compensation resistor. Consists of conductor layers made of different materials. Here, it is preferable that the movable part and the compensation resistor are formed of a polysilicon layer.

さらに、本発明のさらに異なる態様においては、上記各発明において、前記可動部と前記補償用抵抗は隣接する導体層で構成される。この場合に、前記可動部と前記補償用抵抗が共通の収容空間に収容されていることが好ましい。この場合も、可動部と補償用抵抗はポリシリコン層で構成されることが望ましい。なお、本明細書において隣接する導体層とは、基板上において他の導体(他の導体層、配線層など)が間に介在しない態様で配置されていることを意味する。   Furthermore, in a further different aspect of the present invention, in each of the above-mentioned inventions, the movable part and the compensation resistor are constituted by adjacent conductor layers. In this case, it is preferable that the movable part and the compensation resistor are accommodated in a common accommodation space. Also in this case, it is desirable that the movable part and the compensation resistor are formed of a polysilicon layer. In the present specification, the adjacent conductor layers mean that other conductors (other conductor layers, wiring layers, etc.) are arranged on the substrate in a manner that they are not interposed therebetween.

次に、本発明の共振回路の製造方法は、固定電極及び該固定電極の少なくとも一部に対向する可動部を備えた可動電極を有するMEMSレゾネータと、該MEMSレゾネータにバイアス電圧を印加する電圧印加手段とを具備する共振回路の製造方法において、前記電圧印加手段は、補償用抵抗と基準抵抗とを備え、前記補償用抵抗と前記基準抵抗の接続点電位を前記MEMSレゾネータの少なくとも一方の端子に出力する分圧回路を有し、前記可動部を形成するとともに、前記可動部と同じ層で前記補償用抵抗を形成する工程と、前記可動部と異なる層で前記基準抵抗を形成する工程と、を具備することを特徴とする。ここで、可動部と補償用抵抗を形成する工程と、基準抵抗を形成する工程はいずれの工程を先に実施しても構わない。   Next, a method for manufacturing a resonant circuit according to the present invention includes a MEMS resonator having a fixed electrode and a movable electrode having a movable portion facing at least a part of the fixed electrode, and voltage application for applying a bias voltage to the MEMS resonator. The voltage applying means includes a compensation resistor and a reference resistor, and a connection point potential between the compensation resistor and the reference resistor is applied to at least one terminal of the MEMS resonator. A voltage dividing circuit for outputting, forming the movable part, forming the compensation resistor in the same layer as the movable part, and forming the reference resistance in a layer different from the movable part; It is characterized by comprising. Here, the step of forming the movable part and the compensation resistor and the step of forming the reference resistance may be performed first.

本発明の一の態様においては、前記可動部及び前記補償用抵抗は同一の材料で同一の方法で形成された導体層で構成され、前記基準抵抗は前記可動部及び前記補償用抵抗と異なる材料若しくは異なる方法で形成された導体層で構成される。ここで、可動部と補償用抵抗はポリシリコン層で構成されることが好ましい。   In one aspect of the present invention, the movable part and the compensation resistor are made of a conductive layer made of the same material and in the same method, and the reference resistance is a material different from the movable part and the compensation resistor. Or it is comprised with the conductor layer formed by the different method. Here, it is preferable that the movable part and the compensation resistor are formed of a polysilicon layer.

本発明の他の態様においては、前記可動部と前記補償用抵抗は隣接する導体層で構成される。これによれば、可動部と補償用抵抗が隣接することで、形成時の条件(例えば、成膜条件)に依存する膜厚値についても関連性を高めることができるので、共振周波数の補償効果を高めることができる。   In another aspect of the invention, the movable part and the compensation resistor are formed of adjacent conductor layers. According to this, since the movable portion and the compensation resistor are adjacent to each other, it is possible to increase the relevance with respect to the film thickness value depending on the formation conditions (for example, film formation conditions), so that the resonance frequency compensation effect Can be increased.

本発明の別の態様においては、前記可動部と前記補償用抵抗が共に収容される共通の収容空間を形成する工程をさらに有することが好ましい。これによれば、可動部と補償用抵抗とが収容空間内に共に配置されることで、補償用抵抗に周囲の素子による温度上昇が生ずることを防止できる。また、可動部に対するリリース工程時に補償用抵抗も同時に同じ条件でエッチング作用を受けるなど、可動部と補償用抵抗においてそれらの形成後に施される後処理の内容が同一となることから、後処理の相違による影響(構造寸法の変化等)を低減することができ、その結果、補償用抵抗による共振周波数の補償作用を高めることができる。この場合も、可動部と補償用抵抗はポリシリコン層で構成されることが望ましい。   In another aspect of the present invention, it is preferable that the method further includes a step of forming a common accommodation space in which the movable portion and the compensation resistor are accommodated together. According to this, since the movable part and the compensation resistor are arranged together in the accommodating space, it is possible to prevent the compensation resistor from being increased in temperature by surrounding elements. In addition, since the compensation resistance is subjected to the etching action under the same conditions at the same time during the release process for the movable part, the contents of the post-processing applied after the formation of the movable part and the compensation resistance are the same. The influence (change in structural dimensions, etc.) due to the difference can be reduced, and as a result, the resonance frequency compensation action by the compensation resistor can be enhanced. Also in this case, it is desirable that the movable part and the compensation resistor are formed of a polysilicon layer.

本発明の別の態様においては、前記可動部と前記補償用抵抗は同じ層上に形成される。これによれば、可動部と補償用抵抗とが同じ下地上に形成されることとなるので、可動部と補償用抵抗の形成(成膜)条件をさらに同等なものとすることができるため、膜厚の関連性をさらに高めることが可能であり、その結果、補償用抵抗による共振周波数の補償効果をさらに向上できる。   In another aspect of the present invention, the movable portion and the compensation resistor are formed on the same layer. According to this, since the movable part and the compensation resistor are formed on the same base, it is possible to make the formation (film formation) conditions of the movable part and the compensation resistor more equivalent. The relevance of the film thickness can be further increased, and as a result, the resonance frequency compensation effect by the compensation resistor can be further improved.

次に、本発明の電子装置は、上記のいずれかに記載の共振回路と、該共振回路に接続される信号回路部とが同一基板上に形成されてなることを特徴とする。これによれば、MEMSレゾネータ及び電圧印加手段を含む共振回路と信号回路部とを同一基板上に一体に構成できるため、コンパクトに構成できるとともに、特に、MEMSレゾネータ及び信号回路部といった複数の構成要素を並行して形成することにより同一工程で複数の構成要素を形成することが可能になるので、製造効率の向上や製造コストの低減を図ることができる。ここで、上記電子装置は、典型的には単一の半導体基板上に上記構成が一体に設けられた半導体装置(半導体チップ)として構成される。   Next, an electronic device according to the present invention is characterized in that any one of the resonance circuits described above and a signal circuit unit connected to the resonance circuit are formed on the same substrate. According to this, since the resonance circuit including the MEMS resonator and the voltage applying unit and the signal circuit unit can be integrally formed on the same substrate, it can be configured compactly, and in particular, a plurality of components such as the MEMS resonator and the signal circuit unit. By forming them in parallel, it becomes possible to form a plurality of components in the same process, so that it is possible to improve manufacturing efficiency and reduce manufacturing costs. Here, the electronic device is typically configured as a semiconductor device (semiconductor chip) in which the above configuration is integrally provided on a single semiconductor substrate.

なお、このような電子装置の例としては、上記信号回路部として負性抵抗を有する増幅回路を用いて発振回路を構成する場合が挙げられる。また、上記基板としては、シリコン基板等の半導体基板、ガラス基板、セラミックス基板などが挙げられるが、振動子としてMEMSレゾネータを構成する場合には、シリコン基板等の半導体基板を用いた半導体装置を構成することが好ましい。   As an example of such an electronic device, there is a case where an oscillation circuit is configured using an amplifier circuit having a negative resistance as the signal circuit portion. Examples of the substrate include a semiconductor substrate such as a silicon substrate, a glass substrate, and a ceramic substrate. When a MEMS resonator is configured as a vibrator, a semiconductor device using a semiconductor substrate such as a silicon substrate is configured. It is preferable to do.

本発明によれば、可動部の構造寸法のばらつきに起因する振動子の共振周波数の変動を抑制し、共振回路の周波数特性の精度の向上を図ることができるという優れた効果を奏し得る。   According to the present invention, it is possible to achieve an excellent effect that the fluctuation of the resonance frequency of the vibrator due to the variation in the structural dimensions of the movable part can be suppressed and the accuracy of the frequency characteristics of the resonance circuit can be improved.

本発明に係る共振回路の振動子の構成例を示す概略斜視図。The schematic perspective view which shows the structural example of the vibrator | oscillator of the resonance circuit which concerns on this invention. 同振動子の縦断面図(a)及び(b)。The longitudinal cross-sectional view (a) and (b) of the vibrator | oscillator. 振動子の通過特性及び位相変位の周波数依存性を示すグラフ(a)及び(b)。Graphs (a) and (b) showing the pass characteristics of the vibrator and the frequency dependence of the phase displacement. 振動子の通過特性のバイアス電圧依存性を示すグラフ。The graph which shows the bias voltage dependence of the passage characteristic of a vibrator. 共振回路の第1実施形態の構成を示す回路図。The circuit diagram which shows the structure of 1st Embodiment of a resonance circuit. 共振回路の第2実施形態の構成を示す回路図。The circuit diagram which shows the structure of 2nd Embodiment of a resonance circuit. 共振回路の振動子と補償用抵抗要素の構造寸法の関係を模式的に示す構成図。The block diagram which shows typically the relationship of the structural dimension of the vibrator | oscillator of a resonance circuit, and the resistance element for compensation. 共振回路の構成要素のより具体的な配置例を示す概略斜視図(a)及び(b)。The schematic perspective view (a) and (b) which shows the more concrete example of arrangement | positioning of the component of a resonance circuit. 共振回路の構成要素のより具体的な他の配置例を示す概略平面図。The schematic plan view which shows the more specific other example of arrangement | positioning of the component of a resonance circuit. 共振回路を含む電子装置の構成例を示す回路図。FIG. 6 is a circuit diagram illustrating a configuration example of an electronic device including a resonance circuit. 基準抵抗要素の構成例を示す部分平面図(a)及び部分断面図(b)。The fragmentary top view (a) and fragmentary sectional view (b) which show the example of composition of a standard resistance element. 基準抵抗要素の他の構成例を示す回路図(a)乃至(c)。Circuit diagrams (a) to (c) showing other configuration examples of the reference resistance element. 共振回路の製造方法を示す概略工程断面図(a)乃至(h)。Schematic process sectional drawing (a) thru | or (h) which show the manufacturing method of a resonant circuit. 共振回路の製造方法の他の例を示す概略工程断面図(a)乃至(h)。Schematic process sectional drawing (a) thru | or (h) which show the other example of the manufacturing method of a resonance circuit.

次に、添付図面を参照して本発明の実施形態について詳細に説明する。図1は本実施形態の共振回路に用いることのできるMEMSレゾネータ10の構成例を示す概略斜視図、図2は図1のA−A線及びB−B線に沿った断面を示す同振動子10の断面図(a)及び(b)である。   Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a schematic perspective view showing a configuration example of a MEMS resonator 10 that can be used in the resonance circuit of the present embodiment, and FIG. 2 is the same vibrator showing cross sections taken along lines AA and BB in FIG. 10 is a cross-sectional view (a) and (b) of FIG.

MEMSレゾネータ10は、シリコン単結晶等の半導体よりなる基板1上に構成される。基板1上には酸化シリコン(SiO)等の絶縁膜2が形成され、さらに絶縁膜2上には窒化シリコン等の振動子10の下地層11が形成される。下地層11上には、ドーピングにより導電性が付与された多結晶シリコン等よりなる固定電極12と、同様の材質よりなる可動電極13とが形成される。ここで、振動子10の振動子電極を構成する固定電極12の一部と可動電極13の可動部13aは基板1上において適宜の間隔(数um以下)で相互に上下方向に対向配置される。そして、可動部13aは固定電極12との間に生ずる静電引力に応じて上下に撓み、固定電極12との間の対向間隔を変化させる方向に可動に構成される。 The MEMS resonator 10 is configured on a substrate 1 made of a semiconductor such as a silicon single crystal. An insulating film 2 such as silicon oxide (SiO 2 ) is formed on the substrate 1, and a base layer 11 of the vibrator 10 such as silicon nitride is further formed on the insulating film 2. On the base layer 11, a fixed electrode 12 made of polycrystalline silicon or the like imparted with conductivity by doping and a movable electrode 13 made of the same material are formed. Here, a part of the fixed electrode 12 constituting the vibrator electrode of the vibrator 10 and the movable portion 13a of the movable electrode 13 are arranged on the substrate 1 so as to face each other in the vertical direction at an appropriate interval (several um or less). . The movable portion 13a is configured to bend in the vertical direction according to the electrostatic attractive force generated between the movable electrode 13a and the movable electrode 13a so as to be movable in the direction in which the distance between the movable electrode 13a and the fixed electrode 12 is changed.

なお、図示のMEMSレゾネータ10は可動電極13が片持ち梁状に構成されることにより可動部13aとされた片持ち梁構造を有するが、これは本発明の振動子の一例に過ぎず、本発明においては、MEMSレゾネータの可動部が両持ち梁状に構成されたもの、円盤状に構成されたものなど、種々の形状、構造を採用したものを用いることが可能である。   Although the illustrated MEMS resonator 10 has a cantilever structure in which the movable electrode 13 is formed in a cantilever shape to form a movable portion 13a, this is merely an example of the vibrator of the present invention. In the invention, it is possible to use a MEMS resonator adopting various shapes and structures, such as a movable part of the MEMS resonator formed in a doubly-supported beam shape or a disk-shaped movable part.

図3は本発明に係る共振回路の上記MEMSレゾネータ10の電気的特性を示す概略特性図である。ここで、図3(a)はMEMSレゾネータ10に交流信号を入力したときの通過特性を示すグラフ、図3(b)は位相変位を示すグラフである。このように、MEMSレゾネータ10は適宜の共振周波数を有する共振特性を備えているが、この共振周波数fは、以下の式(1)で示される。
=(1/2π)・(k/meff1/2・・・(1)
ここで、kはMEMSレゾネータ10の構造から決定されるばね定数、meffは同構造の有効質量である。
FIG. 3 is a schematic characteristic diagram showing the electrical characteristics of the MEMS resonator 10 of the resonance circuit according to the present invention. Here, FIG. 3A is a graph showing pass characteristics when an AC signal is input to the MEMS resonator 10, and FIG. 3B is a graph showing phase displacement. As described above, the MEMS resonator 10 has a resonance characteristic having an appropriate resonance frequency. The resonance frequency f n is expressed by the following equation (1).
f n = (1 / 2π) · (k m / m eff) 1/2 ··· (1)
Here, k m is the spring constant determined from the structure of the MEMS resonator 10, m eff is the effective mass of the structure.

一方、MEMSレゾネータ10の固定電極12と可動電極13の間に適宜のバイアス電圧(直流バイアス)を印加すると両電極の間に静電引力が発生し、上記ばね定数kを減少させる様に作用する。このため、上記式(1)により共振周波数fが低下する。そして、一般に、バイアス電圧が増加するほど共振周波数fは減少することになる。 On the other hand, electrostatic attraction between the application appropriate bias voltage (DC bias) both electrodes between the fixed electrode 12 and movable electrode 13 is generated in the MEMS resonator 10, it acts as to reduce the spring constant k m To do. For this reason, the resonance frequency f n is reduced by the above equation (1). In general, the resonance frequency f n decreases as the bias voltage increases.

図4は、MEMSレゾネータ10に印加したバイアス電圧Vbを変化させたときの交流信号の共振特性を示すグラフである。このように、バイアス電圧Vbが増加するほど共振周波数fは低下する。 FIG. 4 is a graph showing the resonance characteristics of the AC signal when the bias voltage Vb applied to the MEMS resonator 10 is changed. Thus, the resonance frequency f n decreases as the bias voltage Vb increases.

図5は、第1実施形態に用いられるMEMSレゾネータ10を含む共振回路30の構成を示す回路図である。この例では、共振回路30の入力端子30aと出力端子30bがMEMSレゾネータ10の第1の端子10aと第2の端子10b(いずれか一方が上記固定電極12に接続された側の端子で、いずれか他方が上記可動電極13に接続された側の端子)に接続されるとともに、MEMSレゾネータ10の第1の端子(入力側の端子)10aと入力端子30aとの間、並びに、第2の端子(出力側の端子)10bと出力端子30bとの間には電圧印加手段であるバイアス回路20が接続されている。また、入力端子30aと第1の端子10aとの間には入力側結合容量Caが接続され、出力端子30bと第2の端子10bとの間には出力側結合容量Cbが接続される。   FIG. 5 is a circuit diagram showing a configuration of the resonance circuit 30 including the MEMS resonator 10 used in the first embodiment. In this example, the input terminal 30 a and the output terminal 30 b of the resonance circuit 30 are the first terminal 10 a and the second terminal 10 b of the MEMS resonator 10 (one of which is connected to the fixed electrode 12, whichever The other terminal is connected to the movable electrode 13 side terminal), the first terminal (input side terminal) 10a of the MEMS resonator 10 and the input terminal 30a, and the second terminal A bias circuit 20 serving as a voltage application unit is connected between the (output side terminal) 10b and the output terminal 30b. An input side coupling capacitor Ca is connected between the input terminal 30a and the first terminal 10a, and an output side coupling capacitor Cb is connected between the output terminal 30b and the second terminal 10b.

バイアス回路20は、MEMSレゾネータ10の両端子10aと10bに直流バイアス電圧を印加するための構成部分である。バイアス回路20は、補償用抵抗R11と、基準抵抗R12とが直列に接続されてなり、両抵抗の直列回路の両端に電圧が印加される分圧回路21を有する。図示例の場合、分圧回路21では、補償用抵抗R11側に高電位である直流電源電位Vdcが供給され、基準抵抗R12側が低電位である接地電位に接続されている。そして、補償用抵抗R11と基準抵抗R12の接続点電位VpがMEMSレゾネータ10の出力側の第2の端子10bに与えられる。この接続点電位Vpは、分圧回路21の両端の電位差圧Vdcと分圧比Dv=R12/(R11+R12)に応じた第2の電位Vp=Dv・Vdcとなる。   The bias circuit 20 is a component for applying a DC bias voltage to both terminals 10 a and 10 b of the MEMS resonator 10. The bias circuit 20 includes a voltage dividing circuit 21 in which a compensation resistor R11 and a reference resistor R12 are connected in series, and a voltage is applied to both ends of the series circuit of both resistors. In the case of the illustrated example, in the voltage dividing circuit 21, the DC power supply potential Vdc that is a high potential is supplied to the compensation resistor R11 side, and the reference resistor R12 side is connected to a ground potential that is a low potential. The connection point potential Vp between the compensation resistor R11 and the reference resistor R12 is applied to the second terminal 10b on the output side of the MEMS resonator 10. This connection point potential Vp becomes the second potential Vp = Dv · Vdc corresponding to the potential difference pressure Vdc at both ends of the voltage dividing circuit 21 and the voltage dividing ratio Dv = R12 / (R11 + R12).

一方、バイアス回路20には、MEMSレゾネータ10の入力側の第1の端子10aに接続された電位供給部22が設けられ、この電位供給部22は抵抗R13を介して定電位(図示例では接地電位)に接続され、MEMSレゾネータ10の入力側端子10aに第1の電位Vqを与える。ここで、本実施形態では第2の電位である接続点電位Vpは常に第1の電位Vqより高くなるように構成される。このようにして、MEMSレゾネータ10には、上記バイアス回路20の分圧回路21が供給する第2の電位Vpと、電位供給部22が供給する第1の電位Vqとの差に相当するバイアス電圧Vb=Vp−Vqが印加される。なお、この共振回路30は入力端子30aと出力端子30bが外部回路に接続されて用いられるが、外部回路とMEMSレゾネータ10は入力側結合容量Ca及び出力側結合容量Cbにより直流的に分離されるので、MEMSレゾネータ10にはバイアス回路20による上記バイアス電圧Vbのみが直流バイアスとして印加される。   On the other hand, the bias circuit 20 is provided with a potential supply unit 22 connected to the first terminal 10a on the input side of the MEMS resonator 10, and the potential supply unit 22 is connected to a constant potential (grounded in the illustrated example) via a resistor R13. The first potential Vq is applied to the input terminal 10a of the MEMS resonator 10. Here, in the present embodiment, the connection potential Vp which is the second potential is configured to be always higher than the first potential Vq. In this manner, the MEMS resonator 10 has a bias voltage corresponding to the difference between the second potential Vp supplied by the voltage dividing circuit 21 of the bias circuit 20 and the first potential Vq supplied by the potential supply unit 22. Vb = Vp−Vq is applied. The resonance circuit 30 is used with an input terminal 30a and an output terminal 30b connected to an external circuit. However, the external circuit and the MEMS resonator 10 are DC-isolated by an input side coupling capacitor Ca and an output side coupling capacitor Cb. Therefore, only the bias voltage Vb from the bias circuit 20 is applied to the MEMS resonator 10 as a DC bias.

なお、この第1実施形態では、MEMSレゾネータ10の出力側の第2の端子10bに分圧回路21による第2の電位Vpが供給され、入力側の第1の端子10aに他の第1の電位Vqが電位供給部22により供給されるが、これとは逆に、入力側の第1の端子10aに分圧回路21による電位Vpが第1の電位として供給され、出力側の第2の端子10bに他の電位Vqが第2の電位として供給されるように構成してもよい。また、バイアス回路20がMEMSレゾネータ10のいずれか一方の端子に電位Vpを供給する分圧回路21のみで構成されていてもよい。さらに、上記例では電位Vqが分圧回路21により供給される電位Vpより低い場合について説明したが、例えば、電位Vqを高電位に抵抗R13を介して接続する構成とすることで、分圧回路21により供給される電位Vpより高い構成としてもよい。   In the first embodiment, the second potential Vp from the voltage dividing circuit 21 is supplied to the second terminal 10b on the output side of the MEMS resonator 10, and the other first voltage is supplied to the first terminal 10a on the input side. The potential Vq is supplied by the potential supply unit 22, but conversely, the potential Vp from the voltage dividing circuit 21 is supplied to the first terminal 10a on the input side as the first potential, and the second potential on the output side is supplied. Another potential Vq may be supplied to the terminal 10b as the second potential. In addition, the bias circuit 20 may be configured by only the voltage dividing circuit 21 that supplies the potential Vp to any one terminal of the MEMS resonator 10. Furthermore, although the case where the potential Vq is lower than the potential Vp supplied by the voltage dividing circuit 21 has been described in the above example, for example, the voltage dividing circuit can be configured by connecting the potential Vq to a high potential via the resistor R13. 21 may be higher than the potential Vp supplied by the power supply 21.

図6は、第2実施形態の共振回路30′の構成を示す回路図である。この例では、MEMSレゾネータ10の両端に共に分圧回路による電位Vp、Vqを供給するバイアス回路20′が設けられる点で第1実施形態と異なるが、他の構成は全て同一であるので、説明を省略する。   FIG. 6 is a circuit diagram showing a configuration of a resonance circuit 30 ′ of the second embodiment. This example is different from the first embodiment in that a bias circuit 20 ′ for supplying potentials Vp and Vq by a voltage dividing circuit is provided at both ends of the MEMS resonator 10, but all other configurations are the same. Is omitted.

ここで、MEMSレゾネータ10の出力側の第2の端子10bには第1実施形態と同様の補償用抵抗R11及び基準抵抗R12を備えた分圧回路21が接続される。ここで、この分圧回路21では、補償用抵抗R11側が高電位のVdc1に接続され、基準抵抗R12側が低電位の接地電位に接続される。   Here, a voltage dividing circuit 21 having a compensation resistor R11 and a reference resistor R12 similar to those in the first embodiment is connected to the second terminal 10b on the output side of the MEMS resonator 10. Here, in the voltage dividing circuit 21, the compensation resistor R11 side is connected to the high potential Vdc1, and the reference resistor R12 side is connected to the low potential ground potential.

また、MEMSレゾネータ10の入力側の第1の端子10aには基準抵抗R14及び補償用抵抗R15を備えた分圧回路22′が接続される。この分圧回路22′は、基準抵抗R14側が高電位のVdc2に接続され、補償用抵抗R15側が低電位の接地電位に接続される。   A voltage dividing circuit 22 ′ having a reference resistor R 14 and a compensating resistor R 15 is connected to the first terminal 10 a on the input side of the MEMS resonator 10. In the voltage dividing circuit 22 ', the reference resistor R14 side is connected to the high potential Vdc2, and the compensation resistor R15 side is connected to the low potential ground potential.

この場合には、MEMSレゾネータ10の入力側の第1の端子10aに基準抵抗R14及び補償用抵抗R15を備えた分圧回路22′の接続点電位Vqが第1の電位として供給され、出力側の第2の端子10bに補償用抵抗R11及び基準抵抗R12を備えた分圧回路21の接続点電位Vpが第2の電位として供給されるので、MEMSレゾネータ10のバイアス電圧は上記と同様にVb=Vp−Vqとなる。なお、この実施形態でも接続点電位Vpは常に接続点電位Vqより高い電位とされる。   In this case, the connection point potential Vq of the voltage dividing circuit 22 ′ having the reference resistor R14 and the compensation resistor R15 is supplied to the first terminal 10a on the input side of the MEMS resonator 10 as the first potential, and the output side Since the connection point potential Vp of the voltage dividing circuit 21 including the compensation resistor R11 and the reference resistor R12 is supplied to the second terminal 10b as the second potential, the bias voltage of the MEMS resonator 10 is Vb as described above. = Vp-Vq. In this embodiment, the connection point potential Vp is always higher than the connection point potential Vq.

上記の各実施形態において、補償用抵抗R11は、上記振動子10の可動部13aと同一の層で構成される。例えば、可動部13aと補償用抵抗R11は、共通の導電層を成膜し、この導電層を一括してパターニングすることによって同時に構成される。   In each of the embodiments described above, the compensation resistor R11 is formed of the same layer as the movable portion 13a of the vibrator 10. For example, the movable portion 13a and the compensation resistor R11 are configured simultaneously by forming a common conductive layer and patterning the conductive layer in a lump.

図7は、MEMSレゾネータ10と補償用抵抗R11の構成を模式的に(すなわち、実際の配置とは無関係に隣接配置した状態で)示す図である。MEMSレゾネータ10は上述のように固定電極12と可動電極13を有するが、可動電極13は、固定電極12の固定電極12と対向する可動部13aを有し、この可動部13aの厚みHと、可動部13aの張り出し方向(図示左右方向)の長さ(梁長さ)Lo(固定電極12と重なる範囲において張り出し方向に延在する長さ)とによってMEMSレゾネータ10の共振周波数fnが以下の式(1′)のように算出できることが知られている。
fn=(1/2π)・(35E/33ρ)1/2・H/Lo・・・(1′)
ここで、Eは可動部13aを構成する素材のヤング率、ρは同素材の密度である。したがって、上記式(1′)により、可動部13aの厚みHが増加すると共振周波数fnが増加し、可動部13aが薄くなると共振周波数fnが低下すること、すなわち、厚みHと共振周波数fnとが正の相関を有することがわかる。
FIG. 7 is a diagram schematically showing the configuration of the MEMS resonator 10 and the compensation resistor R11 (that is, in a state in which the MEMS resonator 10 and the compensating resistor R11 are adjacently arranged irrespective of the actual arrangement). The MEMS resonator 10 has the fixed electrode 12 and the movable electrode 13 as described above, but the movable electrode 13 has a movable portion 13a facing the fixed electrode 12 of the fixed electrode 12, and a thickness H of the movable portion 13a, The resonance frequency fn of the MEMS resonator 10 is expressed by the following equation depending on the length (beam length) Lo (length extending in the extending direction in the range overlapping the fixed electrode 12) in the extending direction (left-right direction in the drawing) of the movable portion 13a. It is known that it can be calculated as (1 ').
fn = (1 / 2π) · (35E / 33ρ) 1/2 · H / Lo 2 (1 ′)
Here, E is the Young's modulus of the material constituting the movable portion 13a, and ρ is the density of the material. Therefore, according to the above equation (1 ′), when the thickness H of the movable portion 13a is increased, the resonance frequency fn is increased, and when the movable portion 13a is thinned, the resonance frequency fn is decreased. It can be seen that there is a positive correlation.

一方、補償用抵抗R11の抵抗値は、平面方向の両端部近傍(図示左右の端部近傍)を接続点として用いる場合を考えると、両端部間の長さLr、当該長さ方向と直交する図示しない幅Wr、厚みは可動部13aと同じHであるから、以下の式(2)によって与えられる。
R11=ρr・Lr/(Wr・H)・・・(2)
ここで、ρrは素材の抵抗率である。したがって、この式(2)により、補償用抵抗R11の抵抗層の厚みHが増加すると抵抗値は減少し、厚みHが減少すると抵抗値は増加すること、すなわち、厚みHと補償用抵抗R11の抵抗値とが負の相関を有することがわかる。
On the other hand, the resistance value of the compensation resistor R11 is orthogonal to the length Lr between both ends when considering the vicinity of both ends in the plane direction (near the left and right ends in the figure) as a connection point. Since the width Wr and the thickness (not shown) are the same as those of the movable portion 13a, they are given by the following expression (2).
R11 = ρr · Lr / (Wr · H) (2)
Here, ρr is the resistivity of the material. Therefore, according to this equation (2), the resistance value decreases as the resistance layer thickness H of the compensation resistor R11 increases, and the resistance value increases as the thickness H decreases, that is, the thickness H and the compensation resistor R11. It can be seen that the resistance value has a negative correlation.

一方、基準抵抗R12は可動部13aとは異なる構造、例えば、別の工程で形成される異なる層で構成されるか、或いは、外付けの抵抗で構成される。したがって、補償用抵抗R11が可動部13aと層の厚みHに関して共通し、これによって可動部13aの厚みHのばらつきと連動して補償用抵抗R11の厚みHがばらつくのに対して、基準抵抗12は可動部13aの厚みHのばらつきとは必ずしも連関しない。なお、上記の説明では、可動部13aの厚みと補償用抵抗R11の厚みとが同一であるとしたが、両者が同じ層で構成されていれば製造時における厚みのばらつきによる厚みの増減が連動していることから、両者の厚みが必ずしも一致している必要はない。   On the other hand, the reference resistor R12 has a structure different from that of the movable portion 13a, for example, a different layer formed in a separate process, or an external resistor. Accordingly, the compensation resistor R11 is common to the movable portion 13a with respect to the layer thickness H, and thereby the thickness H of the compensation resistor R11 varies in conjunction with the variation in the thickness H of the movable portion 13a. Does not necessarily relate to variations in the thickness H of the movable portion 13a. In the above description, the thickness of the movable portion 13a and the thickness of the compensation resistor R11 are the same. However, if both are formed of the same layer, the thickness increase / decrease due to the thickness variation at the time of manufacture is linked. Therefore, the thicknesses of the two do not necessarily match.

そして、上記のバイアス回路部20、20′はいずれも層の厚みHが所定量だけ増大したときにR11の抵抗値が下がるために、供給電位Vpが上昇するように構成される。具体的には、補償用抵抗R11が低下すると、基準抵抗R12が同様に低下しない限り、分圧比Dvが増加するために接続点電位Vpが高電位側に移動する。このように、本実施形態では、層の厚みHとバイアス電圧Vb=Vp―Vqが正の相関を有するため、上記式(1′)と図4に示す特性により、可動部13aの厚みHの変化(例えば所定量の増加)に起因して共振周波数fnが変動しようとすると、同じ厚みHの変化に起因する補償用抵抗R11の抵抗値の変化がバイアス電圧の変化を招いてこれを抑制し、全体として可動部13aの厚みのばらつきによる共振周波数の変動が低減される。   The bias circuit sections 20 and 20 'are both configured to increase the supply potential Vp because the resistance value of R11 decreases when the layer thickness H increases by a predetermined amount. Specifically, when the compensation resistor R11 is lowered, unless the reference resistor R12 is similarly lowered, the voltage dividing ratio Dv is increased, so that the connection point potential Vp moves to the high potential side. As described above, in this embodiment, since the layer thickness H and the bias voltage Vb = Vp−Vq have a positive correlation, the thickness H of the movable portion 13a is determined by the above-described equation (1 ′) and the characteristics shown in FIG. When the resonance frequency fn is about to change due to a change (for example, an increase of a predetermined amount), a change in the resistance value of the compensation resistor R11 caused by the same change in the thickness H causes a change in the bias voltage and suppresses this. As a whole, fluctuations in the resonance frequency due to variations in the thickness of the movable portion 13a are reduced.

なお、上記事項は第1実施形態と第2実施形態のいずれの実施形態でも共通である。ただし、第2実施形態においては、補償用抵抗R15を補償用抵抗R11と同様に可動部13aと同じ層で構成することで、厚みHが増加すると補償用抵抗R15の抵抗値が低下して分圧回路22′の接続点電位Vqが低下するので、上記と同様にバイアス電圧Vb=Vp−Vq(Vp>Vq)を増加させる方向に作用する。したがって、この分圧回路22′も可動部13aの厚みHの変化に起因する共振周波数fnの変動を抑制する働きを示す。   The above items are common to both the first embodiment and the second embodiment. However, in the second embodiment, the compensation resistor R15 is formed of the same layer as the movable portion 13a in the same manner as the compensation resistor R11, so that the resistance value of the compensation resistor R15 decreases as the thickness H increases. Since the connection point potential Vq of the voltage circuit 22 'decreases, the bias voltage Vb = Vp-Vq (Vp> Vq) is increased in the same manner as described above. Therefore, the voltage dividing circuit 22 'also functions to suppress fluctuations in the resonance frequency fn caused by the change in the thickness H of the movable portion 13a.

したがって、第2実施形態では、抵抗R15を抵抗R11と同様に可動部13aと同じ層で構成する補償用抵抗とすることで第2の電位Vpと第1の電位Vqが共に変化する結果、厚みHの変化によるバイアス電圧Vpの変化率を高めることを可能にしている。もっとも、図示例において、抵抗R11のみ補償用抵抗としてもよく、或いは、抵抗R15のみを補償用抵抗としてもよい。抵抗R11が補償用抵抗で、抵抗R15が補償用抵抗でなければ、第1実施形態と同等に第1の電位Vqは他の定電位に接続されることで与えられる構成となる。   Therefore, in the second embodiment, the resistance R15 is a compensation resistance configured by the same layer as the movable portion 13a in the same manner as the resistance R11. As a result, both the second potential Vp and the first potential Vq change. It is possible to increase the rate of change of the bias voltage Vp due to the change of H. However, in the illustrated example, only the resistor R11 may be a compensation resistor, or only the resistor R15 may be a compensation resistor. If the resistor R11 is not a compensation resistor and the resistor R15 is not a compensation resistor, the first potential Vq is given by being connected to another constant potential as in the first embodiment.

なお、以上の説明は、電位Vpが電位Vqより高いことを前提にして行ったが、上記とは逆に、電位Vpが電位Vqより低い場合も考えられる。例えば、図5に示す構成では、上述のように電位Vqを高電位に抵抗R13を介して接続する構成とすることで、分圧回路21により供給される電位Vpより高い構成とすることができる。このように電位Vpが電位Vqよりも低い場合には、電位Vpを出力する分圧回路内の電位の高低及び増減とバイアス電圧の増減に関する記述は電位の高低及び電位の上昇と低下をそれぞれ逆に言い換えることで妥当する。   Note that the above description is made on the assumption that the potential Vp is higher than the potential Vq, but conversely, the case where the potential Vp is lower than the potential Vq is also conceivable. For example, in the configuration shown in FIG. 5, the potential Vq is connected to the high potential via the resistor R13 as described above, so that the configuration can be higher than the potential Vp supplied by the voltage dividing circuit 21. . As described above, when the potential Vp is lower than the potential Vq, the description about the level of the potential in the voltage dividing circuit that outputs the potential Vp and the increase / decrease of the bias voltage and the increase / decrease of the potential are reversed. In other words, it is appropriate.

また、上記と同様に、本実施形態の第2の電位Vpが第1の電位Vqより高い電位である関係を、第2の電位Vpが第1の電位Vqよりも低い電位であるように変更する場合には、分割回路21の補償用抵抗R11と基準抵抗R12の接続位置を置換すればよく、また、第2実施形態では分圧回路22′の基準抵抗R14と補償用抵抗R15の接続位置を置換すればよい。   Similarly to the above, the relationship in which the second potential Vp of this embodiment is higher than the first potential Vq is changed so that the second potential Vp is lower than the first potential Vq. In this case, the connection position between the compensation resistor R11 and the reference resistor R12 in the dividing circuit 21 may be replaced. In the second embodiment, the connection position between the reference resistor R14 and the compensation resistor R15 in the voltage dividing circuit 22 '. Should be replaced.

なお、上記各実施形態では、分圧回路21に含まれる補償用抵抗R11を層の厚みと負の相関を有する抵抗値を備える抵抗層で構成したが、たとえば、抵抗層の表裏両面に電極を接続し、層の厚みと正の相関を有する抵抗値を備える抵抗層で構成してもよい。この場合には、分割回路21において補償用抵抗R11と基準抵抗R12の接続位置を置換し、補償用抵抗R11を低電位側に接続すればよい。同様に、第2実施形態の分圧回路22′においては補償用抵抗R15を上記と同様に層の厚みと正の相関を備える抵抗値を有する抵抗層とする場合には、補償用抵抗R15を高電位側に、基準抵抗R14を低電位側に接続すればよい。   In each of the above embodiments, the compensation resistor R11 included in the voltage dividing circuit 21 is configured by a resistance layer having a resistance value having a negative correlation with the thickness of the layer. For example, electrodes are provided on both the front and back surfaces of the resistance layer. You may comprise by the resistance layer provided with the resistance value which connects and has a positive correlation with the thickness of a layer. In this case, it is only necessary to replace the connection position of the compensation resistor R11 and the reference resistor R12 in the dividing circuit 21 and connect the compensation resistor R11 to the low potential side. Similarly, in the voltage dividing circuit 22 ′ of the second embodiment, when the compensation resistor R15 is a resistance layer having a resistance value having a positive correlation with the layer thickness as described above, the compensation resistor R15 is The reference resistor R14 may be connected to the low potential side on the high potential side.

図8(a)は、上記第1実施形態の構成を模式的に示す概略斜視図である。なお、この図8においては回路要素間の結線関係については線で模式的に描いてある。この図においては、基板及びその上に形成される絶縁膜、下地層、層間絶縁膜等を省略してある。図示例では、基板上に形成した第1導電層により固定電極12を形成し、その後、固定電極12上に図示しない絶縁膜(犠牲層となるもの)を形成してから、第2導電層により可動電極13及び補償用抵抗R11を形成する。ここで、可動電極13の可動部13aと補償用抵抗R11の抵抗層は第2導電層の形成及びそのパターニングによって一括して形成される。   FIG. 8A is a schematic perspective view schematically showing the configuration of the first embodiment. In FIG. 8, the connection relationship between circuit elements is schematically drawn with lines. In this figure, the substrate and the insulating film, base layer, interlayer insulating film and the like formed thereon are omitted. In the illustrated example, the fixed electrode 12 is formed by the first conductive layer formed on the substrate, and then an insulating film (not shown) (not shown) is formed on the fixed electrode 12, and then the second conductive layer is used. The movable electrode 13 and the compensation resistor R11 are formed. Here, the movable portion 13a of the movable electrode 13 and the resistance layer of the compensation resistor R11 are collectively formed by forming the second conductive layer and patterning it.

また、基準抵抗R12を構成する抵抗層は、可動部13aの形成工程とは異なる工程で形成される。たとえば、第1導電層の形成及びそのパターニングによって固定電極12と一括して形成できる。もっとも、補償用抵抗11の形成工程と基準抵抗R12の形成工程とが異なる工程であるものの、同種の材料や成膜方法を採用した工程である点で共通する場合には、両工程により形成した構造寸法に関連が生ずる可能性があるので、基準抵抗R12の形成工程は、補償用抵抗R11の形成工程とは形成材料と形成方法の少なくとも一方が異なることが好ましい。例えば、形成材料としては、導電性を有する多結晶シリコンに対して金属層や基板内の不純物領域を用いること、或いは、形成方法としては、CVD法に対してスパッタリング法、蒸着法、イオン注入法などを用いることなどが挙げられる。   Further, the resistance layer constituting the reference resistor R12 is formed in a process different from the process of forming the movable portion 13a. For example, it can be formed together with the fixed electrode 12 by forming the first conductive layer and patterning it. However, although the forming process of the compensation resistor 11 and the forming process of the reference resistor R12 are different processes, if they are common in that they are processes using the same kind of material and film forming method, they are formed by both processes. Since there is a possibility that the structure dimension is related, it is preferable that the formation process of the reference resistor R12 is different from the formation process of the compensation resistor R11 in at least one of the formation material and the formation method. For example, as a forming material, a metal layer or an impurity region in the substrate is used for conductive polycrystalline silicon, or as a forming method, sputtering method, vapor deposition method, ion implantation method is used for CVD method. And the like.

上記のようにして形成されたMEMSレゾネータ10、補償用抵抗R11、基準抵抗R12の上には層間絶縁膜(図示せず)が形成され、この層間絶縁膜上にはさらに金属膜が形成され適宜にパターニングされることで、層間絶縁膜に形成されたスルーホールを通して下層構造と導電接続された入力側の第1の端子10a、出力側の第2の端子10b、補償用抵抗端子20a,20b、基準抵抗端子20c,20d、及び、配線10cが形成される。入力側の第1の端子10aは可動電極13と導電接続され、出力側の第2の端子10bは固定電極12と導電接続される。出力側の第2の端子10bは配線部10cを介して補償用抵抗端子20b及び基準抵抗端子20cに導電接続される。補償用抵抗端子20aと基準抵抗端子20bは補償用抵抗R11の平面方向に延長された長手方向両端部にそれぞれ導電接続され、基準抵抗端子20cと20dは基準抵抗R12の平面方向に延長された長手方向両端部にそれぞれ導電接続される。   An interlayer insulating film (not shown) is formed on the MEMS resonator 10, the compensation resistor R11, and the reference resistor R12 formed as described above, and a metal film is further formed on the interlayer insulating film. To the input side first terminal 10a, the output side second terminal 10b, the compensation resistance terminals 20a and 20b, which are conductively connected to the lower layer structure through through holes formed in the interlayer insulating film. Reference resistance terminals 20c and 20d and wiring 10c are formed. The first terminal 10 a on the input side is conductively connected to the movable electrode 13, and the second terminal 10 b on the output side is conductively connected to the fixed electrode 12. The output-side second terminal 10b is conductively connected to the compensation resistor terminal 20b and the reference resistor terminal 20c through the wiring portion 10c. The compensation resistor terminal 20a and the reference resistor terminal 20b are conductively connected to both ends in the longitudinal direction of the compensation resistor R11 extending in the plane direction, and the reference resistor terminals 20c and 20d are elongated in the plane direction of the reference resistor R12. Conductive connections are made to both ends in the direction.

上記構成において、MEMSレゾネータ10を構成する固定電極12及び可動部13aは、層間絶縁膜などが形成されない収容空間10A(図示二点鎖線で示す。)内に配置される。この収容空間10Aは、基板上に上記各構造を形成した後に、後述する方法でリリース工程において層間絶縁膜を部分的にエッチングすることによって構成される。この収容空間10A内においては、固定電極12と可動部13aは相互に直接対向し、可動部13aが固定電極12の上方において対向間隔を変化させる方向に可動に構成される。   In the above configuration, the fixed electrode 12 and the movable portion 13a constituting the MEMS resonator 10 are arranged in a housing space 10A (indicated by a two-dot chain line in the drawing) where an interlayer insulating film or the like is not formed. The accommodation space 10A is formed by partially etching the interlayer insulating film in a release process by a method described later after forming each of the above structures on the substrate. In the accommodation space 10 </ b> A, the fixed electrode 12 and the movable portion 13 a are directly opposed to each other, and the movable portion 13 a is configured to be movable in a direction in which the facing interval is changed above the fixed electrode 12.

この図示例において、補償用抵抗R11と基準抵抗R12は抵抗層の延長方向が基板上において同一直線状に配列されるように配置される。また、補償用抵抗R11と基準抵抗R12の上記延長方向は固定電極12及び可動電極13の延長方向(図示例では固定電極12上に可動電極13が張り出す方向と一致する方向)とが基板上において平行となるように形成されている。   In this illustrated example, the compensation resistor R11 and the reference resistor R12 are arranged such that the extending direction of the resistance layer is arranged in the same straight line on the substrate. Further, the extending direction of the compensation resistor R11 and the reference resistor R12 is the extending direction of the fixed electrode 12 and the movable electrode 13 (in the illustrated example, the direction coinciding with the direction in which the movable electrode 13 protrudes on the fixed electrode 12). Are formed so as to be parallel to each other.

図8(b)は、上記第1実施形態の図8(a)に示す構成とは異なる他の構成例を示す概略部分斜視図である。ここで、各端子部や配線の結線関係については上記構成と同様であるので、それらの説明は省略する。この構成例では、基板上に形成される収容空間10A′内に補償用抵抗R11が配置されている点で、図8(a)に示す例とは異なる。このように補償用抵抗R11をMEMSレゾネータ10の配置される収容空間10A′内に配置することで、可動部13aと補償用抵抗R11とを同一の製造条件で形成することができる。   FIG. 8B is a schematic partial perspective view showing another configuration example different from the configuration shown in FIG. 8A of the first embodiment. Here, since the connection relation between each terminal part and wiring is the same as that of the above-described configuration, the description thereof is omitted. This configuration example is different from the example shown in FIG. 8A in that the compensation resistor R11 is disposed in the accommodation space 10A ′ formed on the substrate. By disposing the compensation resistor R11 in the accommodating space 10A ′ in which the MEMS resonator 10 is disposed in this way, the movable portion 13a and the compensation resistor R11 can be formed under the same manufacturing conditions.

この図示例においても、補償用抵抗R11と基準抵抗R12は抵抗層の延長方向が基板上において同一直線状に配列されるように配置される。また、補償用抵抗R11と基準抵抗R12の上記延長方向は固定電極12及び可動電極13の延長方向(図示例では固定電極12上に可動電極13が張り出す方向と一致する方向)とが基板上において平行となるように形成されている。ただし、この例では、可動部13aを備えたMEMSレゾネータ10と補償用抵抗R11とが上記延長方向と交差(直交)する方向に隣接して配置される。すなわち、基板上においてMEMSレゾネータ10と補償用抵抗R11との間に他の導電層や配線層等の導体が介在していない。このように可動部と補償用抵抗が隣接することで、形成時の成膜条件に依存する膜厚値についても関連性を高めることができるので、共振周波数の補償効果を高めることができる。   Also in this illustrated example, the compensation resistor R11 and the reference resistor R12 are arranged such that the extending direction of the resistance layer is arranged in the same straight line on the substrate. Further, the extending direction of the compensation resistor R11 and the reference resistor R12 is the extending direction of the fixed electrode 12 and the movable electrode 13 (in the illustrated example, the direction coinciding with the direction in which the movable electrode 13 protrudes on the fixed electrode 12). Are formed so as to be parallel to each other. However, in this example, the MEMS resonator 10 including the movable portion 13a and the compensation resistor R11 are disposed adjacent to each other in a direction intersecting (orthogonal) with the extension direction. That is, no conductor such as another conductive layer or wiring layer is interposed between the MEMS resonator 10 and the compensation resistor R11 on the substrate. Since the movable portion and the compensation resistor are adjacent to each other in this manner, the relevance can be increased with respect to the film thickness value depending on the film formation condition at the time of formation, so that the resonance frequency compensation effect can be enhanced.

本実施形態では、収容空間10A′が上記延長方向と交差(直交)する方向に延在して、互いに隣接する可動部13aと補償用抵抗R11を共に包含するように構成されている。このように可動部13aと補償用抵抗R11とが共通の収容空間10A内に共に配置されることで、収容空間10A′を形成する際のエッチングによる影響が可動部13aと補償用抵抗R11に等しく作用するので、当該エッチング工程の有無による両者間の膜厚の関連性の低下を防止できる。   In the present embodiment, the accommodation space 10A ′ extends in a direction intersecting (orthogonal) with the extension direction and includes both the movable portion 13a and the compensation resistor R11 adjacent to each other. Thus, the movable part 13a and the compensation resistor R11 are arranged together in the common accommodation space 10A, so that the influence of etching when forming the accommodation space 10A ′ is equal to the movable part 13a and the compensation resistor R11. Therefore, it is possible to prevent a decrease in the relationship between the thicknesses due to the presence or absence of the etching process.

図9は上記とは別の平面構造の例を示す概略平面図である。なお、この図9においても回路要素間の結線関係の一部については線で模式的に描いてある。この例では、可動電極13が第1の端子10aに接続され、固定電極12が第2の端子10bに接続されている点では上記と同様である。しかしながら、第1の端子10aは補償用抵抗R11と基準抵抗R12の接続点に接続され、第2の端子10bは接地用抵抗R13に接続されている。この接地用抵抗R13の他端は接地電位に接続される。また、第1の端子10aは図示しない入力側結合容量に接続され、第2の端子10bは図示しない出力側結合容量に接続される。この構成でも、補償用抵抗R11は可動部13aを備えたMEMSレゾネータ10と隣接して配置されている。可動部13aを含むMEMSレゾネータ10は収容空間10A″に収容されている。この場合に、収容空間10A″を拡張して、隣接する補償用抵抗R11をも収容するように構成してもよい。   FIG. 9 is a schematic plan view showing an example of a planar structure different from the above. In FIG. 9 as well, a part of the connection relation between circuit elements is schematically drawn with lines. In this example, the movable electrode 13 is connected to the first terminal 10a, and the fixed electrode 12 is connected to the second terminal 10b. However, the first terminal 10a is connected to the connection point between the compensation resistor R11 and the reference resistor R12, and the second terminal 10b is connected to the grounding resistor R13. The other end of the grounding resistor R13 is connected to the ground potential. The first terminal 10a is connected to an input side coupling capacitor (not shown), and the second terminal 10b is connected to an output side coupling capacitor (not shown). Even in this configuration, the compensation resistor R11 is disposed adjacent to the MEMS resonator 10 including the movable portion 13a. The MEMS resonator 10 including the movable portion 13a is accommodated in the accommodating space 10A ″. In this case, the accommodating space 10A ″ may be expanded to accommodate the adjacent compensation resistor R11.

なお、上記の図8及び図9に示した構成を、固定電極12を第1の端子10aに接続し、可動電極13を第2の端子10bに接続するように変更してもよい。また、上記各電極や抵抗は全てポリシリコン層で構成されることが好ましい。一般的に、ポリシリコン層のシート抵抗としては1.0〜2.0kΩ/□(ohm/square)程度の値が容易に得られる。   8 and 9 may be modified so that the fixed electrode 12 is connected to the first terminal 10a and the movable electrode 13 is connected to the second terminal 10b. Moreover, it is preferable that each said electrode and resistance are comprised by a polysilicon layer altogether. Generally, the sheet resistance of the polysilicon layer is easily obtained as a value of about 1.0 to 2.0 kΩ / □ (ohm / square).

図10は、本発明に係る共振回路30と、この共振回路30に接続された信号回路部40とを有する電子装置の実施例を示す概略回路構成図である。ここで、図示例では、第1実施形態の共振回路30を用いた発振回路を構成した場合を示している。なお、この例において第1実施形態の代わりに第2実施形態の共振回路30′を用いても構わない。   FIG. 10 is a schematic circuit configuration diagram showing an embodiment of an electronic device having a resonance circuit 30 according to the present invention and a signal circuit unit 40 connected to the resonance circuit 30. Here, in the illustrated example, a case where an oscillation circuit using the resonance circuit 30 of the first embodiment is configured is shown. In this example, the resonance circuit 30 'of the second embodiment may be used instead of the first embodiment.

この実施例では、共振回路30の入力端子30a、出力端子30bを信号回路部40に接続し、この信号回路部40には、共振回路30と並列に接続された負性抵抗を有する増幅回路INV1と、共振回路30と並列に接続された帰還抵抗Rfbとが設けられる。また、これらの増幅回路INV、帰還抵抗Rfb及び共振回路30の両端部(入力端子30a及び出力端子30b)は静電容量Cg及びCdを介して定電位(接地電位)に接続される。また、これらの並列回路は増幅回路INV2に接続され、この増幅回路INV2から出力電位Voutが出力される。   In this embodiment, the input terminal 30 a and the output terminal 30 b of the resonance circuit 30 are connected to the signal circuit unit 40, and the signal circuit unit 40 includes an amplifier circuit INV 1 having a negative resistance connected in parallel with the resonance circuit 30. And a feedback resistor Rfb connected in parallel with the resonance circuit 30 is provided. Further, both ends (input terminal 30a and output terminal 30b) of the amplifier circuit INV, the feedback resistor Rfb, and the resonance circuit 30 are connected to a constant potential (ground potential) via capacitances Cg and Cd. These parallel circuits are connected to the amplifier circuit INV2, and the output potential Vout is output from the amplifier circuit INV2.

図11は、上記バイアス電圧供給部20の抵抗R12、14などの基準抵抗の構成例を示す部分平面図(a)及び部分断面図(b)である。この構成例は、共通の半導体よりなる基板1上にMEMSレゾネータ10及びバイアス回路20を形成する場合の例として構成してある。シリコン基板等の半導体よりなる基板1上には酸化シリコン等よりなる絶縁膜2が形成され、この絶縁膜2上にはアルミニウム等よりなる配線部3B及び3Cが形成される。基板1の表層部には不純物領域1Aが形成され、この不純物領域1A内の表面部分には不純物領域1Aよりさらに不純物濃度を高めて導電性を向上させたコンタクト領域1B、1Cが形成される。ここで、たとえば基板1がp型基板であれば、不純物領域1Aはn型不純物領域であり、コンタクト領域1B、1Cは高濃度n型不純物領域である。上記配線部3B及び3Cはそれぞれ絶縁膜2のスルーホールを通して上記コンタクト領域1B、1Cに導電接続される。   FIG. 11 is a partial plan view (a) and a partial cross-sectional view (b) showing a configuration example of reference resistors such as the resistors R12 and R14 of the bias voltage supply unit 20. In this configuration example, the MEMS resonator 10 and the bias circuit 20 are formed on the substrate 1 made of a common semiconductor. An insulating film 2 made of silicon oxide or the like is formed on a substrate 1 made of a semiconductor such as a silicon substrate, and wiring portions 3B and 3C made of aluminum or the like are formed on the insulating film 2. Impurity regions 1A are formed in the surface layer portion of the substrate 1, and contact regions 1B and 1C are formed on the surface portion in the impurity regions 1A. The contact regions 1B and 1C have a higher impurity concentration than the impurity regions 1A and have improved conductivity. Here, for example, if substrate 1 is a p-type substrate, impurity region 1A is an n-type impurity region, and contact regions 1B and 1C are high-concentration n-type impurity regions. The wiring portions 3B and 3C are conductively connected to the contact regions 1B and 1C through the through holes of the insulating film 2, respectively.

上記のように基板1の表層部に形成した不純物領域1Aによって基準抵抗R12を構成することにより、補償用抵抗R11とは抵抗の構成材料も形成方法も異なることから、基板上に形成される可動部13aの構造寸法とは連動しない抵抗要素とすることができる。この場合に、不純物領域1Aの不純物濃度、領域サイズ、コンタクト部1B、1Cの間の平面距離などによって抵抗値を適宜に設定することができる。また、抵抗要素の主要部が基板1の表層部に形成されるため、基板1上に設けられる構造に影響を与えにくく、当該構造の設計上の自由度を高めることができるという利点もある。   Since the reference resistor R12 is constituted by the impurity region 1A formed in the surface layer portion of the substrate 1 as described above, the resistance constituent material and the forming method are different from those of the compensation resistor R11, so that the movable resistor formed on the substrate is formed. It can be set as the resistance element which does not interlock | cooperate with the structural dimension of the part 13a. In this case, the resistance value can be appropriately set according to the impurity concentration of the impurity region 1A, the region size, the planar distance between the contact portions 1B and 1C, and the like. In addition, since the main part of the resistance element is formed on the surface layer portion of the substrate 1, there is an advantage that the structure provided on the substrate 1 is hardly affected and the degree of freedom in designing the structure can be increased.

図12は、基準抵抗の他の構成例を模式的に示す回路図である。図12(a)に示す例は基板に形成された電界効果トランジスタ(FET)のゲートに所定のゲート電圧を印加したときのチャネル抵抗を抵抗要素としたもの、図12(b)に示す例はゲートをソースに接続した定電流源を構成して抵抗要素として用いるものである。また、図12(c)に示す例はpチャネル型MOSFETとnチャネル型MOSFETのそれぞれのゲートとソースを接続して直列に接続された分圧回路を構成した例を示すが、当該分圧回路のいずれか一方を基準抵抗とし、他方を上記の補償用抵抗と置き換えることにより、上記バイアス回路を構成できる。   FIG. 12 is a circuit diagram schematically showing another configuration example of the reference resistor. In the example shown in FIG. 12A, the channel resistance when a predetermined gate voltage is applied to the gate of a field effect transistor (FET) formed on the substrate is used as a resistance element. In the example shown in FIG. A constant current source having a gate connected to a source is configured and used as a resistance element. Further, the example shown in FIG. 12C shows an example in which a voltage dividing circuit connected in series by connecting gates and sources of a p-channel MOSFET and an n-channel MOSFET is formed. The bias circuit can be configured by replacing one of the reference resistors as the reference resistor and the other with the compensation resistor.

なお、上記基準抵抗は、基板内に形成されたポリシリコン抵抗などの抵抗体を所望値にトリミングなどで調整したものでも良い。また、上記基準抵抗は上記MEMSレゾネータが形成された基板外に別素子で配置されていても良い。要は、上記基準抵抗は上記補償用抵抗R11もしくはR15、またはその両方と連動して抵抗値が変わらない構造体もしくは素子で形成されていれば良い。   Note that the reference resistance may be adjusted by trimming a resistor such as a polysilicon resistor formed in the substrate to a desired value. The reference resistor may be arranged as a separate element outside the substrate on which the MEMS resonator is formed. In short, the reference resistor may be formed of a structure or element whose resistance value does not change in conjunction with the compensation resistor R11 or R15, or both.

最後に、図13を参照して、本発明に係る共振回路の製造方法について説明する。この例では、図13(a)に示す半導体基板(例えば、単結晶シリコン等よりなるp型半導体基板)1を用意し、次に、図13(b)に示すように、基板1上に酸化シリコン等よりなる絶縁膜2を形成する。次に、図13(c)に示すように、特にMEMSレゾネータ10の下に形成される窒化シリコン等の絶縁膜よりなる下地層11を形成する。この下地層11は、後述するリリース工程においてリリースエッチングの停止層として機能するものである。   Finally, with reference to FIG. 13, a method for manufacturing a resonant circuit according to the present invention will be described. In this example, a semiconductor substrate (for example, a p-type semiconductor substrate made of single crystal silicon or the like) 1 shown in FIG. 13A is prepared, and then oxidized on the substrate 1 as shown in FIG. 13B. An insulating film 2 made of silicon or the like is formed. Next, as shown in FIG. 13C, a base layer 11 made of an insulating film such as silicon nitride formed under the MEMS resonator 10 is formed. The underlayer 11 functions as a release etching stop layer in a release process described later.

その後、図13(d)に示すように、下地層11上に導電性を有する多結晶シリコン等の第1導電層を成膜し、パターニングすることによって固定電極12を形成する。この工程は、例えば、多結晶シリコンを成膜した後に不純物を注入して導電性を付与し、その後、レジスト形成、エッチング等のパターニング処理を行うことで実施できる。そして、図13(e)に示すように、この固定電極12上にPSG(リンドープガラス)等の絶縁膜よりなる犠牲層3を形成する。なお、この犠牲層3は固定電極12に熱酸化処理を施すことで生ずる熱酸化膜で構成することも可能である。   Thereafter, as shown in FIG. 13D, a fixed conductive layer 12 is formed by forming a first conductive layer such as polycrystalline silicon having conductivity on the base layer 11 and patterning it. This step can be performed, for example, by implanting impurities after film formation of polycrystalline silicon to impart conductivity, and then performing a patterning process such as resist formation or etching. Then, as shown in FIG. 13E, a sacrificial layer 3 made of an insulating film such as PSG (phosphorus doped glass) is formed on the fixed electrode 12. The sacrificial layer 3 can also be formed of a thermal oxide film generated by subjecting the fixed electrode 12 to thermal oxidation.

さらに、図13(f)に示すように、犠牲層3の上には上記と同様の導電性の多結晶シリコン等の第2導電層を成膜し、パターニングすることにより可動電極13及び抵抗層R11を同時に形成する。ここで、可動電極13は上述のように固定電極12と対向する可動部13aを備えている。また、抵抗層R11は上述の補償用抵抗を構成するもので、可動電極13(の可動部13a)と同一の材料で、かつ、同一の方法(すなわち、同一の成膜プロセス及びパターニングプロセス)で形成される。したがって、可動部13aと抵抗層R11は基本的に同様の成膜量とパターニング精度で形成されているため、構造寸法、たとえば、厚み、平面形状の長さや幅のばらつきが連動する傾向を有する。すなわち、一般に可動部13aの或る構造寸法が設計値より大きくなれば、抵抗層R11の同じ構造寸法も設計値より大きくなる。特に、可動部13aと抵抗層R11の厚みは本来小さな寸法とされるので、その厚みのばらつきの割合は他の構造寸法よりきわめて大きく、その分、上述のように共振周波数に対する影響も大きい。   Further, as shown in FIG. 13 (f), a second conductive layer made of conductive polycrystalline silicon or the like similar to the above is formed on the sacrificial layer 3, and patterned to form the movable electrode 13 and the resistance layer. R11 is formed simultaneously. Here, the movable electrode 13 includes the movable portion 13a facing the fixed electrode 12 as described above. The resistance layer R11 constitutes the compensation resistor described above, and is made of the same material as the movable electrode 13 (the movable portion 13a thereof) and in the same method (that is, the same film forming process and patterning process). It is formed. Therefore, since the movable portion 13a and the resistance layer R11 are basically formed with the same film formation amount and patterning accuracy, there is a tendency that variations in structural dimensions, for example, thickness, planar length and width, are linked. That is, generally, if a certain structural dimension of the movable portion 13a is larger than the design value, the same structural dimension of the resistance layer R11 is also larger than the design value. In particular, since the thickness of the movable portion 13a and the resistance layer R11 is originally a small dimension, the ratio of the variation in the thickness is much larger than the other structural dimensions, and accordingly, the influence on the resonance frequency is large as described above.

なお、図13(d)、(e)及び(f)においては補償用抵抗R11の形成領域において下地層11を残しておき、この下地層11上に補償用抵抗R11を形成しているが、一般的には上述のように下地層11は収容空間10Aを形成する際のリリースエッチングから下層構造を保護するためのエッチングストップ層として機能するものであるので、下地層11を後に収容空間10Aが形成される領域に限定して形成し、他の領域である補償用抵抗R11の形成領域から除去するようにしてもよい。この場合、補償用抵抗R11は絶縁膜2上に形成される。   13D, 13E, and 13F, the base layer 11 is left in the formation region of the compensation resistor R11, and the compensation resistor R11 is formed on the base layer 11. In general, as described above, the base layer 11 functions as an etching stop layer for protecting the lower layer structure from release etching when the storage space 10A is formed. It may be formed only in the region to be formed, and may be removed from the forming region of the compensation resistor R11 which is another region. In this case, the compensation resistor R11 is formed on the insulating film 2.

その後、図13(g)に示すように、酸化シリコン等よりなる層間絶縁膜4、6、8と、アルミニウム等よりなる配線層5、7とが交互に積層される。また、図示しないが、基準抵抗である別の抵抗層R11やその他の抵抗層R13及びこれらを接続する配線部を含む構造部分も基板1上に形成され、これによってバイアス回路20が基板1上に一体に構成される。この場合、MEMSレゾネータ10とバイアス回路20は上記配線層5,7を介して接続される。さらに、上記の信号回路部40を構成する構造部分もまた基板1上に一体に構成されることで、上述の電子装置が一体に構成されることが好ましい。   Thereafter, as shown in FIG. 13G, interlayer insulating films 4, 6, 8 made of silicon oxide or the like and wiring layers 5, 7 made of aluminum or the like are alternately laminated. Further, although not shown, a structure portion including another resistance layer R11 which is a reference resistance, another resistance layer R13, and a wiring portion connecting them is also formed on the substrate 1, whereby the bias circuit 20 is formed on the substrate 1. It is constructed integrally. In this case, the MEMS resonator 10 and the bias circuit 20 are connected via the wiring layers 5 and 7. Furthermore, it is preferable that the above-described electronic device is integrally formed by also integrally forming the structural portion constituting the signal circuit unit 40 on the substrate 1.

上記層間絶縁膜8上にはレジスト等の樹脂や窒化シリコン等よりなる保護膜9が形成され、この保護膜9のMEMSレゾネータ10の上方位置に開口部9aを形成する。そして、この開口部9aを通して緩衝フッ酸等のエッチング液やエッチングガスにより、その下方にある上記犠牲層3及び層間絶縁膜4,6,8を除去し、図13(h)に示す収容空間10Aを形成する(リリース工程)。これによって可動部13aが解放されて可動に構成され、MEMSレゾネータ10が動作可能な状態とされる。   A protective film 9 made of a resin such as a resist or silicon nitride is formed on the interlayer insulating film 8, and an opening 9 a is formed above the MEMS resonator 10 in the protective film 9. Then, the sacrificial layer 3 and the interlayer insulating films 4, 6, and 8 are removed through the opening 9 a with an etching solution such as buffered hydrofluoric acid or an etching gas, and the accommodation space 10 </ b> A shown in FIG. Is formed (release process). As a result, the movable portion 13a is released to be movable, and the MEMS resonator 10 is operable.

なお、上述の図8(b)に示すように抵抗層R11が配置される収容空間10A′を形成する場合も、その製造方法は上記と何ら変わるものではなく、上記リリース工程において除去する範囲を抵抗層R11の形成領域にも亘るように設定すればよい。   In addition, when forming the accommodating space 10A ′ in which the resistance layer R11 is disposed as shown in FIG. 8B, the manufacturing method is not different from the above, and the range to be removed in the release step is not limited. What is necessary is just to set so that the formation area of resistance layer R11 may be covered.

図14は上記とは異なる他の製造方法の例を示す工程断面図である。この製造方法では、図14(a)乃至(d)に示すように、基板1上に絶縁膜2、下地層11及び固定電極12を形成するまでの工程は図13に示すものと同様である。   FIG. 14 is a process sectional view showing an example of another manufacturing method different from the above. In this manufacturing method, as shown in FIGS. 14A to 14D, the steps until the insulating film 2, the base layer 11 and the fixed electrode 12 are formed on the substrate 1 are the same as those shown in FIG. .

その後、図14(e)に示すように酸化シリコン等の絶縁膜3′をCVD法や熱酸化法等により全面的に形成し、この絶縁膜3′をパターニングすることによって図14(f)に示すように可動電極13の支持部が形成される領域を除去する。このとき、補償用抵抗R11が形成される領域には絶縁膜3′が残った状態とされる。   Thereafter, as shown in FIG. 14E, an insulating film 3 'such as silicon oxide is formed on the entire surface by CVD or thermal oxidation, and this insulating film 3' is patterned to obtain the structure shown in FIG. As shown, the region where the support of the movable electrode 13 is formed is removed. At this time, the insulating film 3 'remains in the region where the compensation resistor R11 is formed.

次に、図14(g)に示すように、上記と同様の第2導電層を成膜し、パターニングすることによって可動電極13及び抵抗層R11を同時に形成する。このとき、可動部13aと補償用抵抗R11は同じ絶縁膜3′を下地層とし、この上にそれぞれ成膜されるので、可動部13aと補償用抵抗R11の成膜条件をさらに同等のものとすることができる。したがって、可動部13aと補償用抵抗R11の膜厚の変動態様をより近似したものとすることができるので、補償用抵抗R11による上述の共振周波数の補償効果をさらに高めることが可能になる。ただし、可動電極13の可動部13a以外の支持部は上記絶縁膜3′の形成されていない領域において上記下地層11上に設けられる。その後は、上記図13の場合と同様に、図14(h)に示すように上層構造を形成したのちにリリース工程により収容空間10Aを形成する。   Next, as shown in FIG. 14G, the second conductive layer similar to the above is formed and patterned to form the movable electrode 13 and the resistance layer R11 at the same time. At this time, since the movable portion 13a and the compensation resistor R11 are formed on the same insulating film 3 'as a base layer, respectively, the deposition conditions of the movable portion 13a and the compensation resistor R11 are further equivalent. can do. Therefore, the variation aspect of the film thicknesses of the movable portion 13a and the compensation resistor R11 can be approximated, so that the above-described resonance frequency compensation effect by the compensation resistor R11 can be further enhanced. However, the support portion other than the movable portion 13a of the movable electrode 13 is provided on the base layer 11 in a region where the insulating film 3 'is not formed. Thereafter, similarly to the case of FIG. 13, the upper space structure is formed as shown in FIG. 14 (h), and then the accommodation space 10A is formed by a release process.

なお、以上述べた各実施形態は本発明を実施するための一例に過ぎないので、本発明は、上述の図示例にのみ限定されるものではなく、例えば、上記各実施形態の特徴点を相互に矛盾しない限り任意に組み合わせて実施することができるなど、本発明の要旨を逸脱しない範囲内において種々変更を加え得ることは勿論である。   Each embodiment described above is only an example for carrying out the present invention. Therefore, the present invention is not limited to the illustrated example described above. For example, the feature points of the respective embodiments are mutually described. Needless to say, various modifications can be made without departing from the gist of the present invention, for example, as long as they do not contradict each other.

1…基板、2…絶縁膜、10…MEMSレゾネータ、10a…第1の端子、10b…第2の端子、11…下地層、12…固定電極、13…可動電極、13a…可動部、20…バイアス回路、R11、R15…補償用抵抗、R12、R14…基準抵抗、30、30′…共振回路、30a…入力端子、30b…出力端子、40…信号回路部、Vq…第1の電位、Vp…第2の電位、INV1…負性抵抗を有する増幅回路 DESCRIPTION OF SYMBOLS 1 ... Board | substrate, 2 ... Insulating film, 10 ... MEMS resonator, 10a ... 1st terminal, 10b ... 2nd terminal, 11 ... Underlayer, 12 ... Fixed electrode, 13 ... Movable electrode, 13a ... Movable part, 20 ... Bias circuit, R11, R15: Compensation resistor, R12, R14: Reference resistor, 30, 30 '... Resonant circuit, 30a ... Input terminal, 30b ... Output terminal, 40 ... Signal circuit unit, Vq ... First potential, Vp ... Second potential, INV1, ... Amplifier circuit having negative resistance

Claims (15)

基板と、該基板上に形成された固定電極、及び、該固定電極の少なくとも一部に対向する可動部を備えた可動電極を有するMEMSレゾネータと、該MEMSレゾネータにバイアス電圧を印加する電圧印加手段と、を具備し、
前記電圧印加手段は、前記可動部と同じ層で構成され該層の厚みで抵抗値が変化する補償用抵抗と、該補償用抵抗に接続され前記可動部と異なる層で構成される基準抵抗とを備え、前記補償用抵抗と前記基準抵抗の接続点電位を前記MEMSレゾネータの第1の端子と第2の端子のうちの少なくとも一方の端子に出力する分圧回路を有することを特徴とする共振回路。
A MEMS resonator having a substrate, a fixed electrode formed on the substrate, and a movable electrode having a movable portion facing at least a part of the fixed electrode, and a voltage applying means for applying a bias voltage to the MEMS resonator And comprising
The voltage applying means is composed of the same layer as the movable part and has a compensation resistor whose resistance value varies with the thickness of the layer, and a reference resistor connected to the compensation resistor and composed of a layer different from the movable part. And a voltage dividing circuit that outputs a potential at a connection point between the compensation resistor and the reference resistor to at least one of the first terminal and the second terminal of the MEMS resonator. circuit.
前記電圧印加手段は、前記接続点電位を前記MEMSレゾネータの前記第1の端子と前記第2の端子のうちの一方の端子に出力するとともに、前記MEMSレゾネータの他方の端子に他の電位を出力することを特徴とする請求項1に記載の共振回路。   The voltage applying means outputs the connection point potential to one of the first terminal and the second terminal of the MEMS resonator and outputs another potential to the other terminal of the MEMS resonator. The resonance circuit according to claim 1, wherein: 前記分圧回路では、前記補償用抵抗と前記基準抵抗とが高電位と低電位の間に直列に接続され、前記接続点電位が前記他の電位より高い場合には前記補償用抵抗側に前記高電位が接続されるとともに前記基準抵抗側に前記低電位が接続され、前記接続点電位が前記他の電位より低い場合には前記補償用抵抗側に前記低電位が接続されるとともに前記基準抵抗側に前記低電位が接続されることを特徴とする請求項2に記載の共振回路。   In the voltage dividing circuit, the compensation resistor and the reference resistor are connected in series between a high potential and a low potential, and when the connection point potential is higher than the other potential, the compensation resistor and the reference resistor are connected to the compensation resistor side. When the high potential is connected, the low potential is connected to the reference resistance side, and when the connection point potential is lower than the other potential, the low potential is connected to the compensation resistance side and the reference resistance The resonance circuit according to claim 2, wherein the low potential is connected to the side. MEMSレゾネータの前記第1の端子と入力端子の間に接続された入力側結合容量と、前記第2の端子と出力端子の間に接続された出力側結合容量と、をさらに具備することを特徴とする請求項1乃至3のいずれか一項に記載の共振回路。   The MEMS resonator further includes an input side coupling capacitor connected between the first terminal and the input terminal, and an output side coupling capacitor connected between the second terminal and the output terminal. The resonance circuit according to any one of claims 1 to 3. 基板と、該基板上に形成された固定電極、及び、該固定電極の少なくとも一部に対向する可動部を備えた可動電極を有するMEMSレゾネータと、前記MEMSレゾネータの第1の端子に第1の電位を供給する第1の回路と、第2の端子に第2の電位を供給する第2の回路とを有し、前記MEMSレゾネータに前記第1の電位と前記第2の電位の差に相当するバイアス電圧を印加する電圧印加手段と、を具備し、
前記第1の回路と前記第2の回路のうち少なくとも一方は、前記可動部と同じ層で構成され該層の厚みで抵抗値が変化する補償用抵抗と、該補償用抵抗に接続され前記可動部と異なる層で構成される基準抵抗とを備え、前記補償用抵抗と前記基準抵抗の接続点電位を前記第1の電位若しくは前記第2の電位として出力する分圧回路であることを特徴とする共振回路。
A MEMS resonator having a substrate, a fixed electrode formed on the substrate, and a movable electrode having a movable portion facing at least a part of the fixed electrode, and a first terminal of the MEMS resonator A first circuit for supplying a potential; and a second circuit for supplying a second potential to a second terminal; corresponding to a difference between the first potential and the second potential in the MEMS resonator Voltage applying means for applying a bias voltage to
At least one of the first circuit and the second circuit is formed of the same layer as the movable part, and a compensation resistor whose resistance value varies with the thickness of the layer, and the movable resistor connected to the compensation resistor. A voltage dividing circuit including a reference resistor formed of a layer different from the unit, and outputting a potential at a connection point between the compensation resistor and the reference resistor as the first potential or the second potential. Resonant circuit.
前記可動部及び前記補償用抵抗は同一の材料で形成された導体層で構成され、前記基準抵抗は前記可動部及び前記補償用抵抗と異なる材料で形成された導体層で構成されることを特徴とする請求項1乃至5のいずれか一項に記載の共振回路。   The movable part and the compensation resistor are made of a conductor layer made of the same material, and the reference resistance is made of a conductor layer made of a material different from the movable part and the compensation resistor. The resonance circuit according to any one of claims 1 to 5. 前記可動部と前記補償用抵抗は隣接する導体層で構成されることを特徴とする請求項1乃至6のいずれか一項に記載の共振回路。   The resonance circuit according to claim 1, wherein the movable portion and the compensation resistor are formed of adjacent conductor layers. 前記可動部と前記補償用抵抗は共通の収容空間に収容されていることを特徴とする請求項1乃至7のいずれか一項に記載の共振回路。   The resonance circuit according to claim 1, wherein the movable portion and the compensation resistor are accommodated in a common accommodation space. 固定電極及び該固定電極の少なくとも一部に対向する可動部を備えた可動電極を有するMEMSレゾネータと、該MEMSレゾネータにバイアス電圧を印加する電圧印加手段とを具備する共振回路の製造方法において、
前記電圧印加手段は、補償用抵抗と基準抵抗とを備え、前記補償用抵抗と前記基準抵抗の接続点電位を前記MEMSレゾネータの少なくとも一方の端子に出力する分圧回路を有し、
前記可動部を形成するとともに、前記可動部と同じ層で前記補償用抵抗を形成する工程と、
前記可動部と異なる層で前記基準抵抗を形成する工程と、
を具備することを特徴とする共振回路の製造方法。
In a method of manufacturing a resonance circuit, comprising: a MEMS resonator having a fixed electrode and a movable electrode having a movable portion facing at least a part of the fixed electrode; and a voltage applying means for applying a bias voltage to the MEMS resonator.
The voltage application unit includes a compensation resistor and a reference resistor, and has a voltage dividing circuit that outputs a potential at a connection point between the compensation resistor and the reference resistor to at least one terminal of the MEMS resonator,
Forming the movable part and forming the compensation resistor in the same layer as the movable part;
Forming the reference resistance in a layer different from the movable part;
A method of manufacturing a resonant circuit comprising:
前記可動部及び前記補償用抵抗は同一の材料で同一の方法で形成された導体層で構成され、前記基準抵抗は前記可動部及び前記補償用抵抗と異なる材料若しくは異なる方法で形成された導体層で構成されることを特徴とする請求項9に記載の共振回路の製造方法。   The movable part and the compensation resistor are composed of a conductor layer formed of the same material and in the same method, and the reference resistance is a conductor layer formed of a material different from or different from the movable part and the compensation resistor. The method for manufacturing a resonance circuit according to claim 9, comprising: 前記可動部と前記補償用抵抗は隣接する導体層で構成されることを特徴とする請求項9又は10に記載の共振回路の製造方法。   The method of manufacturing a resonance circuit according to claim 9, wherein the movable portion and the compensation resistor are formed of adjacent conductor layers. 前記前記可動部と前記補償用抵抗が共に収容される共通の収容空間を形成する工程をさらに有することを特徴とする請求項9乃至11のいずれか一項に記載の共振回路の製造方法。   The method for manufacturing a resonance circuit according to claim 9, further comprising a step of forming a common accommodation space in which the movable part and the compensation resistor are accommodated. 請求項1乃至8のいずれか一項に記載の共振回路と、該共振回路に接続される信号回路部とが同一基板上に形成されてなることを特徴とする電子装置。   9. An electronic device comprising: the resonance circuit according to claim 1; and a signal circuit unit connected to the resonance circuit formed on the same substrate. 前記可動部と前記補償用抵抗とが前記基板上に形成された収容空間内に共に配置されることを特徴とする請求項13に記載の電子装置。   The electronic device according to claim 13, wherein the movable portion and the compensation resistor are disposed together in a housing space formed on the substrate. 前記信号回路部が負性抵抗を有する増幅回路を含み、発振回路を構成することを特徴とする請求項13又は14に記載の電子装置。   15. The electronic device according to claim 13, wherein the signal circuit unit includes an amplifier circuit having a negative resistance and constitutes an oscillation circuit.
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