JP2010226189A - Control circuit and inter-circuit communication method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control circuit enabling each channel to transmit a signal at the optimum frequency according to the characteristics of a transmission line, and also to provide an inter-circuit communication method. <P>SOLUTION: The control circuit is provided with: an output circuit 3 for outputting a data signal from a first circuit 1 through a plurality of channels in the transmission of the data signal from the first circuit 1 to a second circuit 2; and an input circuit 4 for inputting the data signal outputted from the output circuit 3 to the second circuit 2. The output circuit 3 includes: a clock frequency generation means 31 for supplying a plurality of different clock frequencies for the respective plurality of channels; and an output means 32 for outputting the data signal based on the plurality of different clock frequencies in each channel of the plurality of channels. The input circuit 4 includes a determination means 41 for selecting a data signal to be outputted to the second circuit 2, based on the result of comparing the receiving qualities of data acquired from the output means 32. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a control circuit and an inter-circuit communication method, and more particularly to frequency control in inter-circuit communication.

  In order to set an optimum communication speed when connecting the information processing apparatus and the external device using the serial communication means, it is necessary to set an optimum clock frequency in the information processing device and the external device. In such a case, Patent Document 1 discloses a technique for setting an optimal clock frequency by repeatedly transmitting test data using different clock frequencies between the information processing apparatus and the external device. More specifically, the information processing apparatus transmits test data using a certain clock frequency to an external device. The external device transmits the received test data to the information processing apparatus. By repeating this series of operations a plurality of times, the information processing apparatus determines an optimum clock frequency from the results of error verification of test data, measurement of delay time, and the like.

  Here, in the inter-circuit communication inside the apparatus, serial communication is often used against the background of cost merit and speeding up of serial communication. In addition, for the purpose of transmitting a large amount of data in inter-circuit communication, a method of performing serial communication between circuits using a plurality of channels has also been realized, and an efficient data signal control method in this case is desired. .

Japanese Patent No. 31888792

  As described above, when realizing multi-channel communication in which circuits are connected by a plurality of serial communication means, each channel normally performs transmission at the same frequency. In this case, the transmission paths connecting the circuits are designed to have substantially the same structure, but there may be some differences. In high-speed transmission, since the optimum frequency in each channel differs due to a slight difference in the structure of the transmission path, for example, a difference in line length, it becomes difficult to operate all channels at the same frequency.

  The present invention has been made to solve such problems, and an object of the present invention is to provide a control circuit and an inter-circuit communication method in which each channel can transmit at an optimum frequency in accordance with the characteristics of the transmission path. .

  In the transmission of the data signal from the first circuit to the second circuit, the control circuit according to the present invention outputs the data signal from the first circuit using a plurality of channels, and the output circuit A control circuit including an input circuit that inputs an output data signal to the second circuit, wherein the output circuit includes a clock frequency generation unit that supplies a plurality of different clock frequencies for each of the plurality of channels, and Each channel of the plurality of channels includes output means for outputting a data signal based on a plurality of different clock frequencies, and the input circuit is configured to compare the reception quality of the data acquired from the output means based on the result of comparison. The determination means which selects the data signal output to a 2nd circuit is provided.

  Further, an inter-circuit communication method according to the present invention includes an output circuit that outputs a data signal from the first circuit using a plurality of channels in transmission of a data signal from the first circuit to the second circuit; An inter-circuit communication method for inputting / outputting a data signal by an input circuit that inputs a data signal output from the output circuit to a second circuit, wherein each of the plurality of channels is a plurality of channels in the output circuit. And outputting a data signal based on different clock frequencies, and selecting a data signal to be output to the second circuit based on a result of comparing the reception quality of data acquired from the output means in the input circuit Providing the step of:

  According to the present invention, it is possible to provide a control circuit and an inter-circuit communication method in which each channel can transmit at an optimum frequency according to the characteristics of the transmission path.

1 is a configuration diagram of a control circuit according to a first embodiment; 1 is a configuration diagram of a control circuit according to a first embodiment; FIG. 3 is a schematic diagram of synchronization processing according to the first and second embodiments. 3 is a flowchart of the output circuit according to the first exemplary embodiment; 3 is a flowchart of the input circuit according to the first exemplary embodiment; FIG. 4 is a configuration diagram of a control circuit according to a second embodiment. 6 is a flowchart of a control circuit according to the second exemplary embodiment;

(Embodiment 1)
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of a control circuit according to the present invention. In the data signal from the first circuit 1 to the second circuit 2, the control circuit outputs the data signal from the first circuit 1 using a plurality of channels and the output circuit 3 outputs the data signal. And an input circuit 4 for inputting a data signal to the second circuit 2. Further, the output circuit 3 includes a clock frequency generation unit 31 and output units 32a to 32c. The input circuit 4 includes determination units 41a to 41c. Further, the output circuit 3 and the input circuit 4 can input and output data signals using a plurality of channels (channels 1 to n). FIG. 1 shows a configuration related to input / output of data of channel 1, channel 2, and channel n. The clock frequency generation unit 31 is used in common for each channel.

  The first circuit 1 outputs the data signal to the output circuit 3 when transmitting the data signal to the second circuit 2.

  The clock frequency generation unit 31 generates a plurality of clock frequencies. Further, the plurality of clock frequencies are generated at different frequencies. Here, in order to generate a plurality of clock frequencies, a plurality of clock frequency generation units 31 may exist, and one clock frequency generation unit 31 may generate a plurality of clock frequencies. The clock frequency generated by the clock frequency generation unit 31 is supplied to the output units 32a to 32c.

  The output units 32 a to 32 c output the data signal acquired from the first circuit 1 to the input circuit 4 based on the clock frequency acquired from the clock frequency generation unit 31. The output unit 32 a outputs a data signal to the input circuit 4 using the channel 1. Similarly, the output unit 32b outputs a data signal to the input circuit 4 using the channel 2, and the output unit 32c outputs a data signal to the input circuit 4 using the channel n.

  The determination unit 41a compares the reception qualities of a plurality of data signals acquired from the output unit 32a using the channel 1, and selects a data signal to be output to the second circuit 2 based on the result. Similarly, the determination unit 41b and the determination unit 41c compare the reception qualities of a plurality of data signals acquired from the channel 2 and the channel n, and select a data signal to be output to the second circuit based on the result. The data signal selected by the determination units 41 a to 41 c is output to the second circuit 2.

  Next, the configuration of the control circuit according to the first embodiment of the present invention will be described in detail with reference to FIG. The output circuit 3 includes a clock frequency generation unit 31, synchronization units 33a to 33c, synchronization units 34a to 34c, synchronization units 35a to 35c, PS (Parallel Serial) conversion units 36a to 36c, and an interface (I). / F) portions 37a to 37c. The input circuit 4 includes determination units 41a to 41c, SP (Serial Parallel) conversion units 42a to 42c, synchronization units 43a to 43c, and input units 44a to 44c. The output units 32a to 32c in the output circuit 3 of FIG. 1 include synchronization units 33a to 33c, synchronization units 34a to 34c, synchronization units 35a to 35c, PS conversion units 36a to 36c, and interface units 37a to 37c. Corresponding to

  The synchronization units 33a to 33c, the synchronization units 34a to 34c, and the synchronization units 35a to 35c synchronize the data signal acquired from the first circuit 1 with the clock frequency acquired from the clock frequency generation unit 31. . The data signal synchronized by the synchronization units 33a to 33c is output to the PS conversion unit 36a. The data signal synchronized by the synchronization units 34a to 34c is output to the PS conversion unit 36b. The data signal synchronized by the synchronization units 35a to 35c is output to the PS conversion unit 36c.

  Here, the synchronization processing will be specifically described with reference to FIG. In the data signal acquired by the synchronization unit, the change point appearing during T1 is synchronized with the timing at which the period of T2 starts. Further, the change point appearing during T2 is synchronized with the timing at which the period of T3 starts. When the start timing of T4 and the data change point timing become the same, synchronization may be performed at the start timing of T4. Then, the change point appearing during T4 is synchronized with the timing at which the period of T5 starts.

  The PS conversion unit 36a converts the data signal acquired from the synchronization units 33a to 33c from the parallel state to the serial state. Here, it is assumed that the first circuit stores data in the parallel state, and the output circuit 3 acquires the data signal in the parallel state from the first circuit 1. When data is acquired from the first circuit 1 in a serial state, the process of the PS conversion unit is not necessary. Similarly, the PS converters 36b and 36c also convert parallel data signals into a serial state. The data signal converted to the serial state is output to the interface units 37a to 37c.

  The interface unit 37 a outputs a data signal to the input circuit 4 using the channel 1. Similarly, the interface unit 37b uses the channel 2 and the interface unit 37c outputs the data signal to the input circuit 4 using the channel n.

  The input unit 44 a acquires the data signal output from the output circuit 3 using the channel 1. Similarly, the input unit 44b uses the channel 2 and the input unit 44c uses the channel n to acquire the data signal output from the output circuit 3, respectively. The input units 44a to 44c output the acquired data signals to the determination units 41a to 41c.

  The determination unit 41a acquires a data signal from the input unit 44a. Here, the determination unit 41a acquires a plurality of data signals synchronized with different clock frequencies. Therefore, the reception quality of a plurality of acquired data is compared, and the data signal with the best state is selected.

  For example, the error rate of the acquired data signal is calculated, the data signal with the lowest error rate value is identified as the data signal with the best state, and selection is performed. Alternatively, the waveform indicating the known pulse signal and the waveform of the acquired data signal are compared, and the data signal whose waveform is closest to the known pulse signal is identified as the data signal in the best state and selected. The selected data signal is output to the SP conversion unit 42a. Similarly, the determination units 41b and 41c select the data signal having the best state from the data signals acquired from the input unit 44b or 44c. The selected data signal is output to the SP converters 42b and 42c.

  The SP converters 42a to 42c convert the data signal in the serial state into the parallel state. The data signal converted into the parallel state is output to the synchronization units 43a to 43c.

  The synchronization units 43a to 43c obtain data signals from the SP conversion units 42a to 42c. The synchronization units 43a to 43c synchronize data signals using a clock frequency commonly used in the input circuit 4. Since the synchronization performs the same process as in FIG. 3, the description thereof is omitted.

  The synchronized data signal is output to the second circuit 2.

  Next, a processing flow of the output circuit according to the first exemplary embodiment of the present invention will be described with reference to FIG. The data signal acquired from the first circuit is duplicated and input to the synchronization units 33a to 33c, the synchronization units 34a to 34c, and the synchronization units 35a to 35c (S10).

  Next, the synchronization unit 33a performs a synchronization process on the data signal acquired from the first circuit 1 using the clock frequency generated by the clock frequency generation unit 31 (S11). The synchronization process is the same as that described above with reference to FIG. The synchronization units 33b to 33c, the synchronization units 34a to 34c, and the synchronization units 35a to 35c perform the synchronization process in the same manner.

  Next, the PS conversion unit 36a converts the parallel state data signal acquired from the synchronization units 33a to 33c into a serial state data signal (S12). The conversion is performed for each data signal synchronized by each synchronization unit, and sequentially output to the interface unit 37a. The PS conversion unit 36b and the PS conversion unit 36c perform similar processing.

  Next, the interface units 37 a to 37 c obtain serial data signals from the PS conversion units 36 a to 36 c and output them to the input circuit 4. The interface units 37a to 37c sequentially acquire data output from the PS conversion units 36a to 36c, and output data signals to the input circuit 4 in the acquired order.

  Next, the processing flow of the input circuit 4 according to the first exemplary embodiment of the present invention will be described with reference to FIG. The input units 44a to 44c acquire data signals from the interface units 37a to 37c of the output circuit 3 (S20). The acquired data signal is output to the determination units 41a to 41c.

  Next, the determination unit 41a acquires a plurality of data signals synchronized with different clock frequencies. Therefore, the reception quality of a plurality of acquired data is compared, and the data signal with the best state is selected.

  For example, the error rate of the acquired data signal is calculated (S21), the data signal having the lowest error rate value is identified as the data signal with the best state, and selection is performed (S22). Alternatively, the waveform indicating the known pulse signal and the waveform of the acquired data signal are compared, and the data signal whose waveform is closest to the known pulse signal is identified as the data signal in the best state and selected. The selected data signal is output to the SP conversion unit 42a. Similarly, the determination units 41b and 41c select the data signal having the best state from the acquired data signals. The selected data signal is output to the SP converters 42b and 42c.

  Next, the SP conversion units 42a to 42c convert the serial data signal into the parallel state (S23).

  Next, the synchronization units 43a to 43c perform synchronization processing on the data converted into the parallel state by the SP conversion unit 23 using a clock frequency commonly used in the input circuit 4, and the second circuit 2 (S24).

  As described above, the control circuit according to the first exemplary embodiment of the present invention can select data synchronized with an optimal clock frequency from among data synchronized with a plurality of clock frequencies. it can. As a result, the data signal can be output while the circuits are synchronized with each other at the optimum clock frequency, so that the communication quality can be improved.

  Next, the configuration of the control circuit according to the second embodiment of the present invention will be described with reference to FIG. The output circuit 3 includes control units 38a to 38c. Other configurations are the same as those in FIG.

  The determination units 41a to 41c of the input circuit 4 select the optimum data from the data synchronized at different clock frequencies in the output circuit 3. The clock frequency information used for the selected data is output to the output circuit 3. The control units 38a to 38c of the output circuit 3 acquire the clock frequency information output from the determination units 41a to 41c. For example, when the clock frequency information output from the determination unit 41a indicates the clock frequency used for the data signal synchronized by the synchronization unit 33a, the control unit 38a instructs the clock frequency generation unit 31 to The channel 1 is notified to supply the clock frequency only to the synchronization unit 33a. In other words, the control unit 38a notifies the clock frequency generation unit 31 to supply only the clock frequency indicated in the acquired clock frequency information. Similarly, the control units 38b and 38c acquire clock frequency information used for the channel 2 and the channel n and notify the clock frequency generation unit 31 of the clock frequency information.

  Next, the flow of processing according to the second embodiment of the present invention will be described with reference to FIG. Since the processes before the determination units 41a to 41c select the data synchronized with the optimal clock frequency are the same as those in FIGS. 4 and 5, the description thereof is omitted.

  When the determination units 41a to 41c of the input circuit 4 select the optimal data with the best state (S30), the clock frequency information used for the optimal data is output to the output circuit 3 (S31).

  Next, the control units 38a to 38c of the output circuit 3 acquire the clock frequency information output from the determination units 41a to 41c (S32). Next, the control unit 38a notifies the clock frequency generation unit 31 to supply the clock frequency indicated in the clock frequency information to the channel 1 (S33). That is, a notification is made so that a clock frequency other than the clock frequency indicated in the clock frequency information is not output to the channel 1. The same processing is performed for the control units 38b and 38c. For each channel, the clock generation unit 31 outputs a clock frequency other than the designated clock frequency to the synchronization units 33a to 33c, the synchronization units 34a to 34c, and the synchronization units 35a to 35c. Is canceled (S34). Note that, for example, when a certain clock frequency is not included in the notification from the control unit 38a but is included in the notification from the control unit 38b, the clock generation unit 31 determines that the clock to the channel 2 Continue to supply frequency.

  As described above, in the control circuit according to the second embodiment of the present invention, the output circuit 3 obtains information on the optimum clock frequency from the input circuit that receives the data signal, thereby obtaining an unnecessary clock frequency. Since the synchronization process can be deleted, the process can be reduced.

  The above description describes the embodiment of the present invention, and the present invention is not limited to the above embodiment. Moreover, those skilled in the art can easily change, add, and convert each element of the above embodiments within the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 1st circuit 2 2nd circuit 3 Output circuit 4 Input circuit 31 Clock frequency generation part 32a thru | or 32c Output part 33a thru | or 33c Synchronization part 34a thru | or 34c Synchronization part 35a thru | or 35c Synchronization part 36a thru | or 36c PS conversion part 37a thru | or 37c Interface unit 41a to 41c Determination unit 42a to 42c SP conversion unit 43a to 43c Synchronization unit 44a to 44c Input unit

Claims (10)

In transmission of a data signal from the first circuit to the second circuit, an output circuit that outputs the data signal from the first circuit using a plurality of channels, and a data signal output from the output circuit A control circuit comprising an input circuit for input to a second circuit,
The output circuit is
Clock frequency generating means for supplying a plurality of different clock frequencies for each of the plurality of channels;
Each of the plurality of channels comprises output means for outputting a data signal based on a plurality of different clock frequencies;
The input circuit is
A control circuit comprising determination means for selecting a data signal to be output to the second circuit based on a result of comparing the reception quality of data acquired from the output means. The determination means inputs clock frequency information used for the selected data to the output circuit,
2. The control circuit according to claim 1, wherein the output circuit further includes a clock frequency control unit that performs control to supply a clock frequency indicated by the clock frequency information to a channel that outputs the selected data. The output means further includes synchronization means for synchronizing data using a plurality of different clock frequencies,
2. The control circuit according to claim 1, wherein the data synchronized by the synchronization means is sequentially output.   3. The control circuit according to claim 1, wherein the determination unit selects data to be stored in the second circuit based on a result of comparing data error rates of a plurality of data acquired from the output unit. .   The determination unit selects data to be stored in the second circuit based on a result of comparing a plurality of data waveforms acquired from the output unit with a predetermined waveform. 2. The control circuit according to 2. In transmission of a data signal from the first circuit to the second circuit, an output circuit that outputs the data signal from the first circuit using a plurality of channels, and a data signal output from the output circuit An inter-circuit communication method for inputting / outputting a data signal by an input circuit that inputs to a circuit of
In the output circuit, each channel of the plurality of channels includes a step of outputting a data signal based on a plurality of different clock frequencies,
A circuit-to-circuit communication method comprising a step of selecting a data signal to be output to the second circuit based on a result of comparing reception quality of data acquired from the output means in the input circuit. Outputting clock frequency information used for the selected data to an output circuit;
7. The inter-circuit communication method according to claim 6, further comprising a step of performing control to supply a clock frequency indicated by the output clock frequency information to a channel that outputs the selected data in the output circuit. . The step of outputting the data signal includes synchronizing data using a plurality of different clock frequencies;
7. The inter-circuit communication method according to claim 6, further comprising a step of sequentially outputting the synchronized data.   8. The inter-circuit communication method according to claim 6 or 7, wherein the step of selecting data further comprises a step of selecting data to be stored in the second circuit based on a result of comparing data error rates of a plurality of data.   The circuit according to claim 6 or 7, wherein the step of selecting data further comprises a step of selecting data to be stored in the second circuit based on a result of comparing a plurality of waveforms with a predetermined waveform. Communication method.

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