JP2010219971A - Video signal switching apparatus, and video signal switching method used therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a video signal switching apparatus capable of making shockless an output video after switching. <P>SOLUTION: A video signal switching apparatus 1 includes: first and second extraction means 11 and 12 for extracting first and second time stamps superimposed beforehand on first and second video signals inputted from different transmission lines; a clock generating means 13 for generating a clock common for the first and second video signals on the basis of the first and second time stamps extracted by the first and second extraction means; first and second translocation means (buffer sections 14, 15 and a buffer control section 17) for translocating the first and second video signals onto the clock generated by the clock generating means; and a switching means 16 for switching out the outputs from the first and second translocation means in accordance with an external instruction. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a video signal switching device and a video signal switching method used therefor, and more particularly to a method for switching two systems of video signals input from a transmission path.

  FIG. 9 shows a configuration example of a video signal switching device related to the present invention. In FIG. 9, the video signal switching device 3 includes time stamp extraction units 31 and 36, clock generation units 32 and 37, buffer control units 33 and 38, buffer units 34 and 39, and a switching unit 35. ing.

  Two systems of video signals (video # 1, video # 2) are input to the video signal switching device 3 from a transmission path (not shown). Video # 1 and video # 2 are the same signal at the transmission source, but are assumed to be input via different transmission paths of the active transmission line and the backup transmission line, and the delay characteristics of the transmission line And are input at different timings due to differences in jitter characteristics (see, for example, Patent Document 1).

  Further, the transmission path is, for example, an IP (Internet Protocol) network or the like, and a timing signal serving as a timing reference is superimposed on a packet basis such as an RTP (Real Time Transport Protocol) time stamp at the transmission source. Assumed.

  The input video # 1 extracts a time stamp superimposed on the signal by the time stamp extraction unit 31, and the extracted time stamp is input to the clock generation unit 32 and the buffer control unit 33, and the original video signal Is input to the buffer unit 34.

  The clock generation unit 32 generates a clock signal using the time stamp extracted from the video # 1, and the clock signal is input to the buffer unit 34 and used as a read-out clock of the video signal. It is also input to the control unit 33 and used to generate a buffer read control signal.

  Further, the buffer control unit 33 detects the phase difference between the video # 1 and the video # 2 using the time stamp extracted from the video # 1 and the phase information from the buffer control unit 38 for the video # 2, and the buffer control unit 33 A read control signal for the unit 34 is generated. The buffer read control signal is input to the buffer unit 34 and used for controlling the read timing of the video signal. The buffer control unit 33 also performs a process of outputting the phase information of the video # 1 to the buffer control unit 38 for the video # 2. The signal read from the buffer unit 34 is input to the switching unit 35.

  On the other hand, the input video # 2 is also subjected to time stamp extraction processing by the time stamp extraction unit 36, clock generation processing by the clock generation unit 37, and buffering by the buffer control unit 38 in the same manner as the video # 1. The read control signal generation process and the buffering process in the buffer unit 39 are performed, and the signal read from the buffer unit 39 is input to the switching unit 35.

  The switching unit 35 selects either the video # 1 side or the video # 2 side according to a selection control signal input from the outside, and outputs it as an output video.

JP 2008-193145 A

  In the video signal switching device related to the present invention described above, since the clock is generated individually for each input, strictly the same clock is caused by the difference in jitter characteristics and delay characteristics on the transmission path of each signal. Is not generated, and the signal read from the buffer is switched at the different clock.

  Therefore, the video signal switching device related to the present invention has a problem that the output video after switching is not completely shockless. As a result, the output signal characteristics after switching are deteriorated, and the signal standard may not be satisfied, or the subsequent apparatus may be affected. In addition, the video signal switching device related to the present invention requires a clock generation circuit for each input video, and thus there is a problem that costs are increased.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a video signal switching device and a video signal switching method used therefor that can solve the above-mentioned problems and make the output video after switching shockless.

The video signal switching device according to the present invention extracts first and second time stamps that are preliminarily superimposed on a first video signal and a second video signal input from different transmission paths. Extraction means;
Clock generating means for generating a clock common to each of the first and second video signals based on the first and second time stamps extracted by the first and second extracting means,
First and second replacement means for replacing each of the first and second video signals with a clock generated by the clock generation means;
Switching means for switching and outputting the outputs from the first and second transfer means according to an external instruction.

In the video signal switching method according to the present invention, the video signal switching device includes:
First and second extraction processes for extracting first and second time stamps preliminarily superimposed on each of the first and second video signals input from different transmission paths;
A clock generation process for generating a clock common to each of the first and second video signals based on the first and second time stamps extracted in each of the first and second extraction processes;
First and second replacement processing for replacing each of the first and second video signals with the clock generated by the clock generation processing;
A switching process for switching and outputting the outputs from the first and second transfer processes according to an external instruction is performed.

  The present invention has an effect that the output video after switching can be made shockless by adopting the above-described configuration and operation.

It is a block diagram which shows the structural example of the video signal switching apparatus by the 1st Embodiment of this invention. FIG. 2 is a block diagram illustrating a configuration example of a clock generation unit illustrated in FIG. 1. It is a figure which shows the video signal in the transmission source used for the 1st Embodiment of this invention. It is a figure which shows video signal # 1, # 2 at the receiving side used for the 1st Embodiment of this invention. FIG. 5 is a block diagram showing a configuration example of the buffer control unit shown in FIG. It is a figure which plots the log | history of the phase with respect to the reference phase of time stamp # 1 and time stamp # 2 in the 1st Embodiment of this invention, and shows it as a phase fluctuation. It is a block diagram which shows the structural example of the video signal switching apparatus by the 2nd Embodiment of this invention. FIG. 8 is a block diagram illustrating a configuration example of a clock generation unit illustrated in FIG. 7. It is a block diagram which shows the structural example of the video signal switching apparatus relevant to this invention.

  Next, embodiments of the present invention will be described with reference to the drawings. First, an outline of a video signal switching device according to the present invention will be described.

  The video signal switching device according to the present invention performs not only phase alignment of video signals but also clock synchronization when switching video signals input from two different transmission paths such as an active system and a standby system. This enables shockless switching.

  In other words, the video signal switching device according to the present invention preliminarily receives signals from two video signals (video # 1, video # 2) input from the active transmission line and the standby transmission line at the clock generation unit. A clock common to the active system and the standby system is generated using the time stamp superimposed on the video signal, and switching processing is performed after each of the two video signals is replaced with the clock. As a result, the video signal switching device according to the present invention eliminates the discontinuity of the clock due to switching, and enables shockless switching processing.

  FIG. 1 is a block diagram showing a configuration example of a video signal switching device according to the first embodiment of the present invention. In FIG. 1, the video signal switching device 1 includes time stamp extraction units 11 and 12, a clock generation unit 13, buffer units 14 and 15, a switching unit 16, and a buffer control unit 17.

  Two video signals (video # 1 and video # 2) are input to the video signal switching device 1 from an unillustrated working transmission line and a standby transmission line. Video # 1 and video # 2 are the same signal at the source, but are assumed to be input via different transmission paths of the active transmission line and the standby transmission line. Input is made at different timings due to differences in delay characteristics and jitter characteristics.

  The active transmission line and the standby transmission line are, for example, an IP (Internet Protocol) network or the like, and a timing signal serving as a timing reference in units of packets, such as an RTP (Real Time Transport Protocol) time stamp at the transmission source. Is assumed to be superimposed.

  The video signal switching device 1 extracts the time stamps superimposed on the signals of the video # 1 and the video # 2 input by the time stamp extraction units 11 and 2, and extracts the extracted time stamps from the clock generation unit 13 and The data is input to the buffer control unit 17 and the original video signal is input to the buffer units 14 and 15, respectively.

  The clock generation unit 13 generates a clock signal common to the video # 1 and the video # 2 using the time stamps extracted from the video # 1 and the video # 2, respectively, and the clock signal is stored in the buffer units 14 and 15. This is input and used as a video signal read-side clock, and is also input to the buffer control unit 17 to generate a buffer read control signal.

  Further, the buffer control unit 17 detects the phase difference between the video # 1 and the video # 2 using the time stamps extracted from the video # 1 and the video # 2, and outputs the read control signals of the buffer units 14 and 15, respectively. The buffer read control signals are input to the buffer units 14 and 15 and used to control the video signal read timing.

  In this manner, the video signals whose output phase and clock are the same are read from the buffer units 14 and 15 and input to the switching unit 16, respectively. The switching unit 16 selects the video # 1 side or the video # 2 side according to a selection control signal input from the outside. At that time, the switching unit 16 can perform shockless switching because the phase of the two input signals and the clock match.

  FIG. 2 is a block diagram showing a configuration example of the clock generator 13 shown in FIG. In FIG. 2, the clock generation unit 13 includes frequency extraction units 131 and 132, a frequency setting unit 133, and a clock transmission unit 134.

  The time stamps # 1 and # 2 input to the clock generation unit 13 are input to the frequency extraction units 131 and 132, respectively. The frequency extraction units 131 and 132 extract frequency information to be generated from the time stamps # 1 and # 2. The frequency extraction units 131 and 132 input the extracted frequency information to the frequency setting unit 133.

  The frequency setting unit 133 uses the two frequency information input from the frequency extraction units 131 and 132 to set a frequency suitable as a common clock. The frequency setting unit 133 outputs the set frequency information to the clock oscillation unit 134. The clock oscillating unit 134 oscillates a clock having a frequency set by the frequency setting unit 133 and outputs it as an output clock.

  FIG. 3 is a diagram showing a video signal at the transmission source used in the first embodiment of the present invention, and FIG. 4 is a video signal # 1 on the receiving side used in the first embodiment of the present invention. , # 2. With reference to these FIG. 3 and FIG. 4, the operation example in the frequency extraction parts 131 and 132 and the frequency setting part 133 is demonstrated.

  Each video signal # 1 and # 2 is packetized as described above, and a time stamp is superimposed on a packet basis. As shown in FIG. 3, since processing is performed with a clock having a stable frequency at the transmission source, the packets “A”, “B”, “C”, and “D” are equally spaced, The difference value between the superimposed time stamps is also constant.

  However, the packets of the video signals # 1 and # 2 input through different transmission paths are “A1” and “A2”, “B1” and “B2”, “C1” and “C2” in FIG. As in “D1” and “D2”, the respective phases and intervals may be shifted.

  This is because the video signal # 1 and the video signal # 2 have different delay characteristics and jitter characteristics of the transmission paths through which the video signal # 1 and the video signal # 2 respectively pass. Therefore, the phases of “A1” and “A2”, which should be in the same phase, are different, and the same value is superimposed on the time stamps of the A1 packet and the A2 packet. Similarly, “B1” and “B2”, “C1” and “C2”, and “D1” and “D2” are out of phase, but time stamps of the same value are superimposed on each other.

The frequency extraction units 131 and 132 in FIG. 2 perform frequency extraction from the interval of each packet and the difference between the time stamps.
It can be obtained by the following equation: frequency = time stamp difference value / packet interval time.

For example, the difference value (TB1-TA1) between the time stamp TA1 superimposed on the A1 packet in FIG. 4 and the time stamp TB1 superimposed on the B1 packet is 10000, and the interval between the A1 packet and the B1 packet is 370. Assuming 37 microseconds,
Frequency = 10000 / 0.00037037 seconds
≒ 27.0MHz
It becomes.

  However, in practice, as shown in FIG. 4, since the interval between packets becomes wider or narrower, the frequency becomes smaller, becomes larger, or fluctuates, and time stamp # 1 and time stamp # As for the frequency extracted from each of the two, different frequencies are extracted. Therefore, in the frequency setting unit 131 in FIG. 2, for example, an average value of both frequencies is calculated, and the calculation result is determined as a common frequency.

  FIG. 5 is a block diagram showing a configuration example of the buffer control unit 17 shown in FIG. In FIG. 5, the buffer control unit 17 includes phase extraction units 171, 172, fluctuation range analysis units 173, 174, a phase difference calculation unit 175, read control units 176, 177, and a reference phase generation unit 178. Has been.

  In the buffer control unit 17, the input time stamps # 1 and # 2 are input to the phase extraction units 171 and 172, respectively. Further, the reference phase generation unit 178 generates a reference phase signal that is counted up by a stable clock, and outputs the reference phase signal to the phase extraction units 171 and 172.

  The phase extraction units 171 and 172 measure the phase with respect to the reference phase using the reference phase signal and the packet intervals of the time stamps # 1 and # 2, respectively. The phase extraction units 171 and 172 output the measured phase with respect to the reference phase to the fluctuation width analysis units 173 and 174.

  The fluctuation width analysis units 173 and 174 take the phase history with respect to the reference phase measured by the phase extraction units 171 and 172, and output the phase history to the phase difference calculation unit 175. The phase difference calculation unit 175 determines the phases of the videos # 1 and # 2 using the history from the fluctuation range analysis units 173 and 174, and calculates the phase difference between them. The phase difference calculation unit 175 outputs the calculated phase differences between the videos # 1 and # 2 to the read control units 176 and 177, respectively.

  Read control units 176 and 177 use read phase control information # 1 and # 2 for controlling the read timing of the buffer units 14 and 15 in FIG. Generate and output each.

  FIG. 6 is a diagram showing the phase history as a phase variation by plotting the phase history with respect to the reference phase of the time stamp # 1 and the time stamp # 2 in the first embodiment of the present invention. An operation example of the fluctuation range analysis units 173 and 174 and the phase difference calculation unit 175 will be described with reference to FIG.

  In FIG. 6, the history of the phase with respect to the reference phase of the time stamp # 1 and the time stamp # 2 is plotted, and is shown as the phase variation. Since the images # 1 and # 2 are input via transmission lines having different jitter characteristics, the phase with respect to the reference phase is not fixed and has a width as shown in FIG.

  In general, jitter has a lead or delay with respect to the original phase that changes with time, and the lead amount and the delay amount are considered to be equal. Therefore, it can be said that the center of the plotted phase fluctuation is the original phase. . Therefore, the difference value between the center values of the phase fluctuations of the time stamps # 1 and # 2 is the phase difference between the videos # 1 and # 2.

  In the present embodiment, the readout control signal is generated using the phase difference calculated as described above. For example, when video # 1 is advanced by time P from video # 2, the signal of video # 1 is By reading out with a delay of time P from the video # 2, the output phases of the buffer units 14 and 15 in FIG. 1 can be made uniform.

  Thus, in the present embodiment, for example, when switching from the active transmission line to the standby transmission line becomes necessary due to maintenance of the transmission line, the switching is shockless, which affects the service. Switching and maintenance can be performed without any problems. Therefore, in this embodiment, the availability of operation in the transmission system can be increased.

  In the present embodiment, as described above, the common clock generation unit 13 and buffer control unit 17 are used for the videos # 1 and # 2, so that one clock generation unit and one buffer control unit are used. Since the circuit scale can be reduced, the cost of the apparatus can be reduced.

  FIG. 7 is a block diagram showing a configuration example of a video signal switching device according to the second embodiment of the present invention. In FIG. 7, the video signal switching device 2 includes time stamp extraction units 11 and 12, a clock generation unit 23, buffer units 21 and 22, a switching unit 16, and a buffer control unit 17.

  In the first embodiment of the present invention shown in FIG. 1, the clock is generated only from the input time stamp value, but it is generated depending on the state of the received video signal, that is, the jitter or error on the transmission path. There is a possibility that a deviation from the transmission side occurs in the clock. Therefore, in the second embodiment of the present invention, even when such a shift occurs, it is possible to maintain the continuity of the video signal and perform stable switching processing without breaking the buffer.

  In FIG. 7, the operations of the time stamp extraction units 11 and 12, the switching unit 16, and the buffer control unit 17 are the same as those shown in FIG.

  In the buffer units 21 and 22, an input video signal is written, and data is read according to control from the buffer control unit 17 with a clock output from the clock generation unit 23. At the same time, the buffer units 21 and 22 output the respective buffer accumulated data amounts to the clock generation unit 23.

  The clock generator 23 generates a clock according to the input time stamp. At that time, the clock generation unit 23 generates a frequency-corrected clock from the buffer accumulated data amount from the buffer units 21 and 22 so that the respective buffers do not overflow or underflow.

  As described above, in the present embodiment, the clock generator 23 generates the clock as described above, so that even if the input time stamp value is affected by jitter or error on the transmission path, the buffer It is possible to perform stable switching without causing failure.

  FIG. 8 is a block diagram showing a configuration example of the clock generator 23 shown in FIG. In FIG. 8, the clock generation unit 23 includes frequency extraction units 131 and 132, a frequency setting unit 231, a clock transmission unit 134, and a correction frequency calculation unit 232. In FIG. 8, the operations of the frequency extraction units 131 and 132 and the clock oscillation unit 134 are the same as those of the first embodiment of the present invention shown in FIG.

  In the clock generation unit 23, both the buffer accumulated data amounts output from the buffer units 21 and 22 are input to the correction frequency calculation unit 232. The correction frequency calculation unit 232 checks the amount of data stored in the two buffers from the buffer units 21 and 22, generates a frequency correction control signal, and outputs it to the frequency setting unit 231.

  That is, in the correction frequency calculation unit 232, when the input buffer amount is increasing, the control signal for correcting the frequency to the higher side is output to the frequency setting unit 231 and set from the time stamp. Set the clock frequency higher than the frequency. As a result, in the present embodiment, the read clock from the buffer units 21 and 22 is increased, the read speed is increased, and the buffer accumulated data amount can be reduced.

  On the contrary, in the correction frequency calculation unit 232, when the input buffer amount is reduced, the control signal for correcting the frequency to the lower side is output to the frequency setting unit 231 and set from the time stamp. Set a clock frequency lower than the specified frequency. As a result, in the present embodiment, the read clock from the buffer units 21 and 22 is lowered, the read speed is reduced, and the buffer accumulated data amount can be increased.

  As described above, in this embodiment, even when the clock generation from only the time stamp is shifted due to the influence of jitter or error on the transmission path, the two clocks can always be kept the same, As a result, switching without shock can be realized.

  1 and 7, the signal input from the transmission path is described as a video signal. However, this signal need not be limited to an uncompressed video signal, and even in the case of a compressed video signal, It can be applied in the same way.

1, 2 Video signal switching device
11, 12 Time stamp extractor
13, 23 Clock generation unit 14, 15, 21, 22 Buffer unit
16 switching part
17 Buffer controller
131, 132 Frequency extraction unit
133,231 Frequency setting part
134 Clock transmitter
171 and 172 Phase extractor
173,174 Variation range analysis section
175 Phase difference calculation unit
176, 177 Read controller
178 Reference phase generator

Claims (8)

First and second extraction means for extracting first and second time stamps preliminarily superimposed on each of the first and second video signals input from different transmission paths;
Clock generating means for generating a clock common to each of the first and second video signals based on the first and second time stamps extracted by the first and second extracting means,
First and second replacement means for replacing each of the first and second video signals with a clock generated by the clock generation means;
A video signal switching device comprising: switching means for switching and outputting the outputs from the first and second transfer means according to an external instruction.   The clock generation means includes first and second frequency extraction means for extracting first and second frequency information to be generated from each of the first and second time stamps, and the first and second frequencies. 2. A frequency setting means for calculating an average value of frequencies from the first and second frequency information extracted by the extraction means and determining the calculation result as a common frequency. Video signal switching device.   The first and second transposing means are first and second buffers for holding the first and second video signals, respectively, and the first and second buffers based on a clock generated by the clock generating means. Buffer control means for controlling writing of each of the second video signals to the first and second buffers and reading of the first and second video signals from the first and second buffers; 3. The video signal switching device according to claim 1, further comprising a video signal switching device. Feedback the amount of data stored in each of the first and second buffers to the clock generation means;
The clock generation means is configured to output the first and second time stamps based on the first and second time stamps extracted by the first and second extraction means and the accumulated data amounts of the first and second buffers, respectively. 4. The video signal switching device according to claim 3, wherein a clock common to each of the second video signals is generated. Video signal switching device
First and second extraction processes for extracting first and second time stamps preliminarily superimposed on each of the first and second video signals input from different transmission paths;
A clock generation process for generating a clock common to each of the first and second video signals based on the first and second time stamps extracted in each of the first and second extraction processes;
First and second replacement processing for replacing each of the first and second video signals with the clock generated by the clock generation processing;
A video signal switching method comprising: executing a switching process of switching and outputting the outputs from the first and second transfer processes according to an external instruction.   In the clock generation process, first and second frequency information to be generated from each of the first and second time stamps is extracted, and an average value of the frequencies is obtained from the extracted first and second frequency information. 6. The video signal switching method according to claim 5, wherein the calculation result is determined as a common frequency. The video signal switching device is provided with first and second buffers for holding the first and second video signals,
In the first and second transfer processes, the writing of the first and second video signals to the first and second buffers and the first based on the clock generated in the clock generation process. 7. The video signal switching method according to claim 5 or 6, further comprising controlling reading from the first and second buffers of each of the first and second video signals. The amount of accumulated data in each of the first and second buffers is fed back to the clock generation process,
In the clock generation process, the first and second time stamps extracted in each of the first and second extraction processes and the accumulated data amounts of the first and second buffers are used. 8. The video signal switching method according to claim 7, wherein a clock common to each of the second video signals is generated.

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