JP2008022432A - Signal transmitting/receiving apparatus and communication synchronism control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal transmitting/receiving apparatus in which received signals are hardly accumulated in a buffer too much or signals are hardly lacked in the buffer. <P>SOLUTION: A clock part 8 outputs a transmitting clock and a receiving clock to an analog interface part 6. The analog interface part 6 converts an analog audio signal sent from a telephone set 7 into a digital audio signal and stores it in a transmitting buffer 53 in the timing when the transmitting clock is output from the clock part 8. Furthermore, a jitter buffer control part 3 causes a receiving jitter buffer 52 to store an IP frame that becomes an audio signal to be sent to the telephone set 7. A timing generating part 33 monitors the amount of audio signals stored in the receiving jitter buffer 52 and controls an output cycle of the transmitting clock or the receiving clock of the clock part 8 in accordance with the amount of audio signals stored in the receiving jitter buffer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a signal transmission / reception apparatus that transmits and receives signals and a communication synchronization control method that is applied to a signal transmission and reception apparatus that transmits and receives signals.

  A system is known in which VoIP (Voice Over IP) devices are connected to each other, and VoIP devices transmit and receive audio signals. Each VoIP device operates according to an independent clock. That is, a VoIP device with a fast clock and a VoIP device with a slow clock may transmit and receive audio signals.

  Patent Document 1 describes a data reception / playback apparatus. The data reception / playback apparatus described in Patent Document 1 has a remaining amount measuring circuit that measures the remaining amount of the reception buffer, and a remaining amount of the reception buffer that is available based on the measurement value of the remaining amount measurement circuit. A clock frequency determining circuit for determining a read timing of the buffer read control circuit so as to be within a predetermined range.

JP-A-9-261613 (paragraph 0014)

  When a VoIP device with a fast clock and a VoIP device with a slow clock transmit and receive audio signals, the received audio signals may increase excessively or the received audio signals may be lost due to clock differences. May occur. For example, it is assumed that an audio signal is transmitted from a VoIP device with a fast clock to a VoIP device with a slow clock. At this time, in a VoIP device with a slow clock, the reproduction of the received audio signal does not depend on the amount of the audio signal transmitted. Therefore, in the buffer that accumulates the received audio signal, the audio signal is sequentially accumulated, and the accumulation amount of the audio signal becomes excessive. Since the buffer capacity is finite, the received audio signal must be discarded as the amount of accumulated audio signal increases. Further, for example, it is assumed that an audio signal is transmitted from a VoIP device with a slow clock to a VoIP device with a fast clock. In a VoIP device with a fast clock, since the playback speed of the received audio signal is high, the audio signal is not stored in the buffer for storing the received audio signal. That is, the audio signal to be reproduced is insufficient and the audio signal is lost.

  If the received audio signal increases excessively, the received audio signal does not fit in the buffer and must be discarded. In addition, when the received signal arrives late, the sound signal to be reproduced is insufficient and the sound signal is lost, and the sound is interrupted.

  Here, the case where voice signals are transmitted and received between VoIP devices has been shown, but the same problem occurs when a device other than a VoIP device transmits and receives signals other than voice signals (for example, image signals). In particular, in facsimile communication and data communication, if the received signal is discarded without being stored in the buffer, or if the received signal is not accumulated in the buffer because the arrival of the next received signal is late, the call may be disconnected. .

  In addition, it is preferable to be able to notify the counterpart device that transmits and receives signals that the received signal has increased excessively or that the signal has been lost.

  Therefore, the present invention can make it difficult for the received signal to be accumulated excessively in the buffer, to make it difficult for the buffer to lack a signal, and to cause an excessive accumulation of the signal in the buffer and a shortage of signal. It is an object of the present invention to provide a signal transmission / reception device capable of notifying the device of the transmission partner when this occurs and a communication synchronization control method applied to the signal transmission / reception device.

  The signal transmission / reception apparatus according to the present invention includes a reception signal storage means (for example, reception jitter buffer 52) for temporarily storing a signal received from a communication network, and a signal storage for storing a signal received from the communication network in a reception signal storage means. Control means (for example, CPU 4), transmission signal storage means (for example, transmission buffer 53) for temporarily storing signals to be transmitted to the communication network, first clock signal (for example, reception clock signal), and second Clock signal output means (for example, clock unit 8) for outputting a clock signal (for example, transmission clock signal) and stored in the reception signal storage means when the clock signal output means outputs the first clock signal Received signal reading means (for example, analog interface unit 6) for reading a signal, and clock signal When the output means outputs the second clock signal, the transmission signal writing means (for example, the analog interface unit 6) stores the signal to be transmitted to the communication network in the transmission signal storage means, and the reception signal storage means stores the signal. When the state in which the signal amount is smaller than the threshold value continues, the signal output period of the first clock signal of the clock signal output means is delayed, the signal output period of the second clock signal is increased, and the received signal storage means When the state in which the amount of the signal stored in the signal is greater than the threshold value continues, the clock signal output means speeds up the signal output cycle of the first clock signal and delays the signal output cycle of the second clock signal. Period control means (for example, timing generation unit 33) is provided.

  A signal transmission unit (for example, CPU 4) that transmits the signal stored in the transmission signal storage unit to the communication network is provided, and the signal transmission unit transmits the signal as the amount of the signal stored in the transmission signal storage unit increases. As the transmission period for transmitting the signal stored in the signal storage means to the communication network is increased, and the amount of the signal stored in the transmission signal storage means decreases, the signal stored in the transmission signal storage means is communicated. The structure which makes the transmission period transmitted to a network late may be sufficient. According to such a configuration, it is possible to notify the counterpart device that the received signal has increased excessively or that the signal has been lost.

  When it is determined that the signal received from the communication network is missing, the signal loss judging means (for example, the packet loss detection unit 32) for judging whether or not the signal received from the communication network is missing. A configuration may be provided that includes complementing means (for example, the packet loss detection unit 32) that generates a signal from a signal that has already been received.

  The communication synchronization control method according to the present invention includes a reception signal storage means (for example, reception jitter buffer 52) for temporarily storing a signal received from a communication network, and a transmission signal storage for temporarily storing a signal to be transmitted to the communication network. A communication synchronization control method using a means (for example, transmission buffer 53), wherein a signal storage control means (for example, CPU 4) stores a signal received from a communication network in a reception signal storage means, and a clock signal output means (For example, the clock unit 8) outputs a first clock signal (for example, reception clock signal) and a second clock signal (for example, transmission clock signal), and receives signal reading means (for example, the analog interface unit 6). Is stored in the received signal storage means when the clock signal output means outputs the first clock signal. The transmission signal storage means stores the signal to be transmitted to the communication network when the clock signal output means outputs the second clock signal when the transmission signal writing means (for example, the analog interface unit 6) outputs the second clock signal. When the clock cycle control means (for example, the timing generation unit 33) continues to be in a state where the amount of the signal stored in the received signal storage means is smaller than the threshold, the output of the first clock signal of the clock signal output means When the cycle is delayed, the signal output cycle of the second clock signal is increased, and the amount of the signal stored in the received signal storage means continues to be greater than the threshold, the first clock of the clock signal output means The signal output cycle of the signal is made faster and the signal output cycle of the second clock signal is made slower.

  As the amount of the signal stored in the transmission signal storage means increases, the signal transmission means (for example, the CPU 4) increases the transmission cycle for transmitting the signal stored in the transmission signal storage means to the communication network, and transmits the signal. As the amount of the signal stored in the signal storage unit decreases, a method of delaying the transmission cycle for transmitting the signal stored in the transmission signal storage unit to the communication network may be used. According to such a method, it is possible to notify the counterpart device that the received signal has increased excessively or that the signal has been lost.

  The signal loss determination means (for example, the packet loss detection unit 32) determines whether or not the signal received from the communication network is missing, and the complement means (for example, the packet loss detection unit 32) receives from the communication network. When it is determined that a missing signal has occurred, a method of generating a signal from an already received signal may be used.

  According to the present invention, it is possible to make it difficult for received signals to be accumulated excessively in the received signal storage means, or to make it difficult for a shortage of signals to occur in the received signal storage means.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of a signal transmitting / receiving apparatus according to the present invention. In the following description, a case where the signal transmitting / receiving apparatus implements the VoIP function will be described as an example. That is, the case where the signal transmitting / receiving apparatus transmits and receives an audio signal by VoIP will be described as an example. The signal transmission / reception device 1 is connected to a telephone set 7 and is connected to another signal transmission / reception device via a communication network (not shown. In the present example, the case of the Internet or WAN will be described as an example). Here, a case where signal transmitting / receiving apparatuses having the same configuration are connected via a communication network will be described as an example. The signal transmission / reception apparatus 1 connected via a communication network transmits and receives audio signals in both directions.

  The signal transmitting / receiving apparatus 1 includes a WAN side interface unit 2, a jitter buffer control unit 3, a memory unit 5, an analog interface unit 6, and a clock unit 8.

  The WAN-side interface unit 2 is an interface unit with a communication network (for example, the Internet or WAN).

  The jitter buffer control unit 3 performs detection, omission control, and control of the clock unit 8 of the audio signal received from the signal transmission / reception apparatus of the communication partner via the WAN side interface unit 2. The jitter buffer control unit 3 includes a packet detection unit 31, a packet loss detection unit 32, and a timing generation unit 33.

  The packet detector 31 detects a packet that is an audio signal to be sent to the telephone set 7. That is, the packet detection unit 31 determines whether or not the packet received via the WAN side interface unit 2 is a packet that becomes a voice signal to be transmitted to the telephone set 7. If the received packet is a packet transmitted as an audio signal, the packet detection unit 31 determines that the packet is a packet that becomes an audio signal to be sent to the telephone 7, and the received packet is transmitted as an audio signal. If the packet is not a packet, it is determined that the packet is not a packet that becomes a voice signal to be transmitted to the telephone set 7. Assume that signal transmission / reception devices transmit and receive IP frames. An IP frame is a signal that flows on the Internet. In this case, if the received IP frame is an IP frame transmitted as a voice signal, the packet detection unit 31 determines that the IP frame is an IP frame to be a voice signal to be sent to the telephone set 7 and receives the IP frame. If the IP frame is not an IP frame transmitted as a voice signal, it is determined that the IP frame is not an IP frame serving as a voice signal transmitted to the telephone set 7.

  The packet loss detection unit 32 detects the loss of a packet received via the WAN side interface unit 2. The following two modes can be cited as packet loss modes. The first aspect is packet loss on the communication network. The second mode is that a packet received at the WAN side interface unit 2 is lost although the packet has normally arrived at the WAN side interface unit 2 from the communication network. It should be noted that there are very few omissions in the second aspect, and there are many omissions in the first aspect.

  The packet loss detection unit 32 indicates a sequence number indicating the order of data (in this case, the order of audio signals) given to each packet (packet that becomes an audio signal transmitted to the telephone 7) detected by the packet detection unit 31. To detect. The packet loss detection unit 32 determines that no packet loss has occurred if the sequence numbers are continuous, and determines that a packet loss has occurred if the sequence numbers are not continuous. Assume that signal transmission / reception devices transmit and receive IP frames. In this case, the packet loss detection unit 32 detects a sequence number given to each IP frame detected by the packet detection unit 31. The packet loss detection unit 32 determines that no IP frame is missing if the sequence numbers are continuous, and determines that an IP frame is missing if the sequence numbers are not continuous. To do.

  When the packet loss detection unit 32 determines that there is no omission in a packet that is an audio signal sent to the telephone set 7, the CPU 4 converts the packet that becomes an audio signal sent to the telephone set 7 into a digital audio signal and receives it. The data is stored in the jitter buffer 52.

  When a packet that is an audio signal to be transmitted to the telephone 7 is missing, the packet loss detection unit 32 generates a packet from the packet received via the WAN side interface unit 2. Then, the packet loss detection unit 32 supplements the lost packet with the generated packet. The packet loss detection unit 32 generates a packet by attenuating an audio signal already received via the WAN side interface unit 2, and complements the lost packet by the packet. This technique is called PLC (Packet Loss Concealment).

  The timing generation unit 33 constantly monitors the reception jitter buffer 52 and controls the clock unit 8. If the state in which the amount of the audio signal stored in the reception jitter buffer 52 is larger than the threshold value continues for a predetermined time or longer, the timing generation unit 33 causes the clock unit 8 to delay the output cycle of the transmission clock signal and receive the signal. The output period of the clock signal is increased (in other words, the output frequency of the transmission clock signal is decreased in the clock unit 8 and the output frequency of the reception clock signal is increased). Hereinafter, the transmission clock signal is simply referred to as a transmission clock, and the reception clock signal is simply referred to as a reception clock. If the state where the amount of the audio signal stored in the reception jitter buffer 52 is less than the threshold value continues for a predetermined time or more, the timing generation unit 33 causes the clock unit 8 to make the output cycle of the transmission clock faster, The output period of the reception clock is delayed (in other words, the output frequency of the transmission clock is increased in the clock unit 8 and the output frequency of the reception clock is decreased).

  The analog interface unit 6 converts the audio signal (analog signal) sent from the telephone set 7 into a digital signal according to the transmission clock output from the clock unit 8 and stores it in the transmission buffer 53. Further, the analog interface unit 6 reads out an audio signal (digital signal) stored in the reception jitter buffer 52 according to the reception clock output from the clock unit 8, converts it into an analog signal, and sends it to the telephone set 7.

  Therefore, if the timing generation unit 33 increases the output period of the transmission clock from the clock unit 8, the period for storing the audio signal in the transmission buffer 53 is also increased. Further, as will be described later, the CPU 4 monitors the amount of the audio signal stored in the transmission buffer 53, and increases from the transmission buffer 53 to the WAN side interface as the amount of the audio signal stored in the transmission buffer 53 increases. The operation of transmitting a packet to the signal transmission / reception apparatus of the communication partner via the unit 2 is accelerated (that is, the packet transmission cycle is increased). Therefore, if the output period of the transmission clock from the clock unit 8 is accelerated, the operation of transmitting a packet from the transmission buffer 53 to the signal transmission / reception apparatus of the communication partner via the WAN side interface unit 2 can be accelerated. If the timing generation unit 33 delays the output period of the reception clock from the clock unit 8, the operation of converting the audio signal stored in the reception jitter buffer 52 into an analog signal and sending it to the telephone 7 is delayed. be able to. When the amount of the audio signal stored in the reception jitter buffer 52 is small, the timing generation unit 33 causes the clock unit 8 to increase the output period of the transmission clock, and accelerates the operation of storing the audio signal in the transmission buffer 53. In addition, the output period of the reception clock is delayed in the clock unit 8, and the operation of converting the audio signal stored in the reception jitter buffer 52 into an analog signal and sending it to the telephone 7 is delayed.

  Similarly, if the timing generation unit 33 delays the output cycle of the transmission clock from the clock unit 8, the cycle in which the audio signal is stored in the transmission buffer 53 is also delayed. Then, the CPU 4 monitors the amount of the audio signal stored in the transmission buffer 53, and from the transmission buffer 53 via the WAN side interface unit 2 as the amount of the audio signal stored in the transmission buffer 53 increases. Speeds up the operation of transmitting packets to the signal transmission / reception device of the communication partner. That is, if the amount of the audio signal stored in the transmission buffer 53 decreases, the operation of transmitting a packet from the transmission buffer 53 to the signal transmission / reception apparatus of the communication partner via the WAN side interface unit 2 is delayed (packet transmission). Slow down the cycle). Therefore, if the output cycle of the transmission clock from the clock unit 8 is delayed, the cycle of transmitting packets from the transmission buffer 53 to the signal transmission / reception device of the communication partner via the WAN side interface unit 2 can also be delayed. In addition, if the timing generation unit 33 increases the output period of the reception clock from the clock unit 8, the operation of converting the audio signal stored in the reception jitter buffer 52 into an analog signal and sending it to the telephone 7 is accelerated. be able to. When the amount of the audio signal stored in the reception jitter buffer 52 is large, the timing generation unit 33 delays the output period of the transmission clock in the clock unit 8 and delays the operation of storing the audio signal in the transmission buffer 53, Further, the clock unit 8 is made to increase the output period of the reception clock so that the voice signal stored in the reception jitter buffer 52 is converted into an analog signal and sent to the telephone 7.

  In this way, the timing generation unit 33 increases or decreases the output cycle of the reception clock from the clock unit 8 and the output cycle of the transmission clock, so that the audio stored in the reception jitter buffer 52 and the transmission buffer 53 is obtained. Adjust the amount of signal.

  The CPU 4 performs packetization of the digital audio signal (IP frame) and processing for converting the audio signal received as a packet into a digital signal. Further, the CPU 4 monitors the amount of the audio signal stored in the transmission buffer 53, and from the transmission buffer 53 through the WAN side interface unit 2 as the amount of the audio signal stored in the transmission buffer 53 increases. Speeds up the operation of transmitting packets to the signal transmission / reception device of the communication partner. As the amount of audio signal stored in the transmission buffer 53 decreases, the CPU 4 delays the operation of transmitting a packet from the transmission buffer 53 to the signal transmission / reception apparatus of the communication partner via the WAN side interface unit 2.

  When the timing generation unit 33 speeds up the output cycle of the transmission clock from the clock unit 8, the amount of audio signals stored in the transmission buffer 53 increases, and as a result, the CPU 4 moves the WAN side interface unit 2 from the transmission buffer 53. Speeds up the operation of transmitting packets to the signal transmission / reception apparatus of the communication partner. Further, when the timing generation unit 33 delays the output period of the transmission clock from the clock unit 8, the amount of the audio signal stored in the transmission buffer 53 decreases, and as a result, the CPU 4 changes the WAN side interface from the transmission buffer 53. The operation of transmitting a packet to the signal transmission / reception apparatus of the communication partner via the unit 2 is delayed.

  The memory unit 5 temporarily stores audio signals. The memory unit 5 includes an internal memory 51, a reception jitter buffer 52, and a transmission buffer 53. The internal memory 51 is a memory used when the CPU 4 packetizes a digitized audio signal (IP frame).

  The reception jitter buffer 52 is a buffer that temporarily accumulates audio signals received from the WAN via the WAN side interface unit 2 until the analog interface unit 6 reads the audio signal. The reception jitter buffer 52 absorbs variations in arrival time of voice signals received from the WAN via the WAN side interface unit 2, that is, jitter.

  The transmission buffer 53 is a buffer that temporarily stores an audio signal received from the telephone set 7 via the analog interface unit 6. The audio signal stored in the transmission buffer 53 is transmitted to the counterpart device via the communication network.

  The analog interface unit 6 is an interface with the telephone 7. The analog interface unit 6 encodes (converts to a digital signal) the analog audio signal received from the telephone set 7 in accordance with the transmission clock output from the clock unit 8 and stores it in the transmission buffer 53. Further, the analog interface unit 6 reads out the digital audio signal stored in the reception jitter buffer 52 according to the reception clock output from the clock unit 8, decodes (converts it into an analog signal), and sends it to the telephone 7.

  The clock unit 8 outputs a transmission clock for encoding the analog audio signal from the telephone set 7 in the analog interface unit 6 and storing it in the transmission buffer 53. The clock unit 8 also outputs a reception clock that causes the analog interface unit 6 to read out and decode the digital audio signal stored in the reception jitter buffer 52 and send it to the telephone set 7. The clock unit 8 increases or decreases the output cycle of the transmission clock and the output cycle of the reception clock according to the control of the timing generation unit 33.

  Note that the audio signal transmitted and received between the telephone set 7 and the analog interface unit 6 is an analog signal. The telephone 7 transmits an analog audio signal to the analog interface unit 6. The analog interface unit 6 converts the analog audio signal into a digital audio signal and stores it in the transmission buffer 53. The digital audio signal stored in the transmission buffer 53 is packetized (IP frame) by the CPU 4 and transmitted to the communication network via the WAN side interface unit 2.

  Further, the CPU 4 converts the packet received by the WAN side interface unit 2 from the communication network into a digital audio signal, and stores the digital audio signal in the reception jitter buffer 52. The analog interface unit 6 converts the digital audio signal into an analog audio signal and transmits it to the telephone set 7.

  Next, the operation will be described. In the following description, a case where an audio signal in units of 20 ms is stored in one IP frame and the signal transmitting / receiving apparatuses 1 having the same configuration transmit / receive IP frames via a communication network will be described as an example. In addition, the signal transmission / reception apparatus 1 of this invention does not transmit / receive signals, but the signal transmission / reception apparatus 1 of this invention may transmit / receive a signal with another apparatus.

  First, an operation in which the signal transmitting / receiving apparatus 1 transmits an audio signal to the counterpart signal transmitting / receiving apparatus will be described. The telephone 7 transmits an analog audio signal (analog audio signal) to the analog interface unit 6. The analog interface unit 6 converts the analog audio signal into a digital audio signal in accordance with the timing at which the transmission clock is output from the clock unit 8. The clock unit 8 normally samples the audio signal at 8 kHz.

  The analog interface unit 6 stores the digitized audio signal in the transmission buffer 53. At this time, the analog interface unit 6 stores a predetermined amount of data in the transmission buffer 53 as one unit of data. In general, a signal transmission / reception apparatus having a VoIP function often stores an audio signal corresponding to 20 ms in a transmission buffer as a unit of data. In this example, the case where the analog interface unit 6 stores a digital audio signal in the transmission buffer 53, for example, stores an audio signal for 20 ms as one unit of data will be described as an example.

  The CPU 4 converts the audio signal stored in the transmission buffer 53 into an IP frame using the internal memory 51. Further, the CPU 4 transmits the IP frame to the signal transmission / reception device on the other side via the WAN side interface unit 2. The CPU 4 monitors the amount of the audio signal stored in the transmission buffer 53, and when the amount of the audio signal is large, speeds up the operation of transmitting the IP frame to the communication network (that is, increases the transmission period of the IP frame). .) In addition, when the amount of the audio signal stored in the transmission buffer 53 is small, the CPU 4 delays the operation of transmitting the IP frame to the communication network (that is, delays the IP frame transmission cycle).

  The CPU 4 adds a sequence number to the IP frame (packet) according to the order of the audio signal when the audio signal stored in the transmission buffer 53 is converted into an IP frame (packetized).

  Next, an operation in which the signal transmission / reception device 1 receives an audio signal from the counterpart signal transmission / reception device will be described. FIG. 2 is a flowchart showing an operation when the signal transmission / reception device 1 receives an audio signal from the counterpart signal transmission / reception device.

  The packet detection unit 31 receives the IP frame transmitted from the signal transmission / reception device on the other side via the WAN side interface unit 2 (step S1).

  Subsequently, the packet detection unit 31 determines whether or not the IP frame received via the WAN side interface unit 2 is an IP frame serving as a voice signal to be transmitted to the telephone 7 (step S2). In step S <b> 2, if the received IP frame is an IP frame transmitted as a voice signal, the packet detection unit 31 determines that the IP frame is an IP frame serving as a voice signal transmitted to the telephone 7. If the received IP frame is not an IP frame transmitted as a voice signal, the packet detection unit 31 determines that the IP frame is not an IP frame serving as a voice signal to be transmitted to the telephone set 7. If the received IP frame is not an IP frame to be a voice signal to be sent to the telephone 7 (No in step S2), the process proceeds to step S1.

  After step S <b> 2, the packet loss detection unit 32 determines whether or not there is a loss in the IP frame that is determined to be an IP frame that is an audio signal transmitted to the telephone 7. If there is no omission (packet loss) in the IP frame, the CPU 4 converts the IP frame, which is an audio signal to be sent to the telephone 7, into a digital audio signal, and stores the digital audio signal in the reception jitter buffer 52 ( Step S3). The packet loss detection unit 32 detects a sequence number given to each IP frame determined to be an IP frame that is a voice signal to be transmitted to the telephone set 7. If the sequence numbers are consecutive, the IP frame is missing. It may be determined that no IP frame has occurred, and if the sequence numbers are consecutive, it may be determined that a lack of IP frames has occurred. It is assumed that the communication partner device adds an order number to the IP frame according to the order of the audio signals and transmits the IP frame to which the order number is added.

  When a loss (packet loss) has occurred in the IP frame, the packet loss detection unit 32 generates a packet by attenuating the voice signal already received via the WAN side interface unit 2, and Complement.

  The CPU 4 converts the IP frame received from the WAN side interface unit 2 into a digital audio signal and stores it in the reception jitter buffer 52.

  In addition, the timing generation unit 33 constantly monitors the reception jitter buffer 52, and the state in which the amount of the audio signal stored in the reception jitter buffer 52 is greater than the threshold continues for a predetermined time or more, or the reception jitter buffer 52 It is determined whether or not the state in which the amount of the audio signal stored in is less than the threshold value continues for a predetermined time (step S4).

  The timing generation unit 33 causes the clock unit 8 to delay the output period of the transmission clock if the state in which the amount of the audio signal stored in the reception jitter buffer 52 is greater than the threshold value continues for a predetermined time or longer, and The clock unit 8 is made to increase the output period of the reception clock (step S5). Further, the timing generation unit 33 causes the clock unit 8 to increase the output period of the transmission clock if the state in which the amount of the audio signal stored in the reception jitter buffer 52 is less than the threshold value continues for a predetermined time or longer, Also, the clock unit 8 delays the output period of the reception clock (step S6).

  The analog interface unit 6 reads the digital audio signal stored in the reception jitter buffer 52 at the timing when the clock unit 8 outputs the reception clock to the analog interface unit 6, converts it into an analog audio signal, and sends it to the telephone 7. (Step S7). Further, the analog interface unit 6 converts the analog audio signal from the telephone 7 into a digital audio signal in accordance with the timing at which the clock unit 8 outputs the transmission clock to the analog interface unit 6, and stores it in the transmission buffer 53.

  The fact that the amount of audio signals stored in the reception jitter buffer 52 continues to be large means that the audio signal transmission cycle of the counterpart signal transmitting / receiving apparatus is fast. In this case, the timing generation unit 33 causes the clock unit 8 to increase the output cycle of the reception clock and to delay the output cycle of the transmission clock. Then, the cycle of reading out the digital audio signal stored in the reception jitter buffer 52, converting it into an analog audio signal and sending it to the telephone 7 becomes faster, and the analog audio signal received from the telephone 7 is converted into a digital audio signal and transmitted. The cycle stored in the buffer 53 is delayed. Further, if the output cycle of the transmission clock is delayed and the analog interface unit 6 stores the audio signal in the transmission buffer 53, the amount of the audio signal accumulated in the transmission buffer 53 is reduced. In this case, the CPU 4 The transmission period of the audio signal to the signal transmission / reception apparatus on the other side is delayed. As a result, synchronization with the signal transmission / reception apparatus on the other side can be achieved. Further, the CPU 4 delays the cycle of sending the audio signal to the other party's signal transmitting / receiving device, and thus the state that the amount of the audio signal stored in the reception jitter buffer 52 continues is large. Can notify the transmission / reception device.

  The fact that the amount of the audio signal stored in the reception jitter buffer 52 continues to be small means that the audio signal transmission cycle of the signal transmission / reception apparatus on the other side is slow. In this case, the timing generation unit 33 causes the clock unit 8 to delay the output cycle of the reception clock and to increase the output cycle of the transmission clock. Then, the cycle of reading out the digital audio signal stored in the reception jitter buffer 52, converting it into an analog audio signal and sending it to the telephone set 7 is delayed, and the analog audio signal received from the telephone set 7 is converted into a digital audio signal and transmitted. The cycle stored in the buffer 53 is faster. Further, when the output cycle of the transmission clock becomes faster and the cycle in which the analog interface unit 6 stores the audio signal in the transmission buffer 53 becomes faster, the amount of the audio signal accumulated in the transmission buffer 53 increases. In this case, the CPU 4 Then, the cycle of sending the audio signal to the signal transmission / reception device on the other side is increased. As a result, synchronization with the signal transmission / reception apparatus on the other side can be achieved. Further, the CPU 4 indicates that the state where the amount of the audio signal stored in the reception jitter buffer 52 continues to be small by increasing the cycle of sending the audio signal to the signal transmission / reception device on the other side. Can notify the transmission / reception device.

  A specific example of clock control is shown below. For example, it is assumed that the reception jitter buffer 52 stores up to three audio signals for 20 ms (3 units, that is, 60 ms). The state in which two audio signals (for 40 ms) are stored in the reception jitter buffer 52 that stores up to three (3 units) audio signals is a preferable state in which the signal transmission / reception apparatus on the other side is synchronized. It is.

  When two-way communication is being performed, a state in which more than two audio signals are stored in the reception jitter buffer 52 that can store up to three audio signals is the state of the audio signal stored in the reception jitter buffer 52. There is a large amount. That this state continues means that the audio signal transmission cycle of the counterpart signal transmitting / receiving apparatus is fast. In this case, the timing generation unit 33 causes the clock unit 8 to delay the output cycle of the transmission clock and increase the output cycle of the reception clock. As a result, it is possible to synchronize with the signal transmission / reception apparatus on the other side.

  When two-way communication is being performed, a state in which less than two audio signals are stored in the reception jitter buffer 52 that can store up to three audio signals indicates that the audio signal stored in the reception jitter buffer 52 The amount is small. That this state continues means that the audio signal transmission cycle of the signal transmission / reception apparatus on the other side is slow. In this case, the timing generation unit 33 causes the clock unit 8 to increase the output cycle of the transmission clock and delay the output cycle of the reception clock. As a result, it is possible to synchronize with the signal transmission / reception apparatus on the other side.

  When signal transmission / reception devices 1 having the same configuration are connected to each other via a communication network, the signal transmission / reception devices 1 performing bidirectional communication can be synchronized with each other. Even if the signal transmission / reception device 1 of the present invention performs bidirectional communication with a device that transmits an audio signal based on a reference clock or performs bidirectional communication with a device with low clock accuracy. The signal transmission / reception apparatus 1 of the invention can be synchronized with the counterpart apparatus.

  According to the present invention, the timing generator 33 monitors the amount of the audio signal stored in the reception jitter buffer 52, and the transmission clock of the clock unit 8 is determined according to the amount of the audio signal stored in the reception jitter buffer 52. And the output cycle of the reception clock are respectively changed. Also, the analog interface unit 6 reads out the audio signal stored in the reception jitter buffer when the clock unit 8 outputs the reception clock to the analog interface unit 6, converts it to an analog signal, and transmits it to the telephone 7. When 8 outputs a transmission clock to the analog interface unit 6, the audio signal received from the telephone 7 is converted into a digital signal and stored in the transmission buffer 53. Therefore, it is possible to synchronize with the device on the other side, and it is possible to make it difficult for the received signal to be accumulated excessively in the reception jitter buffer 52 or to make it difficult for the reception jitter buffer 52 to cause a shortage of signals. When the timing generation unit 33 increases the output period of the transmission clock of the clock unit 8, the transmission period of the audio signal to the counterpart signal transmission / reception device is increased, and the timing generation unit 33 determines the transmission clock of the clock unit 8. When the output cycle is delayed, the cycle of sending the audio signal to the signal transmission / reception device on the other side is delayed. Therefore, by increasing or decreasing the period of sending the audio signal to the signal transmission / reception device on the other side, the amount of the audio signal stored in the reception jitter buffer 52 is increased or decreased. The device can be notified.

  In the present invention, the lost packet is complemented not by the clock unit 8 but by the packet loss detection unit 32. When the missing packet is complemented by the clock unit 8, the transmission clock and the reception clock may not be output at an accurate timing. However, in the present invention, the packet loss detecting unit 32 complements the missing packet. The clock unit 8 can output a transmission clock and a reception clock with accurate timing.

  In the above description, the case where the signal transmission / reception apparatus transmits / receives an audio signal has been described as an example, but an image or data may be transmitted / received. Even when the signal transmission / reception device transmits / receives an image or data to / from the communication partner device, it can be synchronized with the communication partner device.

It is a block diagram which shows one Embodiment of the signal transmission / reception apparatus by this invention. It is a flowchart which shows operation | movement when a signal transmission / reception apparatus receives an audio | voice signal from the signal transmission / reception apparatus of the other party.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Signal transmission / reception apparatus 2 WAN side interface part 3 Jitter buffer control part 4 CPU
DESCRIPTION OF SYMBOLS 5 Memory part 6 Analog interface part 8 Clock part 31 Packet detection part 32 Packet loss detection part 33 Timing generation part 51 Internal memory 52 Reception jitter buffer 53 Transmission buffer

Claims (6)

Received signal storage means for temporarily storing signals received from the communication network;
Signal storage control means for storing the signal received from the communication network in the received signal storage means;
Transmission signal storage means for temporarily storing a signal to be transmitted to the communication network;
Clock signal output means for outputting a first clock signal and a second clock signal;
Received signal reading means for reading a signal stored in the received signal storage means when the clock signal output means outputs the first clock signal;
A transmission signal writing means for storing a signal to be transmitted to the communication network in the transmission signal storage means when the clock signal output means outputs the second clock signal;
When the amount of the signal stored in the received signal storage means is less than the threshold value, the signal output period of the first clock signal of the clock signal output means is delayed and the signal output period of the second clock signal And the signal output period of the first clock signal of the clock signal output means is shortened when the amount of the signal stored in the received signal storage means is greater than the threshold, and the second clock signal And a clock cycle control means for delaying the signal output cycle. Comprising signal transmission means for transmitting the signal stored in the transmission signal storage means to the communication network;
The signal transmission means increases the transmission period for transmitting the signal stored in the transmission signal storage means to the communication network as the amount of the signal stored in the transmission signal storage means increases, and stores the signal in the transmission signal storage means. The signal transmission / reception apparatus according to claim 1, wherein a transmission period for transmitting a signal stored in the transmission signal storage unit to the communication network is delayed as the amount of the transmitted signal decreases. Signal loss determination means for determining whether or not a signal received from the communication network is missing;
The signal transmitting / receiving apparatus according to claim 1, further comprising a complementing unit configured to generate a signal from a signal already received when it is determined that a signal received from the communication network is missing. A communication synchronization control method using reception signal storage means for temporarily storing a signal received from a communication network and transmission signal storage means for temporarily storing a signal to be transmitted to the communication network,
The signal storage control means stores the signal received from the communication network in the reception signal storage means,
The clock signal output means outputs the first clock signal and the second clock signal,
The received signal reading means reads the signal stored in the received signal storage means when the clock signal output means outputs the first clock signal,
The transmission signal writing means stores the signal to be transmitted to the communication network in the transmission signal storage means when the clock signal output means outputs the second clock signal,
When the clock cycle control means continues the state in which the amount of the signal stored in the received signal storage means is smaller than the threshold value, the clock cycle control means delays the output cycle of the first clock signal of the clock signal output means, and the second clock When the signal output period of the signal is increased, and when the amount of the signal stored in the reception signal storage unit is greater than the threshold value, the signal output period of the first clock signal of the clock signal output unit is increased, A communication synchronization control method characterized by delaying the signal output cycle of the second clock signal. As the amount of signals stored in the transmission signal storage means increases, the signal transmission means increases the transmission cycle for transmitting the signals stored in the transmission signal storage means to the communication network, and stores them in the transmission signal storage means. The communication synchronization control method according to claim 4, wherein the transmission period for transmitting the signal stored in the transmission signal storage means to the communication network is delayed as the amount of the signal being transmitted decreases. The signal loss determination means determines whether or not there is a loss in the signal received from the communication network,
The communication synchronization control method according to claim 4 or 5, wherein the complementing means generates a signal from the already received signal when it is determined that the signal received from the communication network is missing.

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