JP2010216963A - Device and method for defect inspection - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device and method for defect inspection, capable of ensuring the size of an image block processable by a PE (Processor Element) used in image processing in defect inspection. <P>SOLUTION: In these defect inspection device and method, a semiconductor wafer 10 having a pattern formed on its surface is imaged, the obtained image of the semiconductor wafer 10 is divided into a plurality of image blocks to bring the image within a scope of size capable of being processed by the PE used in defect detection processings for detecting a defect in the pattern formed on the surface of the semiconductor wafer, and the number of the PEs being enough for distributing the plurality of image blocks equally out of the plurality of PEs are used to apply the defect detection processings on the plurality of image blocks in parallel. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a defect inspection apparatus and a defect inspection method for inspecting a semiconductor defect in a semiconductor manufacturing process.

  In a general defect inspection apparatus, an image of a semiconductor wafer to be inspected is acquired and image processing is performed to detect defects, and the defect characteristics (position, size, shape, type, etc.) are used as defect information. Output is done.

  As such a defect inspection apparatus, for example, an image of a semiconductor wafer is acquired by a sensor, the image is divided into a predetermined number of image blocks, and the divided image is divided into a plurality of processor elements (hereinafter referred to as PE). In order to achieve high-speed image processing by performing parallel processing (see Patent Document 1).

JP 2005-274172 A

  As the defect inspection using the above-described conventional technology, for example, an image for each chip formed on a semiconductor wafer is cut out as a unit image for defect inspection, and the unit image is divided into image blocks of the number of PEs used for image processing. It can be considered that the divided images are processed in parallel by a plurality of PEs. However, in recent years, with the miniaturization of semiconductor processes, the chip size has been reduced, and the size of unit images for defect inspection has been reduced. Therefore, there is a concern that the size of the image block divided into the number of PEs used for image processing may be smaller than the minimum processing size necessary for performing image processing in each PE. It is conceivable that image processing cannot be performed or an abnormality occurs in the inspection result.

  The present invention has been made in view of the above, and an object thereof is to provide a defect inspection apparatus and a defect inspection method capable of ensuring the size of a processable image block of PE used for image processing for defect inspection. .

  In order to achieve the above object, the present invention provides an imaging means for imaging a sample having a pattern formed on the surface, and an image of the sample obtained by photographing with the imaging means, wherein the pattern defect on the sample surface is detected. Division means for dividing the image data into a plurality of image blocks so as to be within a processable size range of a processor element used for defect detection processing for detecting the image element, and a plurality of the processor elements, and the plurality of image blocks among the processor elements And an image processing means for performing defect detection processing in parallel on the plurality of image blocks.

  According to the present invention, the size of an image block that can be processed by PE used for image processing for defect inspection can be secured.

It is the schematic which shows the whole structure of the defect inspection apparatus which concerns on one embodiment of this invention. It is a figure which extracts and shows the whole control part of the defect inspection apparatus which concerns on one embodiment of this invention with the periphery structure. It is a figure which shows the flow of each data in the defect inspection apparatus which concerns on one embodiment of this invention. It is a figure which shows an example of the setting screen of the defect inspection process in the defect inspection apparatus which concerns on one embodiment of this invention. It is a flowchart showing the inspection process procedure in the defect inspection apparatus which concerns on one embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing an overall configuration of a defect inspection apparatus according to the present embodiment, and FIG. 2 is a diagram showing an overall control unit of the defect inspection apparatus and its peripheral configuration.

  In FIG. 1, the defect inspection apparatus includes an image acquisition unit 110 that acquires an image of a semiconductor wafer (hereinafter referred to as a wafer) 10 that is a sample to be inspected on which a pattern of a semiconductor chip 11 is formed, and an image acquisition. An image processing unit 100 that performs image processing (described later) on an image from the unit 110 and an external device 120 connected to the image processing unit 100 are schematically configured.

  The image acquisition unit 110 receives light from the surface of the wafer 10 and acquires an image signal, and converts the image signal from the sensor 12 into a digital image signal. And an A / D conversion circuit 13 for inputting to 100. The image signal input to the image processing unit 100 is continuous two-dimensional image data of the surface of the wafer 10. Hereinafter, the image data (image signal) is simply referred to as an image.

  The external device 120 includes an input device for inputting a program used for defect inspection, a set value, an inspection condition, a storage unit for storing the program, set value, inspection condition, inspection result, and the like, and a defect inspection result, inspection. And a display device for displaying a user interface (for example, a graphical user interface: GUI) for inputting conditions to the defect inspection apparatus. Inspection conditions, set values, and the like are input from the input device to the image processing unit 100 of the defect inspection device through the GUI.

  The image processing unit 100 includes an image memory 130 that stores the image input from the image acquisition unit 110, a plurality of multiprocessor units 150 and 151 that perform image processing (described later) on the input image, the image processing unit 100, and the image acquisition. And an overall control unit 140 that controls the operation of the entire defect inspection apparatus including the unit 110 and the external device 120. In the present embodiment, two multiprocessor units 150 and 151 are shown as representatives, and the other multiprocessor units are not shown.

  The image memory 130 has a memory space capable of storing a plurality of chip images. The image memory 130 has a cut-out function for cutting out a predetermined area of the stored image as an inspection image. The image memory 130 cuts out an area specified by an instruction signal from the overall control unit 140 as an inspection image. Are input to a plurality of multiprocessor units 150 and 151.

  2, the overall control unit 140 includes an external input / output interface 141, a program management control unit 142, a state management table 143, and an image management control unit 144. The multiprocessor unit 150 includes a distribution control unit 152, A plurality of processor elements (hereinafter referred to as PE) 154 and 155 are provided. The multiprocessor unit 151 has the same configuration as the multiprocessor unit 150, and includes a distribution control unit 153 and a plurality of PEs 156 and 157. In the present embodiment, two PEs 154 and 155 are shown as representatives among the plurality of PEs of the multiprocessor unit 150, and two PEs 156 and 157 are shown as representatives among the plurality of PEs of the multiprocessor unit 151. The illustration and description of other PEs are omitted.

  The external input / output interface 141 converts the format of data input / output to / from the image processing unit 100 into a corresponding format, and enables the exchange of data inside and outside the image processing 100. The external device 120 exchanges data with each unit of the image processing unit 100 via the external input / output interface 141.

  The program management control unit 142 registers a program for defect inspection input from the external device 120 via the external input / output interface 141 or an arbitrary input by the operator, and based on those programs. In addition to controlling the operation of the image processing unit 100, it performs control such as program load control to the PEs 154 to 157 and execution timing thereof. Each PE 154 to 157 can also execute different programs according to instructions from the program management control unit 142.

  The state management table 143 manages states such as the registration status of programs registered in the program management control unit 142 and the execution status of programs in the PEs 154 to 157. Further, the state management table 143 outputs the program execution status and the like to the external device 120 via the external input / output interface 141.

  Based on the command signal from the program management control unit 142, the image management control unit 144 sends an instruction signal to cut out an inspection image of a predetermined area of the wafer 10 (for example, an image of the area of the semiconductor chip 11) in the image memory 130. Further, based on a command signal from the program management control unit 142, the inspection image from the image memory 130 is divided into a plurality of image blocks and distributed to the PEs 154 to 157. At this time, the image management control unit 144 sends an instruction signal to the distribution control units 152 and 153 of the multiprocessor units 150 and 151 to input the divided image blocks to the PE designated by the image management unit 144.

  Further, the image management control unit 144 calculates the size of the plurality of image blocks to be divided according to the size of the inspection image input from the image memory 130 so that it is within the processable size range of each PE 154 to 157. When the sizes of a plurality of image blocks are made equal, the number of PEs to be used decreases as the size of each image block is increased within the processable size range, and the number of PEs to be used increases as the size is decreased. The program management control unit 142 determines PEs to distribute a plurality of image blocks based on the calculation result (that is, the number of image blocks to be divided) in the image management unit 144. In other words, out of a plurality of PEs, the number of PEs that can uniformly distribute a plurality of image blocks is used. Further, the program management control unit 142 puts the PE that does not distribute the image block into a dormant state that suppresses power consumption or executes another program according to the registered program.

  Each of the PEs 154 to 157 uses the program downloaded from the program management control unit 142 to perform defect detection processing on the image blocks whose sizes are calculated and distributed by the image management control unit 144 in parallel. The defect inspection result is sent to the external device 120 via the program management control unit 142 and displayed on the display unit. In this way, the defect inspection process for the image block to which the PEs 154 to 157 are distributed is sequentially repeated, thereby performing the real-time inspection process for the inspection image.

  Next, the flow of data and commands (command signals) in the defect inspection apparatus will be described with reference to FIG.

  FIG. 3 is a diagram showing the flow of each data and command in the defect inspection apparatus according to the embodiment of the present invention.

  Arithmetic programs arbitrarily created by the operator by the external device 120 are registered in the program management control unit 142 via the external input / output interface 141 of the image processing apparatus 100, including start information and execution parameters. The user interface of the external device 120 may be of any form as long as the information setting contents for the external input / output interface 141 are satisfied. For example, an input box or button control on an operation screen using the above-described GUI (Graphical User Interface) may be used as the input operation means of the operator. The registration information of the program is reflected in the state management table 143 and can be referred to from the external device 120 via the external input / output interface 141. As for the display form of the reference information, the implementation form of the user interface is arbitrary.

  The program registered in the program management control unit 142 selects a PE to be executed by the program management control unit 142, and performs load control and execution control of the program to the PE. Setting information and execution status for each of the PEs 154 to 157 are sequentially reflected in the state management table 143 via the program management control unit 142 and can be referred to from the external device 120 via the external input / output interface 141.

  Next, a setting screen in the external device 120 of the defect inspection apparatus will be described.

  FIG. 4 is a diagram showing an example of a setting screen for defect inspection processing in the defect inspection apparatus according to the embodiment of the present invention.

  4, the setting screen includes a program registration unit 200 that registers various programs used in the image processing apparatus 100, and an execution sequence registration unit 300 that registers an execution sequence of each program registered by the program registration unit 200. Yes.

  The program registration unit 200 includes a plurality of program numbers 230 to 234 used for managing registered programs, a plurality of program selection buttons 220 to 224 for selecting a program to be registered for each program number, and a plurality of program selections. Each of buttons 220 to 224 has a plurality of program name display sections 210 to 214 for displaying the names of programs selected. When one of the program selection buttons 220 to 224 is selected, a list of programs stored in the external device 120 is displayed, and the program is registered by selecting a program in the list. For example, by selecting the program selection button 220 of the program number 230 (Function 1) and selecting the program ExampleSEQ1 from the displayed list of programs, the ExampleSEQ1 is registered, and the name of the selected program is displayed in the program name display section. 210 is displayed.

  The execution sequence registration unit 300 includes a plurality of program blocks 301 to 304 that group programs registered by the program registration unit 200. The programs grouped into the program blocks 301 to 304 are executed in the order of arrangement from the top in the program blocks 301 to 304, respectively. The program blocks 301 to 304 are executed in the order of sequence connection. For example, in the case shown in FIG. 4, the program of the program block 301 is first executed, then the programs of the program block 302 and the program block 304 are executed in parallel, and then the program of the program block 305 is executed. In the program block 302, programs are executed in the order of Function2, Function3, and Function4. In the program block 304, programs are executed in the order of Function100 and Function110. While each program is being executed, the program number currently being executed on the setting screen is displayed, for example, by changing the display color or blinking so that the operator can recognize the program being executed.

  Next, the processing procedure of the defect inspection apparatus in the present embodiment will be described with reference to FIG.

  FIG. 5 is a flowchart showing a processing procedure of defect inspection in the defect inspection apparatus according to the embodiment of the present invention.

  When the inspection parameter setting and the inspection start command are notified from the external device 120, first, registered pre-inspection processing is executed (step S10). This corresponds to the execution of the program (Function 1) of the program block 301 in the execution sequence registration unit 300 of FIG. If there is no registration program, this sequence is skipped.

  When the registered pre-inspection process execution (step S10) is completed, pre-inspection preparations such as image distribution control and image processing program activation according to the input inspection parameters are input by the program management control unit 142 and the image management control unit 144. Inspection parameter analysis is performed (step S20).

  When the inspection parameter analysis (step S20) is completed, the image management control unit 144 divides the inspection image into image blocks according to the inspection parameters and distributes the images to the PEs 154 to 157 (step S30), and the image processing registered by the operator. The program management control unit 142 switches the execution program that operates in each of the PEs 154 to 157 according to the inspection parameter for a plurality of programs that implement the inspection algorithm for the input (step S40), and the input image characteristics input from the image management control unit 144 Inspection processing using an image processing algorithm commensurate with the above is executed (step S50). The processing from step S30 to step S50 corresponds to the execution of the program (Function2, Function3, Function4) of the program block 302 in FIG.

  In addition, after the above-described inspection parameter analysis (step S20) is finished, the inspection operation after the input inspection image distribution is executed in parallel with the processing of step S30 to step S50 (step S100). This corresponds to the execution of the program (Function 100, Function 110) of the program block 304 in FIG. In the process of step S100, an arbitrary program loaded on a specific PE by the external device 120 is executed. The execution timing is controlled by the program management control unit 142. If there is no parallel processing registration program in step S100, this sequence is skipped.

  When the processes of step S50 and step 100 are completed, the program loaded on the specific PE by the external device 120 is executed (step S60). This corresponds to the execution of the program (Function 5) of the program block 303 in FIG. In step S60, if there is no registered program, this sequence is skipped.

  In the processing procedure described above, in the registered inspection pre-processing execution (step S10), the registered inspection parallel processing execution (step S100), and the registered post-inspection processing execution (step S60), a plurality of programs are registered. Execution is possible.

  The effect in this Embodiment comprised as mentioned above is demonstrated.

  When the image of the wafer 10 is acquired by the sensor 12, the image is divided into a predetermined number of image blocks, and the divided images are processed in parallel by the plurality of PEs 154 to 157, each chip 11 formed on the wafer 10 is processed. It is conceivable that the image is cut out as an inspection image for defect inspection, the inspection image is divided into the number of image blocks of PEs 154 to 157 used for image processing, and the divided images are processed in parallel by a plurality of PEs 154 to 157. However, with the miniaturization of semiconductor processes, the chip size has been reduced, and the size of inspection images for defect inspection has been reduced. Therefore, there is a concern that the size of the image block divided into the number of PEs 154 to 157 used for image processing may be smaller than the minimum processing size necessary for performing image processing in each PE 154 to 157. It is conceivable that image processing cannot be performed in the defect inspection, or an abnormality occurs in the inspection result.

  On the other hand, in the defect inspection apparatus in the present embodiment, the images of the wafer 10 obtained by photographing with the image acquisition unit 110 are used for the defect detection processing of PEs 154 to 157 that are used for the defect detection process for detecting the pattern defect on the sample surface. A configuration in which defect detection processing is performed in parallel on a plurality of image blocks by dividing the plurality of image blocks into a processable size range and using a number of PEs capable of evenly distributing the plurality of image blocks. Therefore, it is possible to secure the size of the processable image block of the PE used for the image processing of the defect inspection, and to prevent the image processing from becoming impossible in the defect inspection or causing an abnormality in the inspection result. Can do.

  In addition, when the number of PEs used for image processing is adjusted so that the size of the image block does not fall below the minimum processing size of each PE, processing different from defect detection processing is performed in parallel on PE not used for image processing. Therefore, it is possible to suppress a decrease in the use efficiency of processor resources and to increase the functionality of the image processing apparatus.

DESCRIPTION OF SYMBOLS 10 Semiconductor wafer 11 Semiconductor chip 12 Sensor 13 A / D conversion circuit 100 Image processing part 110 Image acquisition part 120 External apparatus 130 Image memory 140 Overall control part 141 External input / output interface 142 Program management control part 143 Status management table 144 Image management control Units 150 and 151 Multiprocessor units 152 and 153 Distribution control units 154 to 157 Processor element 200 Program setting unit 300 Processing flow setting unit

Claims (8)

Imaging means for imaging a sample having a pattern formed on the surface;
An image of the sample obtained by photographing with the imaging means is divided into a plurality of image blocks so as to be within a processable size range of a processor element used for a defect detection process for detecting a defect of a pattern on the sample surface. Dividing means;
An image processing unit that includes a plurality of the processor elements, and uses a number of processor elements that can evenly distribute the plurality of image blocks, and performs defect detection processing on the plurality of image blocks in parallel. A defect inspection apparatus comprising: The defect inspection apparatus according to claim 1,
A defect inspection apparatus comprising means for causing a processor element not used for defect detection processing of the image processing means to perform at least one processing different from the defect detection processing in parallel with the defect detection processing. The defect inspection apparatus according to claim 1,
A defect inspection apparatus comprising means for putting at least a part of a processor element not used for defect detection processing of the image processing means into a dormant state. In the defect inspection apparatus according to claim 1 or 2,
A defect inspection apparatus, comprising: setting means for individually setting processing performed by the plurality of processor elements in each of the plurality of processor elements. In the defect inspection apparatus according to claim 1 or 2,
Display means for displaying a setting screen for individually setting the processing contents of the plurality of processor elements;
A defect inspection apparatus comprising: setting means for setting processing contents of the plurality of processor elements based on a setting screen displayed on the display means. The defect inspection apparatus according to claim 5,
The setting screen includes a registration unit that registers at least one processing content performed by the plurality of processor elements;
A defect inspection apparatus comprising: a setting unit configured to set an order of performing the processing contents set by the setting unit. In the defect inspection apparatus according to claim 1 or 2,
A defect inspection apparatus comprising display means for displaying an operating state and a processing state in each of the plurality of processor elements. An imaging procedure for imaging a sample having a pattern formed on the surface;
A procedure for dividing the image of the sample obtained by the imaging procedure into a plurality of image blocks so as to be within a processable size range of a processor element used for a defect detection process for detecting a defect of a pattern on the sample surface;
A defect inspection method comprising: performing a defect detection process on the plurality of image blocks in parallel using a number of processor elements that can uniformly distribute the plurality of image blocks among the plurality of processor elements. Method.

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