JP2010213371A - Circuit for preventing malfunction of switching element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit for preventing the malfunction of a switching element, which prevents parasitic oscillation and malfunction, and is available together with a conventional countermeasure technique in a simple structure or is singly applicable. <P>SOLUTION: Switching elements S1, S2, ..., are MOSFETs, and for the MOSFETs, their drains and sources are connected in parallel with one another, and their gates are connected likewise in parallel with one another, but gate resistors R are provided and connected severally in series between each gate and a gate assembly point g. A drain assembly point d is connected to one end on the primary side of a transformer T, and a source assembly point s is grounded, and the other end on the primary side of the transformer T is connected to a circuit power source Vcc, and the MOSFETs are turned on and off (parallel operation) by adding a gate control signal to the gate assembly point g. A capacitor C is laid over between the gate assembly point g leading to each gate and the source assembly point s leading to each source. When a potential ripple of short cycles is added to the gate, the capacitor C absorbs the ripple. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a malfunction prevention circuit for a plurality of switching elements that operate in parallel. More specifically, the present invention relates to an improvement in suppression of parasitic oscillation observed in a turn-off transition period.

  As is well known, MOSFETs are used as switching elements in switching power supplies such as inverters and converters. MOSFETs are preferred for power control applications because they are voltage control elements and have low drive power and the ability to perform high-speed switching without carrier accumulation effects due to operation with a single polarity carrier.

  In power control applications, there is a demand to obtain a large output (current capacity). For this reason, a configuration in which switching elements are connected in parallel may be employed. On the other hand, since the MOSFET has a temperature characteristic with positive on-resistance, even if an imbalance occurs in the current flowing through each element in parallel connection, there is a self-stabilizing action that restores the current difference in each element. Suitable for use in parallel operation. For example, Patent Document 1 proposes a technique for avoiding an overall failure of a parallel other party caused by a failure of one of the MOSFETs in which many MOSFETs are connected in parallel.

  In parallel operation of MOSFETs, there is a known problem that current imbalance occurs in the transition period of switching operation and parasitic oscillation occurs in the gate. This is called parasitic oscillation, but as seen in Non-Patent Document 1 and Patent Document 1, for example, a gate resistor is connected in series to each MOSFET's own gate and the other ends of these gate resistors are connected in parallel. The resonance is prevented by lowering the resonance condition Q by the resistance component.

JP 2004-72811 A

Akira Hasegawa “Revised Switching Regulator Design Know-how”, CQ Publisher, 213 pages, Fig. 6-25, published in 1993

  In the MOSFETs connected in parallel, there is a difference in on / off operation due to individual differences or non-uniform wiring, although only one control signal is applied to all the gates. If there is a deviation in the on / off operation, for example, when the individual of the fastest operation turns off, the potential of the drain of the individual increases. Then, since there is a capacitance (parasitic capacitance) between the gate and the drain, the increased potential propagates to another individual through the gate-drain capacitance Cgd, and potential fluctuation is applied to the other gate. In addition, a potential variation different from that of the gate control signal is applied, which causes an unintended timing operation. This is well known as gate parasitic oscillation (parasitic oscillation), and since a parasitic oscillation signal is applied to the gate, the turn-off becomes unstable, causing malfunction, increasing power loss, and destroying the device due to malfunction. Measures have been taken because there is a risk of failure.

  As described above, it is effective to provide a gate resistance in series with each gate to prevent gate parasitic oscillation. Other than that, ferrite beads are inserted in series with each gate, and the wiring is thickened to increase the wiring inductance. There are known countermeasures such as reducing the length of the drain and source wirings and making twisted pair wirings with equal lengths.

  However, the present inventor decided to study another new countermeasure technique different from the conventional countermeasure method and aimed to establish a highly effective countermeasure technique. If a countermeasure technology with a highly effective and simple configuration can be established, there is a merit that operation stability can be further improved by using it together with the conventional countermeasure method, or it can be simplified by applying it alone. We decided to proceed with technology development.

  In order to solve the above-described problems, the present invention provides (1) a malfunction prevention circuit for a switching element in which a plurality of devices are connected in parallel to simultaneously increase / decrease current capacity, and the switching element is a MOSFET. The plurality of MOSFETs are configured such that at least a gate and a source are connected to each other in parallel connection, and a capacitor is provided between a gate set point connected to each gate and a source set point connected to each source.

  (2) Each MOSFET may be configured such that no gate resistance is provided between the gate and the gate assembly point.

  By adopting such a configuration, in the present invention, a capacitor is provided between the gate aggregation point and the source aggregation point, so that it can be absorbed when a short-term potential fluctuation is applied. For this reason, even if there is a deviation in turn-off between individuals in parallel connection, potential fluctuations propagated through the gate-drain capacitance Cgd can be absorbed, and gate parasitic oscillation can be suppressed.

  In the present invention, since a capacitor is provided between the gate aggregation point and the source aggregation point, the capacitor can be absorbed when a short-period potential variation is applied, and therefore the potential variation propagating through the gate-drain capacitance Cgd can be absorbed. It can be absorbed and gate parasitic oscillation can be suppressed.

  That is, in the parallel operation of MOSFETs, parasitic oscillation can be prevented and malfunction can be prevented. Since the capacitor is simply provided between the gate and the source, the configuration is simple, and this can be used together with the conventional countermeasure technique or can be applied alone.

1 is a circuit diagram showing a preferred embodiment of a switching element malfunction prevention circuit according to the present invention. FIG.

  FIG. 1 shows a preferred embodiment of the present invention. The circuit shown in FIG. 1 is a main part of the switching power supply, and includes a plurality of switching elements S1, S2,...

  The switching elements S1, S2,... Are MOSFETs, and the plurality of MOSFETs (S1, S2,...) Are connected in parallel by connecting drains and sources, and the gates are also connected in parallel. A gate resistor R is provided in series with each other and connected to g. A drain set point d having drains connected in parallel is connected to one end on the primary side of the transformer T, a source set point s having sources connected in parallel is grounded, and the other end on the primary side of the transformer T is connected to the circuit power supply Vcc. The switching elements S1, S2,... Are turned on / off (parallel operation) by connecting them and applying a gate control signal to the gate aggregation point g. In other words, the plurality of switching elements S1, S2,... Function as one switching element, and can perform a large current operation with an increased current capacity by parallel connection.

  In this embodiment, the malfunction prevention circuit of the switching elements S1, S2,... Has a configuration in which a capacitor C is provided between a gate set point g connected to each gate and a source set point s connected to each source. The capacitor C can also be configured to have a small capacity for each switching element. That is, it is also preferable to provide a structure in which a small capacitor is connected between the gate resistance R and the source in each MOSFET (S1, S2,...) So as to function with respect to each gate potential fluctuation.

  In addition, since the capacitor C is connected to the gate aggregation point g, it affects the gate control signal. One of them is a reduction in signal peak due to a change in frequency response, and an adverse effect of absorbing and reducing the original gate control signal at high frequencies. It is preferable to perform setting in consideration of the above. Since the signal waveform is changed by the capacitor C and the switching frequency characteristic is affected, there is a possibility that a switching loss is increased. For this reason, the capacitance of the capacitor C is preferably set as appropriate according to the frequency of the switching operation, and is set to an appropriate value in consideration of signal peak reduction and signal waveform change.

  In this case, since the capacitor C is provided between the gate aggregation point g and the source aggregation point s, it can be absorbed when a short-term potential fluctuation is applied. For this reason, even if there is a deviation in turn-off between individuals in parallel connection, potential fluctuations propagated through the gate-drain capacitance Cgd can be absorbed, and gate parasitic oscillation can be suppressed and prevented. That is, in the parallel operation of the MOSFETs (S1, S2,...), Parasitic oscillation can be prevented and malfunction can be prevented.

  The configuration according to the present invention is simple by merely providing a capacitor C between the gate aggregation point g and the source aggregation point s, and a conventional countermeasure technique for providing a gate resistance R as shown in FIG. There is no problem with the combined use, and synergy between the two can be expected, and the stabilization of the operation can be further improved.

  Further, the MOSFETs (S1, S2,...) May be configured such that the gate resistance R is not provided between each gate and the gate aggregation point g. In other words, the present invention can be applied independently without the conventional countermeasure technique, and since only the capacitor C is provided, there is an effect that simplification can be performed.

S1, S2 Switching element (MOSFET)
R Gate resistance C Capacitor T Transformer

Claims (2)

In order to increase the current capacity, it is a malfunction prevention circuit for switching elements that are connected in parallel and operated simultaneously on and off,
The switching element is a MOSFET, and the plurality of MOSFETs are connected in parallel by connecting at least a gate and a source, and a capacitor is passed between a gate set point connected to each gate and a source set point connected to each source. A switching element malfunction prevention circuit characterized by comprising:   2. The malfunction prevention circuit for a switching element according to claim 1, wherein each of the MOSFETs does not have a gate resistance between its own gate and the gate aggregation point.

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