JP6959093B2 - Output circuit and semiconductor device - Google Patents

Description

The present invention relates to output circuits and semiconductor devices.

The following techniques are known as techniques for suppressing the inrush current output from the output circuit when the power is turned on. For example, in Patent Document 1, the feedback voltage obtained by dividing the output voltage is input to the first input terminal, the reference voltage is input to the second input terminal, and the difference between the feedback voltage and the reference voltage is the first. A low-pass filter consisting of a resistor and a capacitor connected between a first error amplifier that outputs as an error voltage, a voltage source of a reference voltage and a second input terminal of the first error amplifier, and a potential difference generated in the resistor. Is input to the second error amplifier that detects and outputs the second error voltage, the first error voltage output from the first error amplifier, and the second error voltage output from the second error amplifier. A voltage regulator circuit including an output transistor for controlling the output voltage is described.

Japanese Unexamined Patent Publication No. 2014-235621

In an output circuit that includes a differential amplifier in which the output voltage output from the output node is input to the inverting input terminal and the reference voltage is input to the non-inverting input terminal, the inrush current at power-on is a problem. Become. For example, when a load capacitance is connected to the output terminal of an output circuit, the potential difference between the inverting input terminal and the non-inverting input terminal of the differential amplifier becomes large until the load capacitance is charged, so that the inrush current is excessive. It is easy to become. In addition, the inrush current may become excessive due to the operation of the load circuit connected to the output terminal of the output circuit becoming unstable temporarily when the power is turned on.

Normally, it is necessary to prepare a power supply having a current capacity corresponding to the maximum current value. Therefore, when the inrush current becomes excessive, a large capacity power supply is required. For example, even if the output current in the steady state is 100 mA, when the inrush current is, for example, 1 A, a power supply capable of outputting a current of 1 A is required.

The present invention has been made in view of the above points, and an object of the present invention is to suppress an inrush current in an output circuit.

The output circuit according to the present invention includes an output unit that outputs an output current of a magnitude corresponding to the level of the output voltage generated in the output node from the output node, a resistance element having one end connected to the output node, and the resistor. A switch connected in parallel to the element and a control unit for controlling an on / off state of the switch are included. The resistance element is configured to include a transistor. In another output circuit of the present invention, the resistance element is configured to include a first transistor, and the switch is configured to include a second transistor having an on-resistance smaller than that of the first transistor. ..
The semiconductor device according to the present invention is configured as the above output circuit formed on a semiconductor substrate.

According to the present invention, it is possible to suppress the inrush current in the output circuit.

It is a circuit diagram which shows the structure of the output circuit which concerns on embodiment of this invention. It is a figure which shows the voltage waveform and the current waveform of each part at the time of power-on of the output circuit which concerns on embodiment of this invention. It is a circuit diagram which shows the structure of the output circuit 1 which concerns on a comparative example. It is a figure which shows the voltage waveform and the current waveform of each part at the time of power-on of the output circuit which concerns on a comparative example. It is a circuit diagram which shows the structure of the output circuit which concerns on other embodiment of this invention. It is a circuit diagram which shows the structure of the output circuit which concerns on other embodiment of this invention. It is a figure which shows the voltage waveform and the current waveform of each part at the time of power-on of the output circuit which concerns on other embodiment of this invention. It is a circuit diagram which shows the structure of the output circuit which concerns on other embodiment of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing, substantially the same or equivalent components or parts are designated by the same reference numerals.

[First Embodiment]
FIG. 1 is a circuit diagram showing a configuration of an output circuit 1 according to a first embodiment of the present invention. Note that FIG. 1 shows a power supply 101 for driving the output circuit 1, a load capacity 103 connected to the output terminal 53 of the output circuit 1, and a circuit block 104 together with the output circuit 1.

The output circuit 1 includes an output unit 10, a resistance element 20, a bypass switch 30, and a control unit 40. Further, the output circuit 1 has a power input terminal 51, a ground terminal 52, and an output terminal 53.

The power input terminal 51 is connected to the positive electrode of the power supply 101 via the power supply switch 102. The power supply 101 generates _{a power supply voltage VCC} for driving the output circuit 1. The ground terminal 52 is connected to the ground line.

The output unit 10 is _{a circuit block that outputs an output current I OUT} having a magnitude corresponding to the level of the _{output voltage V OUT} generated in the output node n1 from the output node n1, and includes a differential amplifier 11 and an output transistor 12. Has been done.

The non-inverting input terminal of the differential amplifier 11 is connected to a reference voltage source 13 that outputs a reference voltage _{V REF.} The reference voltage source 13 may be configured to include, for example, a bandgap circuit. The inverting input terminal of the differential amplifier 11 is connected to the output node n1. The output end of the differential amplifier 11 is connected to the gate of the output transistor 12. The drain of the output transistor 12 is _{connected to the power supply line to which the power supply voltage VCC} is supplied, and the source of the output transistor 12 is connected to the output node n1.

The differential amplifier 11 drives the output transistor 12 so that the level of the _{output voltage V OUT input to the inverting input terminal matches the level of the reference voltage V REF} input to the non-inverting input terminal. As a result, the output transistor 12 outputs _{an output current I OUT} having a magnitude corresponding to the difference (also referred to as an error input) between _{the output voltage V OUT} and the reference voltage V _REF.

One end of the resistance element 20 is connected to the output node n1, and the other end is connected to the output terminal 53. One end of the bypass switch 30 is connected to the output node n1, and the other end is connected to the output terminal 53. That is, the bypass switch 30 is connected in parallel to the resistance element 20. The bypass switch 30 may be composed of, for example, a relay or a transistor.

The control unit 40 controls the on / off state of the bypass switch 30. That is, the control unit 40, while to the power supply voltage V _CC to the output circuit 1 is stabilized output voltage V _OUT from being turned on, controls the bypass switch 30 in the OFF state, after the output voltage V _OUT is stabilized The bypass switch 30 is controlled to be in the ON state.

In the present embodiment, the control unit 40 includes an oscillator 41 and a counter 42. After the power is turned on, the oscillator 41 _{releases the reset state when the level of the output voltage V OUT} generated in the output node n1 reaches a predetermined level, and continuously outputs a plurality of pulses at regular intervals. The counter 42 counts the number of pulses output from the oscillator 41. Counter 42, when the count value of the pulse output from the oscillator 41 has reached a predetermined value, and outputs a control signal S _C to the bypass switch 30 in the ON state, and supplies it to the bypass switch 30. Bypass switch 30 is turned on in response to the control signal S _C.

When the bypass switch 30 is in the off state, the output current I _OUT output from the output unit 10 is supplied to the load capacitance 103 and the circuit block 104 via the resistance element 20. On the other hand, when the bypass switch 30 is in the ON state, both ends of the resistance element 20 are short-circuited by _{the bypass switch, and most of the output current I OUT} output from the output unit 10 passes through the bypass switch 30 to the load capacitance 103 and. It is supplied to the circuit block 104.

In the output circuit 1, the output unit 10, the resistance element 20, the bypass switch 30, and the control unit 40 may be realized in the form of an integrated circuit formed on a semiconductor substrate, and each of the above components may be a printed circuit board. It may be realized in the form mounted on the top.

The operation of the output circuit 1 will be described below. FIG. 2 is a diagram showing an example of the operation of the output circuit 1, and is a diagram showing a voltage waveform and a current waveform of each part when the power is turned on.

In the initial state, the power switch 102 and the bypass switch 30 are each turned off. When the power switch 102 is turned on and the power supply voltage _VCC is applied to the output circuit 1, the reference voltage V _REF rises. The differential amplifier 11 drives the output transistor 12 so that the level of the _{output voltage V OUT input to the inverting input terminal matches the level of the reference voltage V REF} input to the non-inverting input terminal. Since the load capacity 103 and the circuit block 104 are connected to the output terminal 53 of the output circuit 1, the output voltage V _OUT rises more slowly than the reference voltage V _REF. Therefore, error input in the differential amplifier 11 _(V REF _{-V OUT)} is maximized immediately after turning on the power voltage _{V CC.} The output transistor 12, so outputs an output current _{I OUT} of the magnitude corresponding to the error input, immediately after turning on the power voltage _{V CC,} the magnitude of the output current _{I OUT} is maximum, the output current _{I OUT} in the steady state It will be larger than the size.

However, immediately after the power supply voltage _VCC is turned on, the bypass switch 30 is in the off state, so that the output current I _OUT is output from the output terminal 53 via the resistance element 20. Therefore, the output current I _OUT (inrush current) immediately after the power supply voltage _{VCC is turned on can be suppressed.} Assuming that the resistance value of the resistance element 20 is R ₁ , the current value of the inrush current can be suppressed _{to V OUT} / R _{1 or less.}

As the level of the output voltage V _OUT rises, the error input (V _REF −V _OUT ) becomes smaller, and the output current I _OUT becomes smaller accordingly. After that, when the level of the _{output voltage V OUT reaches a predetermined level V 1} , the reset state of the oscillator 41 of the control unit 40 is released, and the oscillator 41 continuously outputs a plurality of pulses at regular intervals. Counter 42, the count value of the number of pulses output from the oscillator 41 reaches a predetermined value, and outputs a control signal S _C to the bypass switch 30 in the ON state, and supplies it to the bypass switch 30. Bypass switch 30 is turned on in response to the control signal S _C. That is, the bypass switch 30 shifts to the on state after the delay time T ₁ elapses after the level of the _{output voltage V OUT reaches V 1.} By providing the delay time T ₁ , the bypass switch 30 can be shifted to the on state when the output voltage V _{OUT is substantially stable.}

When the bypass switch 30 is turned on, _{the path of the output current I OUT} is switched from the path passing through the resistance element 20 to the path passing through the bypass switch 30 having a resistance value smaller than that of the resistance element 20. The output current I _OUT increases once as the path is switched, but then decreases and stabilizes. In this way, after the output voltage V _OUT is stabilized, the output impedance of the output circuit 1 can be reduced by switching the path of the output current I _{OUT to the path via the bypass switch 30 having a smaller resistance value.} can. As a result, it is possible to suppress fluctuations in the voltage output from the output terminal 53 due to load fluctuations and reduce the loss.

FIG. 3 is a circuit diagram showing the configuration of the output circuit 1X according to the comparative example. The output circuit 1X according to the comparative example does not include the resistance element 20, the bypass switch 30, and the control unit 40 included in the output circuit 1 according to the embodiment of the present invention. That is, in the output circuit 1X according to the comparative example, the output node n1 is directly connected to the output terminal 53 and does not have a means for switching the path of the _{output current I OUT.}

FIG. 4 is a diagram showing an example of the operation of the output circuit 1X according to the comparative example, and is a diagram showing a voltage waveform and a current waveform of each part when the power is turned on. According to the output circuit 1X according to the comparative example, the resistance element in the path where the output current I _OUT flows are not provided, immediately after turning on the power voltage V _CC, the output current I _OUT becomes excessive, over-current protection Works. After that, the current value of the output current I _OUT becomes smaller as the level of _{the output voltage V OUT} rises, and stabilizes when the level of the _{output voltage V OUT stabilizes.} Thus, according to the output circuit 1X according to the comparative example, the inrush current becomes excessively large immediately after power-on, the magnitude of the output current I _OUT immediately after the power is turned on, the output current I _OUT after stabilization of the output voltage V _OUT The difference from the size of is large. Since the power supply 101 for driving the output circuit 1 is required to have a current capacity corresponding to the maximum current value, according to the output circuit 1X according to the comparative example, the power supply 101 has a large capacity. Required.

On the other hand, according to the output circuit 1 according to the embodiment of the present invention, after power voltage V _CC, until the output voltage V _OUT is stabilized, the bypass switch 30 is controlled to the OFF state, the output current I _OUT Flows through the path passing through the resistance element 20, so that the inrush current can be suppressed. Therefore, the current capacity of the power supply 101 can be reduced. Further, after the output voltage V _OUT is stabilized, the bypass switch 30 is controlled to be in the ON state, and the output current I _OUT flows through the path passing through the bypass switch 30, so that the output impedance of the output circuit 1 can be reduced. This makes it possible to avoid performance degradation due to suppression of inrush current.

[Second Embodiment]
FIG. 5 is a circuit diagram showing the configuration of the output circuit 1A according to the second embodiment of the present invention. The output circuit 1A is different from the output circuit 1 according to the first embodiment described above in that the bypass switch 30 is composed of an n-channel MOSFET (metal-oxide-semiconductor field-effect transistor) 31. Off of MOSFET31 is controlled by a control signal _{S C} supplied from the control unit 40. For example, the control signal by the _{S C} signal level ground level, it is possible to turn off the MOSFET 31, the signal level of the control signal _{S C} by a higher level than the level of the threshold voltage Vt of the MOSFET , MOSFET 31 can be turned on.

According to the output circuit 1A, similar to the output circuit 1 according to the first embodiment described above, after power voltage _{V CC,} until the output voltage _{V OUT} is stabilized, MOSFET 31 is controlled to the OFF state, Since the output current I _OUT flows through the path passing through the resistance element 20, the inrush current can be suppressed. Further, after the output voltage V _OUT is stabilized, the MOSFET 31 is controlled to be in the ON state, and most of the output current I _OUT flows through the path passing through the MOSFET 31, so that the output impedance of the output circuit 1 can be reduced. can. Further, by configuring the bypass switch 30 with the MOSFET 31, the output circuit 1A can be formed on the semiconductor substrate.

[Third Embodiment]
FIG. 6 is a circuit diagram showing the configuration of the output circuit 1B according to the third embodiment of the present invention. The output circuit 1B is different from the output circuit 1 according to the first embodiment described above in that the bypass switch 30 is composed of the n-channel type MOSFET 31 and the resistance element 20 is composed of the n-channel type MOSFET 21.

Off of MOSFET31 it is controlled by a control signal _{S C1} supplied from the control unit 40, on-off of the MOSFET21 is controlled by a control signal _{S C2} supplied from the control unit 40. The MOSFET 21 constituting the resistance element 20 may be configured to be always on.

The on-resistance of the MOSFET 31 constituting the bypass switch 30 is smaller than the on-resistance of the MOSFET 21 constituting the resistance element 20. Here, in general, the drain current Ids of the MOSFET can be expressed by the following equation (1). In the equation (1), L is the gate length, W is the channel width, Vds is the drain-source voltage, Vgs is the gate-source voltage, and Vt is the threshold voltage.

Therefore, the on-resistance Ron of the MOSFET can be expressed by the following equation (2). As shown in the equation (2), the on-resistance Ron of the MOSFET can be adjusted by the gate length L and the channel width W of the MOSFET. For example, by making the gate length L of the MOSFET 31 shorter than the gate length L of the MOSFET 21 and further making the channel width W of the MOSFET 31 wider than the channel width W of the MOSFET 21, the on-resistance of the MOSFET 31 is made smaller than the on-resistance of the MOSFET 21. be able to.

FIG. 7 is a diagram showing an example of the operation of the output circuit 1B, and is a diagram showing a voltage waveform and a current waveform of each part when the power is turned on.

In the initial state, the power switch 102, the MOSFET 21 constituting the resistance element 20, and the MOSFET 31 constituting the bypass switch 30 are each turned off. Power switch 102 is turned on, when the power supply voltage _{V CC} is supplied to the output circuit 1B, the control unit 40 controls the MOSFET21 constituting the resistance element 20 to the ON state. Further, when the power supply voltage _VCC is supplied to the output circuit 1, the reference voltage V _REF rises. The output voltage V _OUT rises more slowly than the reference voltage V _REF. Therefore, error input in the differential amplifier 11 _(V REF _{-V OUT)} is maximized immediately after turning on the power voltage _{V CC.} The output transistor 12, so outputs an output current I _OUT of the magnitude corresponding to the error input, immediately after turning on the power voltage V _CC, the magnitude of the output current I _OUT is maximum, becomes greater than the size in the steady state ..

However, immediately after turning on the power voltage _{V CC} is MOSFET 21 constituting the resistance element 20 is turned on, the MOSFET 21 constituting the bypass switch 30 is turned off, the output current _{I OUT} is on-resistance It is output from the output terminal 53 via a relatively large MOSFET 21. Therefore, the output current I _OUT (inrush current) immediately after the power supply voltage _{VCC is turned on can be suppressed.}

As the level of the output voltage V _OUT rises, the error input (V _REF −V _OUT ) becomes smaller, and the output current I _OUT becomes smaller accordingly. Thereafter, the level of the output voltage _{V OUT,} after delay time T1 has elapsed after reaching the predetermined level _{V 1,} the control unit 40, outputs a control signal _{S C1} to the MOSFET31 constituting the bypass switch 30 to the ON state Then, this is supplied to the gate of the MOSFET 31. On the other hand, the control unit 40 keeps the MOSFET 21 constituting the resistance element 20 on.

When the MOSFET 31 is turned on, the path of the output current I _OUT is switched from the path via the MOSFET 21 to the path via the MOSFET 31 having a smaller on-resistance. The output current I _OUT increases once as the path is switched, but then decreases and stabilizes. In this way, after the output voltage V _OUT is stabilized, the output impedance of the output circuit 1 can be reduced by switching the path of the output current I _{OUT to the path via the MOSFET 31 having a relatively small on-resistance.} can. As a result, it is possible to suppress fluctuations in the voltage output from the output terminal 53 due to load fluctuations and reduce the loss.

As described above, according to the output circuit 1B, similarly to the output circuit 1 according to the first embodiment described above, after power voltage V _CC, until the output voltage V _OUT is stabilized, the on-resistance Since the relatively small MOSFET 31 is controlled to the off state and the output current I _OUT flows through the path passing through the MOSFET 21 having a relatively large on-resistance, the inrush current can be suppressed. Further, after the output voltage V _OUT is stabilized, the MOSFET 31 having a relatively small on-resistance is controlled to be in the ON state, and most of the output current I _OUT flows through the path passing through the MOSFET 31, so that the output impedance of the output circuit 1B Can be made smaller.

[Fourth Embodiment]
FIG. 8 is a circuit diagram showing a configuration of an output circuit 1C according to a fourth embodiment of the present invention. In the output circuit 1C, the voltage obtained by dividing the reference voltage VREF by the resistance elements 14 and 15 is input to the non-inverting input terminal of the differential amplifier 11, and the output voltage V _OUT generated in the output node n1 is input by the resistance elements 16 and 17. It differs from the output circuit 1 according to the first embodiment described above in that the divided voltage is input to the inverting input terminal of the differential amplifier 11.

According to the output circuit 1C, similarly to the output circuit 1 according to the first embodiment described above, after power voltage V _CC, until the output voltage V _OUT is stabilized, the bypass switch 30 is controlled to be off Since the output current I _OUT flows through the path passing through the resistance element 20, the inrush current can be suppressed. Further, after the output voltage V _OUT is stabilized, the bypass switch 30 is controlled to be in the ON state, and most of the output current I _OUT flows through the path passing through the bypass switch 30, so that the output impedance of the output circuit 1C is increased. It can be made smaller. Further, according to the output circuit 1C, the level of the _{output voltage V OUT} can be adjusted by adjusting the resistance values of the resistance elements 14, 15, 16 and 17.

1, 1A, 1B, 1C Output circuit 10 Output unit 11 Differential amplifier 12 Output transistor 20 Resistance element 21 MOSFET
30 Bypass switch 31 MOSFET
40 Control unit

Claims (6)

An output unit that outputs an output current of a magnitude corresponding to the level of the output voltage generated at the output node from the output node, and an output unit.
A resistance element whose one end is connected to the output node,
A switch connected in parallel to the resistance element and
A control unit that controls the on / off state of the switch,
Only including,
The resistance element is an output circuit including a transistor. An output unit that outputs an output current of a magnitude corresponding to the level of the output voltage generated at the output node from the output node, and an output unit.
A resistance element whose one end is connected to the output node,
A switch connected in parallel to the resistance element and
A control unit that controls the on / off state of the switch,
Only including,
The resistance element is configured to include a first transistor.
The switch is an output circuit including a second transistor having an on-resistance smaller than that of the first transistor. A claim that the control unit controls the switch to an off state when the output unit is started, and controls the switch to an on state when the output voltage level reaches a predetermined level after the output unit is started. 1 or the output circuit according to claim 2. The output circuit according to claim 1, wherein the switch includes a transistor. The output unit includes a differential amplifier circuit in which the output voltage or a voltage corresponding to the output voltage is input to the inverting input terminal, and the reference voltage or the voltage corresponding to the reference voltage is input to the non-inverting input terminal. The output circuit according to any one of claims 1 to 4, which is configured. A semiconductor device in which the output circuit according to any one of claims 1 to 5 is formed on a semiconductor substrate.

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