JP2010206973A - Power converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform the high-speed control for power distribution while suppressing a short-circuit, when the drive voltage of a load is to be generated from a plurality of serially connected power sources. <P>SOLUTION: A switch (switch 4a), corresponding to a high-order power supply (a second power supply 21), is conducted for control with respect to each switch in a single period of a carrier from the lowest-order power supply (the first power supply 20) to the highest-order power supply (the second power supply 21), during a conduction period of a switch (switch 1a) corresponding to the lowest-order power supply (the first power supply 20). <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a power conversion device.

  Conventionally, a technique for efficiently driving a load using a plurality of power supplies has been disclosed. For example, Patent Document 1 discloses a power converter that can use and distribute a plurality of power sources without using a DC / DC converter to reduce the overall volume and loss. Specifically, the power conversion device uses a first power source and a second power source connected in series to connect a positive electrode of the first power source and a negative electrode of the second power source. Then, a voltage pulse is generated from the output voltage of each power source by switching the polarity connected to the load from the negative electrode of the first power source and the positive electrode of the second power source.

  Patent Document 2 discloses a technique in which a plurality of power supplies are connected in parallel to each other, and the power conversion means generates a voltage pulse from the output voltage of each power supply when controlled by the control means. Here, the voltage pulse is generated by turning on and off the PWM pulse corresponding to the power source on the high potential side while the PWM pulse signal corresponding to the power source on the low potential side is on.

JP 2006-121812 A JP 2007-282405 A

  By the way, according to the technique disclosed in Patent Document 1, it is possible to realize output at each potential such as a single power supply potential or a series power supply potential. However, the conduction state and the interruption state of the switch means may continue for a long time, and pulsation may occur in the DC power in the circuit.

  Further, according to the technique disclosed in Patent Document 2, a parallel-connected power source is used / allocated based on the concept of a low potential and a high potential, and a plurality of power sources connected in series are used / allocated. It is not a thing. Further, even if the concept of low potential and high potential is simply applied to series connection, there is a possibility that a short circuit or the like may occur.

  The present invention has been made in view of such circumstances, and an object of the present invention is to enable high-speed control of power distribution while suppressing a short circuit when generating a drive voltage of a load from a plurality of power supplies connected in series. It is to provide a power conversion device.

  In order to solve such a problem, the present invention provides a control for each switch means in one cycle of the carrier, from the lowest power supply to the highest power supply, during the conduction period of the switch means corresponding to the lower power supply. The switch means corresponding to the power source is made conductive.

  According to the present invention, by paying attention to the relationship between the lower power supply and the upper power supply in a plurality of series power supplies, high-speed power distribution can be realized while suppressing the occurrence of short circuits. Thereby, electric power can be supplied to the load while simultaneously controlling a plurality of power supplies.

Explanatory drawing which shows typically the whole structure of the control system containing the power converter device concerning 1st Embodiment. Explanatory drawing which shows the system configuration centering on the power converter 10 typically Explanatory drawing of the electric potential of the output terminal of power converter 10 Explanatory drawing which shows the structure of the modulation | alteration rate instruction | command production | generation part 46 Explanatory drawing which shows the structure of the offset part 46c. Explanatory drawing which shows the structure of the restriction | limiting part 46d. Explanatory drawing of the on-off state of each switch of the power converter 10 by the conduction | electrical_connection signal generation part 47 Explanatory drawing of the on-off state of each switch of the power converter 10 by the conduction | electrical_connection signal generation part 47 Explanatory drawing which shows the relationship between final modulation | alteration rate instruction | command mu1_cmd, mu2_cmd of the 1st power supply 20 and the 2nd power supply 21, and a carrier. Explanatory drawing which shows typically the structure of the voltage distribution command production | generation part 44 concerning 2nd Embodiment. Explanatory drawing which shows typically the system configuration centering on the power converter 10 of the power converter device concerning 3rd Embodiment. Explanatory drawing which shows the last modulation rate instruction | command regarding the 1st-3rd power supplies 20-22 Explanatory drawing of the on-off state of each switch of the power converter 10 concerning 3rd Embodiment. Explanatory drawing which shows typically the structure of the last modulation rate command production | generation part 46b. Explanatory drawing showing final modulation rate commands mu1_cmd and mu2_cmd of the first power supply 20 and the second power supply 21 Explanatory drawing which shows typically the structure of the last modulation rate command production | generation part 46b. Explanatory drawing which shows the relationship between a carrier and final modulation | alteration rate instruction | command mu1_cmd of each power supply 20,21, mu2_cmd Explanatory drawing of the ON / OFF state of each switch of the power converter 10 by the conduction | electrical_connection signal generation part 47 concerning 6th Embodiment. Explanatory drawing which shows typically the whole structure of the control system to which the power converter device concerning 7th Embodiment was applied. Explanatory drawing which shows the system configuration centering on the power converter 10 typically Explanatory drawing of the ON / OFF state of the upper arm SWA and the lower arm SWB of the inverter 24 The block diagram which shows the structure of the modulation | alteration rate instruction | command production | generation part 56 Explanatory drawing which shows the relationship between the final modulation factor command mug_cmd-mwg_cmd of each phase, the 4th bus-line current Ib4, and the switching state of the upper arm of each phase Explanation will be given on the relationship between the offset with respect to the final modulation rate commands mu1_cmd to mw2_cmd and the first to third bus currents Ib1 to Ib3. Explanatory drawing which shows the simulation result of 1st-3rd bus-bar current Ib1-Ib3 Schematic diagram for explaining the synchronization between second bus current Ib2 and fourth bus current Ib4 Explanatory diagram for explaining synchronization between second bus current Ib2 and fourth bus current Ib4 Explanatory diagram for explaining synchronization between second bus current Ib2 and fourth bus current Ib4 Explanatory diagram for explaining synchronization between second bus current Ib2 and fourth bus current Ib4 Explanatory diagram for explaining synchronization between second bus current Ib2 and fourth bus current Ib4

(First embodiment)
FIG. 1 is an explanatory diagram schematically showing an overall configuration of a control system including a power conversion device according to the first embodiment of the present invention. In the present embodiment, a control system applied to a drive motor for an electric vehicle will be described. This control system is mainly configured by a power converter 10, a motor 30, and a control unit 40, and the power converter 10 and the control unit 40 constitute a power conversion device according to the present embodiment.

  FIG. 2 is an explanatory diagram schematically showing a system configuration centering on the power converter 10. The power converter 10 is connected to a plurality of power supplies (first and second power supplies 20 and 21 in the present embodiment) connected in series with each other, and is controlled by the control unit 40 so that each power supply 20, An output voltage pulse is generated from the output voltage 21 (first power conversion means). And the power converter 10 produces | generates the drive voltage of the three-phase alternating current synchronous motor 30 which is a load with this output voltage pulse.

  Here, each of the first and second power sources 20 and 21 is an independent DC power source, and includes a positive electrode of the first power source 20 which is a lower power source and a second power source 21 which is a higher power source. It is connected in series by connecting the negative electrode. As each power supply 20, 21, for example, a battery such as a nickel metal hydride battery or a lithium ion battery can be used. A negative electrode bus 13 is connected to the negative electrode of the first power supply 20, and a positive electrode bus 14 is connected to the positive electrode of the second power supply 21. The positive electrode of the first power supply 20 and the negative electrode of the second power supply 21 are connected to the common bus 15. A smoothing capacitor 11 is provided between the negative electrode bus 13 and the common bus 15, and a smoothing capacitor 12 is provided between the positive electrode bus 14 and the common bus 15.

  In the power converter 10, switch means capable of controlling bidirectional conduction is connected between the common bus 15 and the output terminals corresponding to the three phases. Each switch means includes a pair of semiconductor switches (for example, switching elements such as NPN type transistors) 1a, 1b to 3a, 3b, each of which can control conduction in one direction. It is configured by connecting in series in a state. In addition, switch means similar to the upper arm of a general three-phase inverter is connected between the positive electrode bus 14 and the output terminals corresponding to the three phases. Each switch means is mainly composed of semiconductor switches (for example, switching elements such as NPN type transistors) 4a to 6a, and each switch (transistor) 4a to 6a is a free-wheeling diode between the collector and the emitter. 4b to 6b are connected in reverse parallel. Furthermore, switch means similar to the lower arm of a general three-phase inverter is connected between the negative electrode bus 13 and the output terminals corresponding to the three phases. Each switch means is composed mainly of semiconductor switches (for example, switching elements such as NPN type transistors) 7a to 9a, and each switch (transistor) 7a to 9a is a free-wheeling diode between the collector and the emitter. 7b to 9b are connected in reverse parallel.

  The on / off state of these semiconductor switches (hereinafter simply referred to as “switches”), that is, switching between conduction and cutoff (switching operation) is controlled through a drive signal output from the control unit 40. Each switch is turned on by the control unit 40, and turned off and turned off (cut off).

  FIG. 3 is an explanatory diagram of the potential of the output terminal of each phase of the power converter 10. The potential of the output terminal of each phase of the power converter 10 is the voltage of the first power supply 20 (hereinafter referred to as “first power supply voltage”) Vdc1 and the voltage of the second power supply 21 (hereinafter referred to as “second power supply voltage”). Based on Vdc2, it can be considered as follows. Hereinafter, only the U phase will be described as an example, but the potential of the output terminal corresponding to the other phases (V phase, W phase) can be considered in the same manner.

  First, as shown in FIG. 5A, the switches 1a and 1b between the common bus 15 and the U-phase output terminal are turned off. In this case, the potential of the U-phase output terminal is based on a series power supply (power supply voltage “Vdc1 + Vdc2”) in which two power supplies 20 and 21 are connected in series, as in the inverter circuit using the switches 4a and 7a as upper and lower arms. The switches 4a and 7a can be operated by controlling the on / off state.

  As shown in FIG. 4B, the switch 4a between the positive bus 14 and the U-phase output terminal is turned off, and the pair of switches 1a and 1b between the common bus 15 and the U-phase output terminal One switch 1b is turned on. In this case, the potential of the U-phase output terminal controls the on / off state of the switches 1a and 7a based on the first power supply 20 (power supply voltage “Vdc1”) as in the inverter having the switches 1a and 7a as upper and lower arms. Can be operated.

  As shown in FIG. 5C, the switch 7a between the negative bus 13 and the U-phase output terminal is turned off, and the pair of switches 1a and 1b between the common bus 15 and the U-phase output terminal The other switch 1a is turned on. In this case, the potential of the U-phase output terminal is based on the second power supply 21 (power supply voltage “Vdc2”), and controls the on / off state of the switches 1b and 4a in the same manner as an inverter having the switches 1b and 4a as upper and lower arms. Can be operated.

  As described above, the power converter 10 can drive the motor 30 by using the two power supplies 20 and 21 simultaneously or by using only one of the power supplies 20 and 21.

  The motor 30 includes, for example, a plurality of phase windings star-connected around a neutral point (in this embodiment, three phase windings including a U-phase winding, a V-phase winding, and a W-phase winding) Is a three-phase AC synchronous motor. The motor 30 is driven by an interaction between a magnetic field generated by supplying three-phase AC power converted in the power converter 10 to each phase winding and a magnetic field generated by a permanent magnet of the rotor. The rotor of the motor 30 is connected to the input shaft of the automatic transmission.

  Referring to FIG. 1 again, the control unit 40 is a control unit that controls the power converter 10, and controls the output torque of the motor 30 that is a load via the power converter 10 (first control unit). ). As the control unit 40, a microcomputer mainly composed of CPU, ROM, RAM, and I / O interface can be used. The control unit 40 performs a calculation for controlling the power converter 10 in accordance with a control program stored in the ROM. Then, the control unit 40 outputs the control signal calculated by this calculation to the power converter 10.

  When the control unit 40 grasps this functionally, the torque control unit 41, the current control unit 42, the dq / 3-phase conversion unit 43, the voltage distribution command generation unit 44, the voltage distribution unit 45, the modulation A rate command generation unit 46, a conduction signal generation unit 47, a carrier wave generation unit 48, and a three-phase / dq conversion unit 49 are included.

  The torque control unit 41 calculates the d-axis and q-axis current command values id * and iq * of the motor 30 based on the torque command T * given from the outside and the motor rotational speed ω, respectively. Based on the d-axis and q-axis current command values id * and iq * and the d-axis and q-axis current values id and iq, the current control unit 42 is configured to match the command value with the actual value. q-axis voltage command values vd * and vq * are respectively calculated. Here, the d-axis and q-axis current values id and iq are calculated by detecting the current of each phase of the motor 30 by the current sensor and then converting the three-phase current by the three-phase / dq conversion unit 49. The Since the sum of the currents of the respective phases of the motor 30 is zero, the currents of the respective phases of the motor 30 can be specified by detecting at least the two-phase currents iu and iv. The dq / 3-phase conversion unit 43 converts the d-axis and q-axis voltage command values vd *, vq * into three-phase output voltage command values vu *, vv *, vw *.

  The target distribution ratio rto * is input to the voltage distribution command generation unit (voltage distribution command generation means) 44 from the outside. This target distribution ratio rto * is a parameter indicating the output ratio of the first power supply 20. When power is output only from the first power supply 20, “1” is input as the target distribution ratio rto *, and when power is output only from the second power supply 21, “0” is input as the target distribution ratio rto *. Is done. Further, when power is evenly distributed between the first power supply 20 and the second power supply 21, “0.5” is input as the target distribution ratio rto *. When the target distribution ratio rto * is input, the voltage distribution command generation unit 44 outputs the voltage distribution command rto_cmd to the voltage distribution unit 45 based on this value. The voltage distribution command rto_cmd is a parameter indicating the distribution of the output voltage to the first power supply 20 and the second power supply 21, and in this embodiment, as a value (rto_cmd = rto *) corresponding to the target distribution ratio rto *. Generated by the voltage distribution command generator 44.

  The voltage distribution unit 45 distributes the output voltage command values vu *, vv *, vw * of each phase according to the voltage distribution command rto_cmd output from the voltage distribution command generation unit 44 (voltage distribution means). As a result, distributed voltage command values Vu1_cmd, Vv1_cmd, and Vw1_cmd, which are three-phase output voltage command values for the first power supply 20, and distributed voltage command values Vu2_cmd, which are three-phase output voltage command values for the second power supply 21, Vv2_cmd and Vw2_cmd are calculated.

Here, the calculation concept of the distribution voltage command values Vu1_cmd to Vw2_cmd calculated by the voltage distribution unit 45 will be described. In order to change the ratio of the electric power P1 supplied from the first power supply 20 and the electric power P2 supplied from the second power supply 21 while controlling the motor torque according to the torque command value T *, Formula 1 is shown. It is only necessary to satisfy both the voltage condition and the power condition shown in Formula 2.

By using Equations 1 and 2 and the voltage distribution command rto_cmd, the distribution voltage command values Vu1_cmd to Vw2_cmd are defined by the following relationship. The voltage distribution unit 45 calculates the distribution voltage command values Vu1_cmd to Vw2_cmd based on the three-phase output voltage command values vu *, vv *, vw * and the voltage distribution command rto_cmd, as shown in the following equation. .

  FIG. 4 is an explanatory diagram showing the configuration of the modulation factor command generator 46. The modulation rate command generation unit 46 refers to the first and second power supply voltages Vdc1 and Vdc2, and generates final modulation rate commands mu1_cmd to mw2_cmd from the distributed voltage command values Vu1_cmd to Vw2_cmd. The final modulation rate commands mu1_cmd to mw2_cmd are command values for the modulation rate to be compared with the carrier (first carrier) generated by the carrier wave generation unit 48 in order to generate the output voltage pulse. The modulation rate command generation unit 46 includes an initial modulation rate command generation unit 46a and a final modulation rate command generation unit 46b.

  The initial modulation rate command generator 46a calculates the initial modulation rate commands mu1 to mw2 by normalizing the distribution voltage command values Vu1_cmd to Vw2_cmd with the power supply voltages Vdc1 and Vdc2 (initial modulation rate command generation means). Specifically, each of the distribution voltage command values Vu1_cmd to Vw1_cmd related to the first power supply 20 is normalized by the first power supply voltage Vdc1, that is, each of the distribution voltage command values Vu1_cmd to Vw1_cmd is the first power supply voltage. Divided by Vdc1. Thereby, the initial modulation rate commands mu1 to mw1 of the respective phases related to the first power supply 20 are calculated. Also, each of the distribution voltage command values Vu2_cmd to Vw2_cmd related to the second power supply 21 is normalized by the second power supply voltage Vdc2, that is, each of the distribution voltage command values Vu2_cmd to Vw2_cmd is divided by the second power supply voltage Vdc2. Is done. Thereby, the initial modulation rate commands mu2 to mw2 of the respective phases related to the second power source 21 are calculated.

  The final modulation rate command generating unit 46b generates final modulation rate commands mu1_cmd to mw2_cmd based on the initial modulation rate commands mu1 to mw2. The final modulation rate command generation unit 46b includes an offset unit 46c and a limiting unit 46d.

  FIG. 5 is an explanatory diagram showing the configuration of the offset unit 46c. The offset unit 46c performs an offset process for offsetting the initial modulation rate commands mu1 to mw2 for the power supplies 20 and 21 (offset means). Specifically, the offset unit 46 c performs an offset process so that the modulation rate command for the first power supply 20 is equal to or greater than the modulation rate command for the second power supply 21. By this offset processing, the switches 4a to 6a connected to the load from the positive electrode of the second power supply 21 are turned on during the conduction period of the switches 1a to 3a connected from the positive electrode of the first power supply 20 to the load. Final modulation rate commands mu1_cmd to mw2_cmd are defined.

  The offset unit 46c includes a modulation factor amplitude calculation unit 46e, an offset value generation unit 46f, and an offset processing unit 46g.

The modulation factor amplitude calculator 46e calculates the amplitudes of the initial modulation factor commands mu1 to mw2 on the premise of obtaining an offset value necessary for the offset processing. Specifically, the modulation factor amplitude calculation unit 46e determines the amplitude of the output voltage command values vu *, vv *, vw * based on the d-axis and q-axis voltage command values vd *, vq *, for example, the U-phase output. The amplitude vu * _pk of the voltage command value vu * is calculated (see Equation 4 (1)). Next, using the calculated amplitude vu * _pk and the voltage distribution command rto_cmd, the amplitude of the distributed voltage command values Vu1_cmd to Vw1_cmd related to the first power supply 20, for example, the amplitude vu1_cmd_pk of the U-phase distributed voltage command value Vu1_cmd, Then, the amplitude of the distributed voltage command values Vu2_cmd to Vw2_cmd related to the second power supply 21, for example, the amplitude vu2_cmd_pk of the U-phase distributed voltage command value Vu2_cmd is calculated (see equations 4 (2) and (3)). The calculated amplitudes vu1_cmd_pk and vu2_cmd_pk are normalized by the corresponding power supply voltages Vdc1 and Vdc2 (see equations 4 (4) and (5)). As a result, the amplitude (hereinafter referred to as “first modulation factor amplitude”) mu1_pk of the initial modulation rate commands mu1 to mw1 related to the first power supply 20 and the amplitude (hereinafter referred to as the initial modulation rate commands mu2 to mw2 related to the second power supply 21). Mu2_pk) (referred to as “second modulation factor amplitude”).

  The offset value generation unit 46f is provided for each power source 20 so that the modulation rate command can be compared with the carrier, and so that the modulation rate command for the first power source 20 is equal to or higher than the modulation rate command for the second power source 21. The offset values m1_off and m2_off for the initial modulation rate commands mu1 to mw1 and mu2 to mw2 are calculated. Here, the first offset value m1_off is an offset value with respect to the first initial modulation rate commands mu1 to mw1, and the second offset value m2_off is an offset value with respect to the second initial modulation rate commands mu2 to mw2. .

In the offset process, basically, the modulation rate command relating to the first power supply 20 is offset so as to be positioned below the upper part of the carrier (the upper limit (maximum value) of the carrier amplitude), and the second power supply 21 The modulation rate command is offset so as to be positioned above the lower part of the carrier (lower limit (minimum value) of carrier amplitude). Specifically, the first and second offset values m1_off and m2_off are calculated based on the following expression. By referring to the first and second modulation factor amplitudes mu1_pk and mu2_pk, offset values m1_off and m2_off are calculated so that the modulation factor command can be compared with the carrier at all times.

  The offset processing unit 46g calculates the offset modulation rate commands mu1_off to mw2_off by performing offset processing on the initial modulation rate commands mu2 to mw2 based on the offset values m1_off and m2_off. Specifically, the offset processing unit 46g adds the first offset value m1_off to each of the initial modulation rate commands mu1 to mw1 related to the first power supply 20, thereby offset-modulating each phase related to the first power supply 20. The rate commands mu1_off to mw1_off are respectively calculated. Further, the offset processing unit 46g adds the second offset value m2_off to the initial modulation rate commands mu2 to mw2 related to the second power supply 21 to thereby set the offset modulation rate commands mu2_off of the respective phases related to the second power supply 21. ~ Mw2_off is calculated respectively.

  FIG. 6 is an explanatory diagram showing the configuration of the limiting unit 46d. The limiting unit 46d performs a limiting process on the modulation rate commands of the power supplies 20 and 21 that have been subjected to the offset process, that is, the offset modulation rate commands mu2_off to mw2_off, so that the final modulation rate commands of the power supplies 20 and 21 are performed. Generate mu1_cmd to mw2_cmd (restriction means). The limiting unit 46d performs a conduction process of the switches 1a to 3a connected from the positive electrode of the first power supply 20 to the load and the switches 4a to 6a connected from the positive electrode of the second power supply 21 to the load. It has a function to limit the conduction time so that it does not reverse in the magnitude relationship. Specifically, the limiting unit 46d limits the modulation rate command so that it does not fall outside the range of the maximum value (specifically “1”) and the minimum value (specifically “0”) of the carrier, Further, the modulation rate related to the first power source 20 is limited so as not to be less than the modulation rate related to the second power source.

  The limiting unit 46d includes a priority modulation rate selecting unit 46h and a modulation rate limiting unit 46i.

  The priority modulation rate selection unit 46h selects which of the first and second power sources 20, 21 is to give priority to the modulation rate command of the power source 20, 21. This selection is to apply the other modulation rate command on the basis of the modulation rate command to be prioritized when limiting the modulation rate command related to the first power supply 20 to be higher than the modulation rate command related to the second power supply 21. Done. Specifically, when the voltage distribution command rto_cmd is larger than 1 (rto_cmd> 1), the modulation rate command related to the first power supply 20 is selected as the priority modulation rate. When the voltage distribution command rto_cmd is smaller than 0 (rto_cmd <0), the modulation rate command related to the second power supply 21 is selected as the priority modulation rate. On the other hand, when the voltage distribution command rto_cmd is 0 or more and 1 or less (0 ≦ rto_cmd ≦ 1), none of the modulation rate commands related to the first and second power supplies 20 is selected as the priority modulation rate. By performing such selection, the modulation rate commands of the power supplies 20 and 21 in which the distributed voltage command values Vu1_cmd to Vw2_cmd are larger than the output voltage command values vu *, vv *, and vw * before voltage distribution. Can be selected.

  The modulation rate limiting unit 46i sets upper and lower limits for the initial modulation rate commands mu1 to mw2 based on the selection result of the priority modulation rate selection unit 46h, and limits the offset modulation rate commands mu1_off to mw2_off according to the set limits. I do. Hereinafter, the relationship between the modulation rate command that is preferentially selected and its limitations (upper limit and lower limit) will be described.

  As a first case, a case where a modulation rate command related to the first power supply 20 is selected as the priority modulation rate will be described. In this case, “1 (maximum value of carrier)” is set as the upper limit and “0 (minimum value of carrier)” is set as the lower limit as the limitation of the modulation rate command of each phase related to the first power supply 20. In addition, as a limitation on the modulation rate command for each phase related to the second power supply 21, the smaller one of “1” and “offset modulation rate commands mu1_off to mw1_off of the first power supply 20” is set as the upper limit. Is set to “0”.

  As a second case, a case where a modulation rate command related to the second power source 20 is selected as the priority modulation rate will be described. In this case, the upper limit of “1” is set as the limit of the modulation rate command of each phase related to the first power supply 20, and the lower limit of “0” and “offset modulation rate commands mu2_off to mw2_off of the second power supply 21” are set. The larger value is set. In addition, as a limitation on the modulation rate command of each phase relating to the second power supply 21, “1” is set as the upper limit and “0” is set as the lower limit.

  As a third case, a case where nothing is selected as the priority modulation rate will be described. In this case, “1” is set as the upper limit, “0” is set as the upper limit, and “offset modulation rate commands mu2_off to mw2_off of the second power supply 21” are set as the upper limit as the limit of the modulation rate command of each phase related to the first power supply 20. The larger value is set. In addition, as a limitation on the modulation rate command for each phase related to the second power supply 21, the smaller one of “1” and “offset modulation rate commands mu1_off to mw1_off of the first power supply 20” is set as the upper limit. The value is set to “0”.

  The modulation rate limiting unit 46i generates final modulation rate commands mu1_cmd to mw2_cmd by inputting the offset modulation rate commands mu1_off to mw2_off using the upper limit and the lower limit set as described above as limiters. Specifically, final phase modulation rate commands mu1_cmd to mw1_cmd for each phase relating to the first power source 20 and final phase modulation factor commands mu2_cmd to mw2_cmd for each phase relating to the second power source 21 are generated.

  Referring again to FIG. 1, the conduction signal generation unit 47 sets the on / off state of each switch of the power converter 10 based on the final modulation rate commands mu1_cmd to mw2_cmd and the carrier generated by the carrier generation unit 48. A conduction signal is generated. And the conduction | electrical_connection signal production | generation part 47 controls the on-off state of each switch of the power converter 10 through the produced | generated conduction signal (conduction control means). In the present embodiment, the carrier wave generation unit 48 generates a carrier that periodically varies with a lower limit of “0” and an upper limit of “1”. In addition, although a triangular wave can be used for a carrier, you may use a sawtooth wave instead of a triangular wave.

  FIG. 7 is an explanatory diagram of an on / off state of each switch of the power converter 10 by the conduction signal generation unit 47. The conduction signal generation unit 47 generates a conduction signal as a result of comparison between the final modulation factor commands mu1_cmd to mw2_cmd and the carrier, and controls the on / off state of each switch through the conduction signal. Hereinafter, only the U phase will be described, but the same applies to the other phases. In FIG. 7, each switch 1a, 1b, 4a, 7a is turned on when the conduction signal relating to each switch 1a, 1b, 4a, 7a is at a high level. Vun indicates a U-phase output voltage, that is, a voltage between the U-phase output of the power converter 10 and the negative electrode of the smoothing capacitor 11.

  First, consider a case in which an inverter circuit (see FIG. 3B) configured only by the first power supply 20 is driven by comparing the carrier with the final modulation factor command mu1_cmd of the first power supply 20. When the final modulation rate command mu1_cmd is smaller than the carrier (mu1_cmd <carrier), the conduction signal generation unit 47 controls the switch 1a to be off and the switch 7a to be on. On the other hand, when the final modulation rate command mu1_cmd is larger than the carrier (mu1_cmd> carrier), the switch 1a is controlled to be on and the switch 7a is controlled to be off.

  Next, consider a case where an inverter circuit (see FIG. 3C) configured only by the second power supply 21 is driven by comparing the carrier with the final modulation factor command mu2_cmd of the second power supply 21. When the final modulation factor command mu2_cmd is smaller than the carrier (mu2_cmd <carrier), the conduction signal generation unit 47 controls the switch 1b to be on and the switch 4a to be off. On the other hand, when the final modulation rate command mu2_cmd is larger than the carrier (mu2_cmd> carrier), the switch 1b is controlled to be off and the switch 4a is controlled to be on.

  As can be seen from FIG. 7, in this embodiment, the following states (1) to (4) are obtained in the PWM 1 cycle, that is, the carrier 1 cycle, by operating the U-phase switches 1a, 1b, 4a, and 7a. Are set sequentially.

(1) Off switch 1a of all power supplies 20 and 21: off, switch 7a: on, switch 1b: on, switch 4a: off (2) Only the lower first power supply 20 is on switch 1a: on, switch 7a: off , Switch 1b: on, switch 4a: off (3) During the on-period of the first power supply 20, the upper switch 2a of the second power supply 21 is on, switch 7a: off, switch 1b: off, switch 4a : ON (4) Only the lower first power supply 20 is ON (the upper second power supply 21 is OFF)
Switch 1a: On, Switch 7a: Off, Switch 1b: On, Switch 4a: Off As can be seen from the series of switch operations, the control for each switch connected to the motor 30 from each power source 20, 21 in one cycle of the carrier is It can be shown as follows. Specifically, the switch 4a connected from the second power supply 21 to the motor 30 during the conduction period of the switch 1a connected from the first power supply 20 to the motor 30 from the first power supply 20 to the second power supply 21. Is conducted. By this switch control, the output voltage pulse in one cycle of the carrier is the negative voltage (“0”) of the lowest first power supply 20, the positive voltage (“Vdc1”) of the first power supply 20, and the first And a positive voltage (“Vdc1 + Vdc2”) output from the second power supply 21 during the positive voltage output period of the power supply 20, and has a convex waveform.

  Thus, in the present embodiment, in the power converter 10, as control for each switch in one cycle of the carrier, from the lowest power supply (first power supply 20) to the highest power supply (second power supply 21), During the conduction period of the switch (switch 1a) corresponding to the lower power supply (first power supply 20), the switch (switch 4a) corresponding to the upper power supply (second power supply 21) is turned on. Under the control of the power converter 10, the output voltage pulse in one cycle of the carrier is the negative voltage (“0”) of the first power supply 20 and the highest power supply from the lowest power supply (first power supply 20). It is composed of positive voltages (“Vdc1” and “Vdc1 + Vdc2”) output by each power supply during the positive voltage output period of the power supply lower than itself over (second power supply 21). According to such a configuration, by controlling the series power supply from the lower order to the higher order, high-speed power distribution can be realized while suppressing the occurrence of a short circuit. Thereby, electric power can be supplied to the motor 30 while controlling both the power supplies 20 and 21 simultaneously.

  FIG. 8 is an explanatory diagram of an on / off state of each switch of the power converter 10 by the conduction signal generation unit 47. As described above, the switch corresponding to the upper power supply is turned on during the conduction period of the switch corresponding to the lower power supply. In the example shown in FIG. 7, the conduction period of the switch corresponding to each power source is sequentially shortened from the lowest to the highest. By the way, as shown in FIG. 8, in the case where the final modulation rate command mu1_cmd of the first power supply 20 and the final modulation rate command mu1_cmd of the second power supply 21 coincide with each other, a switch ( In synchronization with the beginning of the conduction period of the switch 1a), the switch (switch 4a) corresponding to the higher power supply is turned on. Further, in synchronization with the end of the conduction period of the switch (switch 1a) corresponding to the lower power supply, the switch (switch 4a) corresponding to the upper power supply is cut off. In this case, the conduction period of the switch corresponding to each power source is the same from the lowest to the highest in one carrier cycle. The output voltage pulse in one cycle of the carrier includes the negative voltage (“0”) of the lowest power supply (first power supply 20) and the lower power supply (second power supply 21) lower than the power supply (second power supply 21). It is composed of a positive voltage (“Vdc1 + Vdc2”) output during the positive voltage output period of the first power supply 21), and becomes a simple rectangular wave. As described above, in this specification, “during the switch conduction period” and “during the positive voltage output period of the lower power supply” include the entire range from the start point to the end point of the period.

  FIG. 9 is an explanatory diagram showing the relationship between the voltage distribution command rto_cmd, the final modulation rate command mu1_cmd of the first power supply 20, the final modulation rate command mu2_cmd of the second power supply 21, and the carrier. FIGS. 4A and 4C show cases where the voltage distribution command rto_cmd is larger than “0” and smaller than “1”. In this case, the two power sources 20 and 21 share the power of the motor 30. FIG. 5B shows a case where the voltage distribution command rto_cmd is smaller than “0” or a case where the voltage distribution command rto_cmd is larger than “1”. In the former case, the second power source 21 outputs more power than the motor 30 and the first power source 20 is charged. In the latter case, the first power source 20 outputs more power than the motor 30 and the second power source 21 is charged.

  FIG. 4D shows a case where the voltage distribution command rto_cmd is “1”. In this case, the electric power of the motor 30 is output only by the first power supply 20. FIG. 5E shows a case where the voltage distribution command rto_cmd is “0”. In this case, the power of the motor 30 is output only by the second power supply 21.

  In the present embodiment, the final modulation rate command values mu1_cmd to mw2_cmd are calculated by performing offset processing on the initial modulation rate commands mu1 to mw2 and then performing restriction processing. In the offset process, the final modulation factor commands mu1_cmd to mw1_cmd of the first power supply 20 are relatively offset so that they become equal to or greater than the final modulation factor commands mu1_cmd to mw1_cmd of the second power supply 20. Thereby, the conduction time of the switch 1a corresponding to the first power supply 20 is set to be longer than the conduction time of the switch 4a corresponding to the second power supply 21. Therefore, it is possible to supply power to the motor 30 while suppressing abnormalities in the switching pattern and stably controlling both the power supplies 20 and 21 simultaneously. Further, the output voltage command values vu *, vv *, and vw * are distributed according to the voltage distribution command rto_cmd, and initial modulation rate commands mu1 to mw2 are generated thereon. Therefore, the output power of each power source 20 and 21 can be controlled with an arbitrary value, and the power can be transferred between the power sources 20 and 21 by the voltage distribution command rto_cmd.

  In the present embodiment, as the limiting process, limit values (upper limit and lower limit) regarding the initial modulation rate commands mu1 to mw2 of the power supplies 20 and 21 are set, and the offset modulation rate commands mu1_off to mw2_off are within the limit value range. Limited. According to such a configuration, it is possible to set a limit value, and therefore it is possible to perform a limit process in accordance with the driving state. Thereby, even if it is a case where the load of the motor 30 changes suddenly, the situation where an unnecessary restriction | limiting is applied can be suppressed. As a result, motor controllability can be improved.

  In the present embodiment, the modulation rate limiting unit 46i applies the offset modulation rate commands mu1_off to mw2_off related to the other power supply in addition to the maximum value or the minimum value of the carrier as the limit values related to the offset modulation rate commands mu1_off to mw2_off. Is done. According to such a configuration, since the offset modulation rate commands mu1_off to mw2_off related to the first or second power source 20, 21 use the mutual values as the limit values, the range of the modulation rate command value that does not reverse the conduction time is maximized. can do. Therefore, the output range to the motor 30 can be maximized, or the voltage distribution ratio setting range can be maximized.

  Further, in the present embodiment, the limiting unit 46d includes a priority modulation rate selection unit 46h that selects which modulation rate command has priority for the modulation rate commands related to the power supplies 20 and 21. By selecting the priority modulation rate command, the other modulation rate command can be limited in accordance with the priority modulation rate command when the modulation rates cross each other. As a result, it is possible to suppress a situation in which a space in which the modulation rate command is not output is generated, so that the output power to the motor 30 can be kept large.

  The priority modulation rate selection unit 46h selects a modulation rate command corresponding to a power supply in which the distributed voltage command values Vu1_cmd to Vw2_cmd are larger than the output voltage command values vu *, vv *, vw *. Therefore, the modulation rate command corresponding to one of the power supplies 20 and 21 that mainly drives the motor 30 is selected. Thereby, since the output electric power to the motor 30 is ensured stably, the output fluctuation of the motor 30 can be suppressed.

  Further, in the present embodiment, the modulation rate limiting unit 46i sets the maximum value and the minimum value of the carrier as the limit values related to the modulation rate command of the power source selected as the priority by the priority modulation rate selection unit 46h. According to such a configuration, the modulation rate command selected as the priority can take the maximum amplitude, and the maximum output power from the power supply can be given to the motor 30.

  In addition, when the modulation rate command corresponding to the first power supply 20 is selected as a priority, the modulation rate limiting unit 46i has an upper limit of the carrier maximum value and the first value as a limit value related to the modulation rate command of the second power supply 21. The smaller one of the offset modulation rate commands mu1_off to mw1_off of one power source 20 is set, and the minimum value of the carrier is set as the lower limit of the limit value. According to this configuration, it is possible to make maximum use of a portion that is not used by the modulation rate command selected as priority. Therefore, the output range to the motor 30 or the voltage distribution ratio setting range can be maximized.

  In addition, when the modulation rate command corresponding to the second power source 21 is selected as a priority, the modulation rate limiting unit 46i sets the maximum value of the carrier as an upper limit as the limit value related to the modulation rate command of the first power source 20. Then, the lower one of the minimum carrier value and the offset modulation rate command mu2_off to mw2_off of the second power source 21 is set to the lower limit. According to this configuration, it is possible to make maximum use of a portion that is not used by the modulation rate command selected as priority. Therefore, the output range to the motor 30 or the voltage distribution ratio setting range can be maximized.

(Second Embodiment)
Hereinafter, a control system according to the second embodiment of the present invention will be described. The control system according to the second embodiment is different from that of the first embodiment in the configuration of the voltage distribution command generation unit 44 in the control unit 40. The redundant description of the configuration common to the first embodiment will be omitted, and the following description will focus on the differences.

  FIG. 10 is an explanatory diagram schematically illustrating the configuration of the voltage distribution command generation unit 44 according to the second embodiment. The voltage distribution command generation unit 44 has a function of outputting the voltage distribution command rto_cmd to the voltage distribution unit 45 based on the target distribution ratio rto * input from the outside. In this embodiment, the voltage distribution calculation unit 44a And a distribution range calculation unit 44b and a voltage distribution command limiting unit 44c.

The voltage amplitude calculator 44a calculates the voltage amplitude Vpk of the output voltage command values vu *, vv *, vw * for driving the motor 30 from the d-axis and q-axis voltage command values Vd *, Vq *. The voltage amplitude Vpk is calculated based on the following equation, and the calculation result is output to the distribution range calculation unit 44b.

  The distribution range calculation unit 44b calculates the voltage distribution command upper limit rto_upp and the voltage distribution command lower limit rto_low based on the voltage amplitude Vpk and the first and second power supply voltages Vdc1 and Vdc2. Specifically, the distribution range calculation unit 44b calculates the upper and lower limit ranges in which the modulation rate commands for the power supplies 20 and 21 do not exceed “1”. In addition, the distribution range calculation unit 44b, when one of the first and second power supplies 20, 21 outputs more power than the motor 30 and the other power supply charges the surplus power, An upper and lower limit range in which the modulation rate command related to the first power supply 20 does not become less than the modulation rate command related to the second power supply 21 is calculated. Based on the calculated upper and lower limit ranges, a voltage distribution command upper limit rto_upp and a voltage distribution command lower limit rto_low are calculated.

First, a calculation method in a range in which the modulation rate command for each of the power supplies 20 and 21 is “1” will be described. First, the upper limit range rto_upp1 of the voltage distribution command when the modulation factor command becomes “1” at the first power supply voltage Vdc1 is calculated by the following equation. The upper limit range rto_upp1 is used to calculate how many times the voltage amplitude Vpk can be output by the first power supply 20.

Next, the lower limit range rto_low1 of the voltage distribution command when the modulation factor becomes “1” at the power supply voltage Vdc2 of the second power supply 21 is calculated by the following equation. This lower limit range rto_low1 calculates how many times the voltage amplitude Vpk is output when the modulation factor command is up to 1 when only the second power supply 21 is used, and subtracts this calculated value from “1”.

  Second, when one power source outputs more power than the motor 30 and the other power source charges the surplus power, the modulation rate command for the first power source 20 is modulated by the second power source 21. The calculation method of the range which does not become less than rate command is demonstrated. Here, the range is set so that the sum of the amplitudes of the modulation rate commands does not exceed “0.5”.

First, when the first power supply 20 outputs more power than the power of the motor 30, the upper limit range rto_upp2 of the voltage distribution command satisfies the relationship expressed by the following equation (1). From this equation (1), the upper limit range rto_upp2 of the voltage distribution command is calculated by the following equation (2).

Next, when the first power supply 20 charges surplus power, the lower limit range rto_low2 of the voltage distribution command satisfies the relationship expressed by the following equation (1). From this equation (1), the lower limit range rto_low2 of the voltage distribution command is calculated by the following equation (2).

  The distribution range calculation unit 44b sets the minimum value of the upper limit ranges rto_upp1 and rto_upp2 of the voltage distribution command obtained by the above calculation as the voltage distribution command upper limit rto_upp. Further, the distribution range calculation unit 44b sets the maximum value of the upper limit ranges rto_low1 and rto_low2 of the voltage distribution command obtained by the above calculation as the voltage distribution command lower limit rto_low.

  The voltage distribution command limiter 44c receives a target distribution ratio rto * from the outside, and a voltage distribution command lower limit rto_low and a voltage distribution command upper limit rto_upp from the distribution range calculation unit 44b. The voltage distribution command restriction unit 44c compares the target distribution ratio rto * with the ranges of the voltage distribution command lower limit rto_low and the voltage distribution command upper limit rto_upp. When the target distribution ratio rto * deviates from this upper / lower limit range, the voltage distribution command limiter 44c limits the target distribution ratio rto * with the upper / lower limit range as a limit, and outputs the limited value as the voltage distribution command rto_cmd. When the target distribution ratio rto * is within the upper and lower limit range, the voltage distribution command restriction unit 44c outputs the target distribution ratio rto * as the voltage distribution command rto_cmd.

  As described above, in the present embodiment, the voltage distribution command generation unit 44 maintains a relationship in which the final modulation rate commands mu1_cmd to mw1_cmd of the first power supply 20 are equal to or higher than the final modulation rate commands mu2_cmd to mw2_cmd of the second power supply 21. Is calculated (distribution range calculation unit 44b), the target distribution ratio rto * is limited to the calculated distribution range, and a voltage distribution command rto_cmd is output (voltage distribution command limiting unit 44c). According to such a configuration, it is difficult for the modulation rate limiting unit 46i to be restricted, and it is difficult for harmonic components to be superimposed on the modulation rate waveform. As a result, torque fluctuation and the like are less likely to occur, and the motor 30 can be driven stably without increasing the loss in the motor 30.

(Third embodiment)
Hereinafter, a control system according to a third embodiment of the present invention will be described. The control system according to the third embodiment differs from that of the first embodiment in the configuration of the power converter 10 and the control method of the control unit 40 in accordance with the difference in this configuration. The redundant description of the configuration common to the first embodiment will be omitted, and the following description will focus on the differences.

  FIG. 11 is an explanatory diagram schematically illustrating a system configuration centering on the power converter 10 of the power conversion device according to the third embodiment. The power converter 10 is connected to the first to third power supplies 20 to 22 connected in series with each other, and generates an output voltage pulse from the output voltage of each of the power supplies 20 to 22 by being controlled by the control unit 40. To do. And the power converter 10 produces | generates the drive voltage of the motor 30 which is a load with this output voltage pulse.

  Here, the first to third power sources 20 to 22 are independent DC power sources. Each of the power supplies 20 to 22 is connected to the positive electrode of the lower power supply (for example, the first power supply 20) and the negative electrode of the upper power supply (for example, the second power supply 21), so that the lowest power supply is used. Upper power supplies 20 to 22 are connected in series with each other. As each power supply 20-22, batteries, such as a nickel metal hydride battery or a lithium ion battery, can be used, for example. The positive electrode bus 76 is connected to the positive electrode of the third power source 22 located at the highest level, and the negative electrode bus 77 is connected to the negative electrode of the first power source 20 located at the lowest level. The first common bus 78 is connected to the positive electrode of the first power supply 20 and the negative electrode of the second power supply 21 located above the first power supply 20, and the negative electrode of the third power supply 20 is located below the negative electrode. A second common bus 79 is connected to the positive electrode of the second power supply 21. A smoothing capacitor is provided between the negative bus 77 and the first common bus 78, between the first common bus 78 and the second common bus 79, and between the second common bus 79 and the positive bus 76. 73 to 75 are provided.

  In the power converter 10, switching means capable of controlling bidirectional conduction is connected between the first common bus 78 and the output terminals corresponding to the three phases. Each switch means is configured by connecting a pair of semiconductor switches (for example, switching elements such as NPN type transistors) 61a, 61b to 63a, 63b in reverse parallel to each other. Switching means capable of controlling bidirectional conduction is connected between the second common bus 79 and the output terminals corresponding to the three phases. Each switch means is configured by connecting a pair of semiconductor switches (for example, switching elements such as NPN type transistors) 64a, 64b to 66a, 66b in antiparallel with each other.

  In addition, switch means is connected between the positive electrode bus 76 and the output terminals corresponding to the three phases, like the generally known upper arm of the three-phase inverter. Each switch means is mainly composed of semiconductor switches (for example, switching elements such as NPN type transistors) 67a to 69a, and each switch (transistor) 67a to 69a is a free-wheeling diode between the collector and the emitter. 67b to 69b are connected in reverse parallel. Switch means corresponding to each phase is connected between the negative electrode bus 77 and each output terminal corresponding to the three phases, like a generally known lower arm of a three-phase inverter. Each switch means is mainly composed of semiconductor switches (for example, switching elements such as NPN type transistors) 70a to 72a, and each switch (transistor) 70a to 72a is a freewheeling diode between the collector and the emitter. 70b to 72b are connected in reverse parallel. The on / off state of these semiconductor switches (hereinafter simply referred to as “switches”) is controlled through a drive signal output from the control unit 40.

  FIG. 12 is an explanatory diagram showing final modulation rate commands related to the first to third power supplies 20 to 22. The control unit 40 indicates the output ratio of the three-phase output voltage command values vu *, vv *, vw * and the first to third power supplies 20 to 22 according to the same control concept as in the first embodiment. Based on the target distribution ratio rto *, a final modulation rate command for each phase related to the first to third power supplies 20 to 22 is calculated. Hereinafter, only the U phase will be described, but the same applies to the other phases. As shown in the figure, when three first to third power supplies 20 to 22 are connected in series, the final modulation rate command mu1_cmd of the lowest first power supply 20 and the second power supply 21 higher than that. The final modulation rate command mu2_cmd and the final modulation rate command mu3_cmd of the uppermost third power supply 22 are arranged in this order from the top to the bottom of the carrier. It is possible to distribute power and move power between the power sources 20 to 22 within a range where the final modulation factor commands mu1_cmd to mu3_cmd do not intersect.

  FIG. 13 is an explanatory diagram of an on / off state of each switch of the power converter 10 according to the third embodiment. The control unit 40 compares the final modulation rate command for each power source 20 to 22 with the carrier to generate a conduction signal, and generates a conduction signal for setting the on / off state of each switch of the power converter 10 through this conduction signal. . Hereinafter, only the U phase will be described, but the same applies to the other phases.

  First, consider a case in which an inverter circuit composed only of the first power supply 20 is driven by comparing the carrier with the final modulation factor command mu1_cmd of the first power supply 20. When the final modulation rate command mu1_cmd is smaller than the carrier (mu1_cmd <carrier), the control unit 40 controls the switch 61a to be off and the switch 70a to be on. On the other hand, when the final modulation rate command mu1_cmd is larger than the carrier (mu1_cmd> carrier), the switch 61a is controlled to be on and the switch 70a is controlled to be off.

  Next, consider a case in which an inverter circuit composed of only the second power supply 21 is driven by comparing the carrier with the final modulation factor command mu2_cmd of the second power supply 21. When the final modulation rate command mu2_cmd is smaller than the carrier (mu2_cmd <carrier), the control unit 40 controls the switch 64a to be turned off and the switch 61b to be turned on. On the other hand, when the final modulation rate command mu2_cmd is larger than the carrier (mu2_cmd> carrier), the switch 64a is controlled to be on and the switch 61b is controlled to be off.

  Consider a case in which an inverter circuit composed only of the third power supply 22 is driven by comparing the carrier with the final modulation factor command mu3_cmd of the third power supply 22. When the final modulation rate command mu3_cmd is smaller than the carrier (mu3_cmd <carrier), the control unit 40 controls the switch 67a to be turned off and the switch 64b to be turned on. On the other hand, when the final modulation rate command mu2_cmd is larger than the carrier (mu2_cmd> carrier), the switch 67a is controlled to be on and the switch 64b is controlled to be off.

  As can be seen from FIG. 13, in the present embodiment, the operation of the U-phase switches 61a, 70a, 64a, 61b, 67a, 64b causes the following (1) from the following in one PWM period, that is, one carrier period. The state of (6) is sequentially set.

(1) Off switch 61a of all power supplies 20-22: off, switch 70a: on, switch 64a: off, switch 61b: on, switch 67a: off, switch 64b on (2) Only the first power supply 20 at the lowest level ON switch 61a: ON, switch 70a: OFF, switch 64a: OFF, switch 61b: ON, switch 67a: OFF, switch 64b: ON (3) The upper second power supply during the ON period of the first power supply 20 21 ON switch 61a: ON, switch 70a: OFF, switch 64a: ON, switch 61b: OFF, switch 67a: OFF, switch 64b: ON (4) During the ON period of the first and second power supplies 20, 21 On switch 61a of the uppermost third power supply 22: ON, switch 70a: OFF, switch 64a: ON, switch 6 b: OFF, switch 67a: ON, switch 64b: off (5) the third power supply 22 only off the top (the first and second power supply 20, 21 on)
Switch 61a: On, Switch 70a: Off, Switch 64a: On, Switch 61b: Off, Switch 67a: Off, Switch 64b: On (6) Only the second and third power supplies 21 and 22 at the top and its subordinates are off (The first power supply 20 is turned on)
Switch 61a: On, Switch 70a: Off, Switch 64a: Off, Switch 61b: On, Switch 67a: Off, Switch 64b: On As can be seen from the series of switch operations, the motors from each power source 20-22 in one cycle of the carrier Control for each switch connected to 30 can be shown as follows. Specifically, the switch 64a connected from the second power supply 21 to the motor 30 is turned on during the conduction period of the switch 61a connected from the first power supply 20 to the motor 30. Further, the switch 67a connected from the third power supply 22 to the motor 30 is turned on during the conduction period of the switch 64a connected from the second power supply 21 to the motor 30. By this switch control, the output voltage pulse in one cycle of the carrier is the negative voltage (“0”) of the lowest first power supply 20, the positive voltage (“Vdc1”) of the first power supply 20, and the first The positive voltage (“Vdc1 + Vdc2”) output by the second power supply 21 during the positive voltage output period of the power supply 20 and the third power supply 22 during the positive voltage output period of the first and second power supplies 20, 21 It is composed of a positive voltage to be output (“Vdc1 + Vdc2 + Vdc3”) and has a three-stage convex waveform.

  Thus, in the present embodiment, in the power converter 10, as control for each switch in one cycle of the carrier, from the lowest power supply (first power supply 20) to the highest power supply (third power supply 22), During the conduction period of the switch (switch 61a (or switch 64a)) corresponding to the lower power supply (first power supply 20 (or second power supply 21)), the upper power supply (second power supply 21 (or second power supply 21) is used. Switch (switch 64a (or switch 67a)) corresponding to the third power source 22)) is turned on. Under the control of the power converter 10, the output voltage pulse in one cycle of the carrier is the negative voltage (“0”) of the first power supply 20 and the highest power supply from the lowest power supply (first power supply 20). (Second power supply) and the positive voltage ("Vdc1", "Vdc1 + Vdc2", "Vdc1 + Vdc2 + Vdc3") output by each of the power supplies 20 to 22 during the positive voltage output period of the power supply lower than itself. According to such a configuration, high-speed power distribution can be realized, and power can be supplied to the motor 30 while controlling both the power supplies 20 and 21 simultaneously. By doing in this way, even if it is a case where two or more power supplies 20-22 are connected and used in series, electric power distribution and the electric power movement between power supplies are attained.

  Even when two or more power supplies 20 to 22 are connected in series, as in the first embodiment, “during the conduction period of the switch” and “during the positive voltage output period of the lower power supply” The entire range from the start point to the end point of the period is included.

(Fourth embodiment)
Hereinafter, a control system according to a fourth embodiment of the present invention will be described. The control system according to the fourth embodiment is different from that of the first embodiment in the configuration of the modulation rate command generation unit 46 in the control unit 40, specifically, the final modulation rate command generation unit 46b. . The redundant description of the configuration common to the first embodiment will be omitted, and the following description will focus on the differences.

  FIG. 14 is an explanatory diagram schematically showing the configuration of the final modulation rate command generation unit 46b. The final modulation rate command generator 46b can compare the final modulation rate commands mu1_cmd to mw2_cmd of the first and second power supplies 20 and 21 with the carrier, and the final modulation rate commands mu1_cmd to mw1_cmd of the first power supply 20 Is set to be equal to or higher than the final modulation rate commands mu2_cmd to mw2_cmd of the second power supply 21, and the initial modulation rate commands mu1 to mw2 are offset, whereby the final modulation rate commands mu1_cmd to Generate mw2_cmd. The final modulation rate command generation unit 46b of the present embodiment includes a loss definition unit 46j, a conduction time setting unit 46k, a modulation rate amplitude calculation unit 46l, a power supply voltage comparison unit 46m, an offset value generation unit 46n, and an offset process. Part 46o.

  The loss defining unit 46j defines a switch that generates a large loss in the power converter 10. In the conduction time setting unit 46k, the conduction time of the switch defined in the loss definition unit 46j is set. For example, the loss definition unit 46j identifies a switch having a large electrical loss depending on the detected temperature by detecting the temperature of each switch. In addition, the conduction time setting unit 46k sets a time for which only a switch having a large electrical loss is conducted from the temperature based on a preset map or calculation formula.

  The modulation factor amplitude calculation unit 46l calculates the first modulation factor amplitude mu1_pk and the second modulation factor amplitude mu2_pk in the same manner as the modulation factor amplitude calculation unit 46e shown in the first embodiment. The power supply voltage comparison unit 46m compares the magnitudes of the first power supply voltage Vdc1 and the second power supply voltage Vdc2.

  The offset value generation unit 46n includes a conduction time set in the conduction time setting unit 46k, a voltage distribution command rto_cmd, first and second modulation factor amplitudes mu1_pk and mu2_pk calculated by the modulation factor amplitude calculation unit 46l, Based on the comparison result of the power supply voltage comparison unit 46m, offset values m1_off and m2_off related to the first and second power supplies 20 and 21 are calculated, respectively. A method for calculating the offsets m1_off and m2_off will be described later.

  The individual offset values m1_off and m2_off generated in this way are output to the offset processing unit 46o. The offset processing unit 46o calculates the final modulation rate commands mu1_cmd to mw1_cmd of each phase by adding the offset value m1_off to the initial modulation rate commands mu1 to mw1 of each phase with respect to the first power supply 20, respectively. Further, the offset processing unit 46o calculates the final modulation rate commands mu2_cmd to mw2_cmd of each phase by adding the offset value m2_off to the initial modulation rate commands mu2 to mw2 of the respective phases with respect to the second power supply 21.

  Hereinafter, a method for calculating the offsets m1_off and m2_off will be described by exemplifying various cases. In the present embodiment, the loss defining unit 46j defines that the loss of the switch means (specifically, the switches 1a and 1b) connected from the positive electrode of the first power supply 20 to the motor 30 is large. In the conduction time setting unit 46k, a predetermined time for shortening the conduction time of the switch means (switches 1a and 1b) is set.

(Case 1: Voltage distribution command rto_cmd is “0” or more and “1” or less (the first and second power supplies 20 and 21 are powered or regenerated, respectively, or one of the power supplies 20 and 21 stops output and the other power supply 20 , 21 is power running or regeneration))
The offset value generation unit 46n compares the first modulation factor amplitude mu1_pk with the second modulation factor amplitude mu2_pk. The offset value generation unit 46n refers to the comparison result, and then sets the carrier upper limit (the upper limit of the carrier amplitude) Ucarr, the carrier lower limit (the lower limit of the carrier amplitude) Lcarr, the first and second modulation factor amplitudes mu1_pk, mu2_pk, and the initial value. Based on the modulation rate commands mu1 to mw2, offset values m1_off and m2_off are respectively generated.

When the first modulation factor amplitude mu1_pk is smaller than the second modulation factor amplitude mu2_pk (mu1_pk <mu2_pk), the individual offset values m1_off and m2_off are generated as shown in the following equation.

When the switching operation of the corresponding switch means is not performed, the individual offset values m1_off and m2_off are generated as shown in the following expression.

On the other hand, when the first modulation factor amplitude mu1_pk is larger than the second modulation factor amplitude mu2_pk (mu1_pk> mu2_pk), the individual offset values m1_off and m2_off are generated as shown in the following equation.

When the switching operation of the corresponding switch means is not performed, the individual offset values m1_off and m2_off are generated as shown in the following expression.

(Case 2: Voltage distribution command rto_cmd is less than “0” or larger than “1” (one power source 20, 21 is powering and the other power source 20, 21 is regenerating))
The offset value generation unit 46n compares the first power supply voltage Vdc1 with the second power supply voltage Vdc2, and determines the power supplies 20 and 21 having higher voltages. Based on the determination result, the offset value generation unit 46n generates offset values m1_off and m2_off for further reducing the switching loss from the carrier upper limit Ucarr, the carrier lower limit Lcarr, and the initial modulation rate commands mu1 to mw2.

When the first power supply voltage Vdc1 is smaller than the second power supply voltage Vdc2 (Vdc1 <Vdc2), when the switching operation of the corresponding switch means is not performed, the individual offset values m1_off and m2_off are expressed by the following equations: Is generated as follows.

Further, when always switching the corresponding switch means, the individual offset values m1_off and m2_off are generated as shown in the following equation.

On the other hand, when the first power supply voltage Vdc1 is equal to or higher than the second power supply voltage Vdc2 (Vdc1 ≧ Vdc2), when the switching operation of the corresponding switch means is not performed, the individual offset values m1_off and m2_off are: It is generated as shown in the following formula.

Further, when always switching the corresponding switch means, the individual offset values m1_off and m2_off are generated as shown in the following equation.

  In the above calculation, the offset value generation unit 46n outputs a calculation result including the initial modulation rate commands mu2 to mw1 as unknowns to the offset processing unit 46o. However, the initial modulation rate commands mu2 to mw1 of the power supplies 20 and 21 may be input to the offset value generation unit 46n as calculation parameters.

  As described above, in the present embodiment, the final modulation rate command generation unit 46b can compare the final modulation rate commands of the first and second power sources 20 and 21 with the carrier, and the final modulation rate command of the first power source 20 can be compared. Offset processing is performed so that the rate commands mu1_cmd to mw1_cmd are equal to or greater than the final modulation rate commands mu2_cmd to mw2_cmd of the second power supply 21. According to such a configuration, the final modulation rate commands mu1_cmd to mw1_cmd of the first power supply 20 are relatively offset so that they are equal to or greater than the final modulation rate commands mu1_cmd to mw1_cmd of the second power supply 20. Thereby, the conduction time of the switch 1a corresponding to the first power supply 20 is set to be longer than the conduction time of the switch 4a corresponding to the second power supply 21. Therefore, it is possible to supply power to the motor 30 while suppressing abnormalities in the switching pattern and stably controlling both the power supplies 20 and 21 simultaneously. Further, the output voltage command values vu *, vv *, and vw * are distributed according to the voltage distribution command rto_cmd, and initial modulation rate commands mu1 to mw2 are generated thereon. Therefore, the output power of each power source 20 and 21 can be controlled with an arbitrary value, and the power can be transferred between the power sources 20 and 21 by the voltage distribution command rto_cmd.

  In the present embodiment, the final modulation rate command generation unit 46b is set with a predetermined time during which only a switch with a large electrical loss is conducted, and based on the set predetermined time, the first power supply 21 Offset processing is performed in a range where the final modulation rate commands mu1_cmd to mw1_cmd are equal to or greater than the final modulation rate commands mu2_cmd to mw2_cmd of the second power supply 21. This is equivalent to setting the time for current to flow through a switch with a large loss. Thereby, it becomes possible to control the conduction loss generated in the switch having a large loss, and the loss can be reduced as a whole.

  Further, the final modulation rate command generation unit 46b follows the above-described calculation, so that the final modulation rate commands mu1_cmd to mw1_cmd of the first power supply 20 and the final modulation rate commands mu2_cmd to mw2_cmd of the second power supply 21 are obtained. Thus, the offset process is performed so as to coincide with each other at a time equal to or less than 1/3 of the fundamental wave period with respect to the initial modulation rate commands mu1 to mu2. According to such a configuration, by matching the final modulation factor commands mu1_cmd to mw2_cmd of the power supplies 20 and 21, there is no time for only the switch means used in common when the power of the two power supplies 20 and 21 is distributed. Since the common switch means is composed of bidirectional switches 11a, 11b to 13a, 13b, it is a switch means in which the loss usually increases. Since there is no time for only the common switch means to conduct, the conduction loss can be further reduced.

  Further, in the present embodiment, the final modulation rate command generation unit 46b is configured such that the first and second power sources 20, 21 are powering or regenerating, respectively, or one power source is stopping output and the other power source is powering or regenerating. When the first modulation factor amplitude mu1_pk is smaller than the second modulation factor amplitude mu2_pk, the upper part of the final modulation factor commands mu1_cmd to mw1_cmd of the first power source 20 and the final modulation factor commands mu2_cmd to mw2_cmd of the second power source 21 The offset process is performed so as to match the upper part of (see FIG. 15A). According to this configuration, it is possible to output electric power without reversing the vertical relationship between the final modulation rate commands mu2_cmd to mw2_cmd of the second power supply 21 and the final modulation rate commands mu1_cmd to mw1_cmd of the first power supply 20. . Moreover, the conduction loss in the switch means can be reduced. Note that FIG. 15 shows the final modulation rate command mu1_cmd of the first power supply 20 focusing on the U phase and the final modulation rate command mu2_cmd of the second power supply 21 (the same applies in FIG. 15).

  In the present embodiment, the final modulation rate command generation unit 46b is configured such that the first and second power sources 20, 21 are powering or regenerating, respectively, or one of the power sources is stopped and the other power source is powering or regenerating. When the first modulation factor amplitude mu1_pk is larger than the second modulation factor amplitude mu2_pk, the lower part of the final modulation factor commands mu1_cmd to mw1_cmd of the first power source 20 and the final modulation factor commands mu2_cmd to mw2_cmd of the second power source 21 The offset processing is performed so as to match the lower part (see FIG. 15B). According to this configuration, it is possible to output electric power without reversing the vertical relationship between the final modulation rate commands mu2_cmd to mw2_cmd of the second power supply 21 and the final modulation rate commands mu1_cmd to mw1_cmd of the first power supply 20. . Moreover, the conduction loss in the switch means can be reduced.

  In this case, the final modulation rate command generation unit 46b performs a part of the time when the final modulation rate commands mu1_cmd to mw1_cmd of the first power supply 20 and the final modulation rate commands mu2_cmd to mw2_cmd of the second power supply 21 match. Then, an offset process is performed so that the switch means does not perform the switching operation (see FIGS. 15A and 15B). According to such a configuration, the switching loss can be reduced in addition to the conduction loss by not switching between conduction and cutoff during the coincidence time.

  Further, in the present embodiment, when one power source is powering and the other power source is regenerative, the final modulation rate command generation unit 46b includes the upper part of the final modulation rate commands mu1_cmd to mw1_cmd of the first power source 20, The offset processing is performed so as to match the lower portions of the final modulation rate commands mu2_cmd to mw2_cmd of the power source 21 (see FIGS. 15C and 15D). According to this configuration, it is possible to output electric power without reversing the vertical relationship between the final modulation rate commands mu2_cmd to mw2_cmd of the second power supply 21 and the final modulation rate commands mu1_cmd to mw1_cmd of the first power supply 20. . Moreover, the conduction loss in the switch means can be reduced.

  In this case, when the first power supply voltage Vdc1 is smaller than the second power supply voltage Vdc2, the final modulation factor command generation unit 46b includes a switch means that connects the positive electrode of the second power supply 21 to the load. Offset processing is performed so as to cut off the time of one carrier period or more and not more than 1/3 period of the fundamental wave period for each of the initial modulation rate commands mu1 to mw2 (see FIG. 15C). According to such a configuration, switching between conduction / cutoff of a power supply having a high power supply voltage is not performed, and thus switching loss can be more effectively reduced.

  Further, the final modulation factor command generator 46b is configured such that when the first power supply voltage Vdc1 is equal to or higher than the second power supply voltage Vdc2, the switch means for connecting the positive electrode of the first power supply 20 to the load is the first carrier 1 The offset processing is performed so that the continuity is maintained for a period of time equal to or longer than the period and equal to or less than 1/3 of the fundamental wave period related to each of the initial modulation rate commands mu1 to mw2. According to such a configuration, switching between conduction / cutoff of a power supply having a high power supply voltage is not performed, and thus switching loss can be more effectively reduced.

(Fifth embodiment)
Hereinafter, a control system according to a fifth embodiment of the present invention will be described. The control system according to the fifth embodiment is different from that of the first embodiment in the configuration of the modulation rate command generation unit 46 in the control unit 40, specifically, the final modulation rate command generation unit 46b. . The redundant description of the configuration common to the first embodiment will be omitted, and the following description will focus on the differences.

  FIG. 16 is an explanatory diagram schematically showing the configuration of the final modulation rate command generation unit 46b. The final modulation rate command generating unit 46b generates final modulation rate commands mu1_cmd to mw2_cmd based on the initial modulation rate commands mu1 to mw2. The final modulation rate command generation unit 46b of the present embodiment includes an offset value generation unit 46p and an offset processing unit 46q.

The offset value generation unit 46p uses the carrier upper limit (upper limit of carrier amplitude) Ucarr, the lower limit of carrier (lower limit of carrier amplitude) Lcarr, the initial modulation rate commands mu1 to mw2, and the first and second modulation rate amplitudes mu1_pk and mu2_pk. m1_off and m2_off are generated. Specifically, the offset value generation unit 46p calculates an offset value m1_off related to the first power supply 20 and an offset value m2_off related to the second power supply 21 as shown in the following equation. Here, the first and second modulation factor amplitudes mu1_pk and mu2_pk can be obtained by the same method as the processing executed by the modulation factor amplitude calculation unit 46e shown in the first embodiment.

  The individual offset values m1_off and m2_off generated in this way are output to the offset processing unit 46q. The offset processing unit 46q calculates the final modulation rate commands mu1_cmd to mw1_cmd of each phase by adding the offset value m1_off to the initial modulation rate commands mu1 to mw1 of the respective phases with respect to the first power supply 20. Further, the offset processing unit 46o calculates the final modulation rate commands mu2_cmd to mw2_cmd of each phase by adding the offset value m2_off to the initial modulation rate commands mu2 to mw2 of the respective phases with respect to the second power supply 21.

  Here, FIG. 17 is an explanatory diagram showing the relationship between the carrier and the final modulation rate commands mu1_cmd and mu2_cmd of the power supplies 20 and 21. FIG. Note that FIG. 17 illustrates the final modulation rate command mu1_cmd (upper waveform) of the first power supply 20 and the final modulation rate command mu2_cmd (lower waveform) of the second power supply 21 related to the U phase. As described above, according to the present embodiment, the switch means connected to the load from the positive electrodes of the power supplies 20 and 21 by the final modulation rate command generation unit 46b relates to the initial modulation rate commands mu1 to mw2 for one or more cycles of the carrier. Offset processing is performed so that the switching operation is not performed in a time that is 1/3 or less of the fundamental wave period. According to such a configuration, since there is a time during which the conduction / interruption switching operation is not performed, it is possible to supply power to the motor 30 while reducing the switching loss that occurs at the time of switching.

(Sixth embodiment)
Hereinafter, a control system according to a sixth embodiment of the present invention will be described. The control system according to the sixth embodiment is different from that of the first embodiment in the configuration of the conduction signal generator 47 in the control unit 40. The redundant description of the configuration common to the first embodiment will be omitted, and the following description will focus on the differences.

  The conduction signal generation unit 47 sets the on / off state of each switch of the power converter 10 based on the final modulation rate commands mu1_cmd to mw2_cmd from the modulation rate command generation unit 46 and the carrier generated by the carrier generation unit 48. A conduction signal is generated. In the present embodiment, the carrier wave generation unit 48 generates a triangular wave having a lower limit “0” and an upper limit “1” as a carrier. In addition, a sawtooth wave can also be used for a carrier instead of a triangular wave.

  FIG. 18 is an explanatory diagram of an on / off state of each switch of the power converter 10 by the conduction signal generation unit 47 according to the sixth embodiment. The conduction signal generation unit 47 generates a conduction signal as a result of comparison between the final modulation factor commands mu1_cmd to mw2_cmd and the carrier, and controls the on / off state of each switch through the conduction signal. Hereinafter, only the U phase will be described, but the same applies to the other phases. Here, in FIG. 18, when the conduction signals relating to the respective switches 1a, 1b, 4a, 7a are at the high level, the respective switches 1a, 1b, 4a, 7a are turned on. Vun indicates a U-phase output voltage.

  First, consider a case in which an inverter circuit (see FIG. 3B) configured only by the first power supply 20 is driven by comparing the carrier with the final modulation factor command mu1_cmd of the first power supply 20. The conduction signal generation unit 47 has a final modulation rate command mu1_cmd of the first power supply 20 equal to or lower than the carrier, and a final modulation rate command mu1_cmd of the first power supply 20 is the final modulation rate command mu2_cmd of the second power supply 21. If this is the case (mu2_cmd ≦ mu1_cmd ≦ carrier), the switch 1a is controlled to be off and the switch 7a is controlled to be on. The conduction signal generation unit 47 also determines that the final modulation factor command mu1_cmd of the first power supply 20 is larger than the carrier, and this carrier is larger than the final modulation factor command mu2_cmd of the second power supply 21 (mu2_cmd <carrier <Mu1_cmd), switch 7a is turned off, and switch 1a is turned on. Further, the conduction signal generation unit 47 has a final modulation rate command mu1_cmd of the first power supply 20 that is equal to or greater than a final modulation rate command mu2_cmd of the second power supply 21, and a final modulation rate command mu2_cmd of the second power supply 21. Is larger than the carrier (carrier <mu2_cmd ≦ mu1_cmd), the switches 1a and 4a are respectively controlled to be turned off.

  Next, consider a case where an inverter circuit (see FIG. 3C) configured only by the second power supply 21 is driven by comparing the carrier with the final modulation factor command mu2_cmd of the second power supply 21. When the final modulation factor command mu2_cmd is smaller than the carrier (mu2_cmd <carrier), the conduction signal generation unit 47 controls the switch 1b to be on and the switch 4a to be off. On the other hand, when the final modulation rate command mu2_cmd is larger than the carrier (mu2_cmd> carrier), the switch 1b is controlled to be off and the switch 4a is controlled to be on.

  As described above, according to the present embodiment, the conduction signal generation unit 47 conducts the switch unit corresponding to the first power source 20 and conducts the switch unit corresponding to the second power source 21 during the conduction period. The switch means corresponding to the first power supply 20 is cut off on condition that the switch means corresponding to the second power supply 21 is in a conduction period. According to such a configuration, when a switching element having a current-type gate is used, current is not supplied to the switching element on the first power supply 20 side by blocking the gate signal. Thereby, the loss at the gate can be reduced.

  In the first to sixth embodiments described above, the above-described control method may be switched to the control method as described below. This control method includes a carrier corresponding to the first power supply 20 and a carrier corresponding to the second power supply 21. Here, the lower end of the carrier corresponding to the first power source 20 is 0, the upper end thereof is the voltage value of the first power source 20, and the lower end of the carrier corresponding to the second power source 21 is the first power source 20. The voltage value, the upper end of which is the value obtained by adding the voltages of the first and second power sources 20 and 21. Then, an offset value is added to the output voltage command values vu *, vv *, vw * to be applied to the motor 30, and the carrier corresponding to the second power source 21 and the carrier corresponding to the first power source 20 are compared in any part. The switch means is switched depending on whether or not power is distributed. In this case, when switching the control method, for example, when the voltage distribution command rto_cmd is 0 to 1, the latter control method is used, and when the voltage distribution command rto_cmd is less than 0 or exceeds 1, it is shown in each embodiment. Use control techniques. Even when the voltage distribution command rto_cmd is 0 to 1, the control method shown in each embodiment may be used when control with reduced power pulsation is required.

(Seventh embodiment)
Hereinafter, a control system according to a seventh embodiment of the present invention will be described. The control system according to the seventh embodiment is different from that of the first embodiment in that power is generated by receiving external torque and this generated power is used as one of DC power sources. The redundant description of the configuration common to the first embodiment will be omitted, and the following description will focus on the differences.

  FIG. 19 is an explanatory diagram schematically illustrating the overall configuration of a control system to which the power conversion device according to the seventh embodiment is applied. In the present embodiment, an electric motor control system applied to a drive motor for an electric vehicle will be described. This electric motor control system is affirmed mainly by the power converter 10, the motor 30, and the first and second control units 40 and 50.

  FIG. 20 is an explanatory diagram schematically showing a system configuration centering on the power converter 10. The power converter 10 is connected to a plurality of power supplies connected in series with each other, and is a serial conversion device that generates output voltage pulses from the output voltage of each power supply by being controlled by the first control unit 40. . And the power converter 10 produces | generates the drive voltage of the motor 30 which is a load with this output voltage pulse.

  In the present embodiment, a plurality of power sources are a power source (hereinafter referred to as “power generation power source”) formed by rectifying the power generated by the generator 23 by an inverter (generated power converter) 23, a nickel hydrogen battery, or a lithium ion battery. It is comprised with the 2nd power supply 21 comprised with batteries, such as a battery. Here, the power generation source (the generator 23 and the inverter 24) and the second power source 21 function as independent DC power sources, and are connected in series with each other. The power generation power source is a power source corresponding to the first power source in the first embodiment.

  The generator 23 includes, for example, a plurality of phase windings that are star-connected around a neutral point (in this embodiment, three phase windings including a U-phase winding, a V-phase winding, and a W-phase winding). Is a three-phase AC synchronous motor. When the rotor is rotated by an external force, the generator 23 functions as a generator by generating an electromotive force at both ends of the stator winding. The inverter 24 converts the three-phase AC power generated by the generator 23 into DC power, and is mainly composed of upper and lower arms provided corresponding to the respective phases of the generator 23. Each arm is composed of a switching element such as an NPN transistor and a reflux diode connected in reverse parallel thereto.

  Referring to FIG. 19 again, the first control unit 40 is a control means for controlling the power converter 10, similarly to the control unit 40 shown in the first embodiment. The output torque of the motor 30 as a load is controlled. As the first control unit 40, a microcomputer mainly composed of a CPU, a ROM, a RAM, and an I / O interface can be used. The first control unit 40 performs calculations for controlling the power converter 10 according to a control program stored in the ROM. Then, the first control unit 40 outputs the control signal calculated by this calculation to the power converter 10.

  The second control unit 50 is a control unit that controls the inverter 24 (second control unit). As the second control unit 50, a microcomputer mainly composed of a CPU, a ROM, a RAM, and an I / O interface can be used. The second control unit 50 performs a calculation for controlling the inverter 24 in accordance with a control program stored in the ROM. Then, the second control unit 50 outputs a control signal calculated by this calculation to the inverter 24. The arithmetic processing by the second control unit 50 is performed by digital control having the same frequency as the carrier frequency (switching frequency) fc of the inverter 24.

  When the second control unit 50 grasps this functionally, the generated power control unit 51, the current control unit 52, the dq / 3 phase conversion unit 53, the modulation factor command generation unit 56, the PWM generation unit 57, and the carrier wave A generation unit 58 and a three-phase / dq conversion unit 59 are included.

  The generated power control unit 51 generates current commands id_g * and iq_g * for the generator 23 based on the generated power command P input from the external system and the rotor rotational speed ω of the generator 23. The current control unit 52 generates the dq axis voltage commands vd_g * and vq_g * so that the actual currents id_g and iq_g flowing through the generator 23 coincide with the current commands id_g * and iq_g *. The actual currents id_g and iq_g are generated by the three-phase / dq conversion unit 59 based on the U-phase current iu_g and the V-phase current iv_g flowing in the generator 23. The dq / 3-phase converter 53 converts the dq-axis voltage commands vd_g * and vq_g * into the three-phase output voltage commands Vu_g *, Vv_g * and Vw_g *.

  The modulation factor command generator 56 is calculated in the three-phase output voltage commands Vu_g *, Vv_g *, Vw_g * and the offset unit 46c (specifically, the offset value generator 46f) of the first control unit 40. Based on the first and second offset values m1_off and m2_off, the modulation factor commands mug_cmd to mwg_cmd for each phase are generated. Each modulation factor command mug_cmd to mwg_cmd takes a value in the range of “−1” to “1”. Details of the processing performed by the modulation factor command generation unit 56 will be described later.

  FIG. 21 is an explanatory diagram of an on / off state of the upper arm SWA and the lower arm SWB of the inverter 24. The PWM generation unit 57 compares the modulation factor commands mug_cmd to mwg_cmd of each phase with the triangular wave of the carrier cycle Ts (Ts = 1 / fc) generated by the carrier wave generation unit 58 to generate a PWM pulse. Also, the modulation factor commands mug_cmd to mwg_cmd are held at the carrier cycle. The carrier amplitude is in the range of “−1” to “1” in this embodiment. The upper and lower arms of each phase of the inverter 24 are driven using PWM pulses as gate signals. Specifically, when the modulation factor commands mug_cmd to mwg_cmd are smaller than the carrier, the PWM generator 57 controls the upper arm SWA to be turned off and the lower arm SWB to be turned on. In contrast, when the modulation factor commands mug_cmd to mwg_cmd are larger than the carrier, the PWM generation unit 57 controls the upper arm SWA to be turned on and the lower arm SWB to be turned off.

  The figure shows only the U phase, but the same applies to the other phases. As shown in the figure, the modulation rate command mug_cmd is offset as shown by a broken line and compared with the carrier so that the upper and lower arms SWA and SWB are not turned on simultaneously. Thereby, an offset time is set when the arms SWA and SWB are switched.

  FIG. 22 is a block diagram illustrating a configuration of the modulation factor command generation unit 56. Hereinafter, the modulation rate command generation unit 56 that is one of the features of the present embodiment will be described. The modulation rate command generation unit 56 includes an initial modulation rate command generation unit 56a and an offset unit 56b.

  The initial modulation rate command generator (power generation modulation rate generation means) 56a normalizes the three-phase output voltage commands Vu_g *, Vv_g *, and Vw_g * with the voltage Vdc1 of the power generation power source, that is, the output voltage command Vu_g *, Divide Vv_g * and Vw_g * by the voltage Vdc1. As a result, initial modulation rate commands mug to mwg for each phase are generated. The voltage Vdc1 of the power generation power source can be detected as the voltage of the smoothing capacitor 11 between the negative electrode bus 13 and the common bus 15.

  The offset unit (power generation offset means) 56b calculates final modulation rate commands mug_cmd to mwg_cmd based on the first and second offset values m1_off and m2_off and the initial modulation rate commands mug to mwg. Specifically, the offset unit 56b calculates the final modulation rate commands mug_cmd to mwg_cmd by adding the first offset value m1_off to each of the initial modulation rate commands mug to mwn.

  FIG. 23 is an explanatory diagram showing the relationship among final modulation factor commands mug_cmd to mwg_cmd of each phase, the fourth bus current Ib4, and the switching state of the upper arm of each phase. In the figure, the switch of each arm is turned on when the conduction signal is at a high level. Here, as shown in FIG. 20, the current on the load side of the DC bus 14 from the connection point with the smoothing capacitor 12 is the first bus current Ib1, and the DC bus 15 is connected with the smoothing capacitors 11 and 12 from the connection point. The current on the load side is the second bus current Ib2. Further, the current on the load side of the DC bus 13 with respect to the connection point with the smoothing capacitor 11 is a third bus current Ib3, and the current flowing through the DC bus 19 connected to the upper arm of the inverter 24 is a fourth bus current Ib4. To do. Here, the first to fourth bus currents Ib1 to Ib4 are positive when the current flows in the direction of the arrow in the figure (the direction toward the motor 30 side). Further, currents flowing through the U phase, V phase, and W phase of the generator 23 are defined as currents iu, iv, and iw, respectively. When the generator 23 is generating power, the polarity of the fourth bus current Ib4 is positive, but when the generator 23 is powering, that of the fourth bus current Ib4 is negative.

  First, in the inverter 24, in the section T1 in which all the three-phase upper arm switches are turned off, all the three-phase lower arm switches are turned on. In this case, the current flows back between the switch, the return diode, and the generator 23, and the fourth bus current Ib4 becomes “0”. Next, in the section T2, when the U phase is turned on, the current bus iu is supplied to the DC bus 19, and in the section T3, the V phase is turned on, so that the fourth bus current Ib4 is the sum of the currents iu and iv. . Next, in the section T4, when all the three phases are turned on, the current flows between the three-phase upper arm switch, the return diode, and the generator 23, so that the fourth bus current Ib4 is "0". Become. In each of the sections T5, T6, and T7, since the W-phase, V-phase, and U-phase switches are sequentially turned off, the same state as that in each of the sections T3, T2, and T1 described above is obtained.

  Here, when three of the final modulation factor commands mug_cmd to mwg_cmd are offset upward, the section T4 becomes longer and the sections T1 and T7 become shorter than in the case where they are not offset. The other sections T2, T3, T5, and T6 are the same. On the other hand, when three of the final modulation rate commands mug_cmd to mwg_cmd are offset downward, the section T4 is shortened and the sections T1 and T7 are lengthened as compared to the case where the offset is not offset. Thus, by offsetting the modulation factor, the phase of the fourth bus current Ib4 of the fourth DC bus can be variably set.

  In the control of the power converter 10, the carrier and the final modulation rate commands mu1_cmd to mw1_cmd related to the generated power source corresponding to the first power source and the final modulation rate commands mu2_cmd to mw2_cmd related to the second power source 21 are compared. FIG. 24 illustrates the relationship between the offset for the final modulation rate commands mu1_cmd to mw2_cmd and the first to third bus currents Ib1 to Ib3. In the figure, Vun to Vwn represent the output voltage of each phase of the power converter 10, that is, the voltage between the output terminal of each phase of the power converter 10 and the negative electrode of the smoothing capacitor 11.

  First, when the circuit on the power generation power source side switches, all the switches 7a, 8a, 9a are turned on in the section T1. Since the motor current circulates in the winding of the motor 30, the switches 7a, 8a, 9a and the antiparallel freewheeling diodes 7b, 8b, 9b, the first to third bus currents Ib1 to Ib3 become zero. In the section T2, since the switch 1a is turned on, the second bus current Ib2 becomes the current “iu”, and the third bus current Ib3 becomes “−iu”. In the section T3, since the switch 2a is turned on, the second bus current Ib2 is “iu + iv”, and the third bus current Ib3 is “−iu-iv”. In the section T4, since the switch 3a is turned on, the current flows back through the switches 1a, 2a, 3a, the windings of the motor 30 and the return diodes 7b, 8b, 9b. It becomes zero. In addition, in each of the sections T10 to T13 subsequent to the sections T5 to T9 described later, the state is the same as each of the sections T4 to T1 described above.

  Even when the circuit on the second power supply 21 side continues to switch to the power generation power supply side, a current flows through the first to third DC buses 13 to 15 as shown in FIG. 24 according to the switching pattern. In this case, in the sections T5 and T9, the first bus current Ib1 is the current “iu”, and the second bus current Ib2 is “−iu”. In the sections T6 and T8, the first bus current Ib1 is “iu + iv”, and the second bus current Ib2 is “−iu-iv”. In the section T9, the first to third bus currents Ib1 to Ib3 are zero.

  Here, when the final modulation rate commands mu1_cmd to mw1_cmd related to the power generation power source that is the first power supply and the final modulation rate commands mu1_cmd to mw2_cmd related to the second power supply 21 are offset, the sections T1, T4, T7, T10 , T13 is variably set. Thereby, the phases of the first to third bus currents Ib1 to Ib3 can be variably set. FIG. 25 shows the simulation results of the first to third bus currents Ib1 to Ib3. It can be seen that the first to third bus currents Ib1 to Ib4 flow corresponding to the carriers.

  FIG. 26 is a schematic diagram for explaining the synchronization between the second bus current Ib2 and the fourth bus current Ib4. The current of the capacitor 11 corresponds to the difference between the second bus current Ib2 and the fourth bus current Ib4. Therefore, the current flowing through the capacitor 11 can be reduced by synchronizing the timings of the second bus current Ib2 and the fourth bus current Ib4. Therefore, the final modulation rate commands mug_cmd to mwg_cmd related to the control of the inverter 24 are offset in association with the offset value m1_off for the final modulation rate commands mu1_cmd to mw1_cmd related to the control of the power converter 10. Since the second bus current Ib2 and the fourth bus current Ib4 are synchronized in timing, the current flowing into the capacitor 11 is canceled out. Thereby, the heat_generation | fever of the capacitor | condenser 11 is suppressed and the capacitor | condenser 11 can be reduced in size. Therefore, the apparatus size can be reduced.

  Moreover, in this embodiment, the carrier frequency of the power converter 10 which is a series type converter is equal to the carrier frequency of the inverter 24 which is a generated power converter. In this case, the offset values for the final modulation factor commands mu1_cmd to mw1_cmd and mug_cmd to mwg_cmd can be made equal to each other to synchronize the cancellation timing of the pulsed current flowing into the power supply portion. Thereby, the electric current which flows into the capacitor | condenser 11 can be negated.

(Eighth embodiment)
Hereinafter, a control system according to an eighth embodiment of the present invention will be described. The control system according to the eighth embodiment differs from that of the previous seventh embodiment in that the carrier frequency in the control of the power converter 10 which is a series converter and the inverter 24 which is a generated power converter. The carrier frequency in the control is different. In the present embodiment, a case where the carrier frequency of the power converter 10 is smaller than the carrier frequency of the inverter 24 is assumed. Specifically, the carrier frequency of the inverter 24 is twice the carrier frequency of the power converter 10. And In the following, the description common to the seventh embodiment will be omitted, and the description will focus on the differences.

In the present embodiment, the modulation rate command generation unit 56 of the second control unit 50 includes an initial modulation rate command generation unit 56a and an offset unit 56b. The initial modulation rate command generation unit 56a standardizes the three-phase output voltage commands Vu_g *, Vv_g *, and Vw_g * with the voltage Vdc1 of the power generation power source. As a result, initial modulation rate commands mug to mwg for each phase are generated. The offset unit 56b calculates final modulation rate commands mug_cmd to mwg_cmd based on the first and second offset values m1_off and m2_off calculated in the first control unit 40 and the initial modulation rate commands mug to mwg. . Specifically, the offset unit 56b calculates final modulation rate commands mug_cmd to mwg_cmd based on the following equations.

  27 and 28 are explanatory diagrams for explaining the synchronization between the second bus current Ib2 and the fourth bus current Ib4. Here, FIG. 27 shows the case where the final modulation rate commands mug_cmd to mwg_cmd in the control of the inverter 24 are equally offset based on the offset value m1_cmd for the final modulation rate commands mu1_cmd to mw1_cmd related to the generated power source in the control of the power converter 10. It is explanatory drawing of. In this case, since the second bus current Ib2 and the fourth bus current Ib4 are different in timing, current cancellation in the capacitor 11 does not occur.

  Therefore, in the present embodiment, the offset unit 56b offsets the initial modulation rate commands mug to mwg based on a value obtained by multiplying the offset value m1_off by the coefficient 1/2. Accordingly, as shown in FIG. 28, the second bus current Ib2 and the fourth bus current Ib4 can be associated with each other in timing, so that the capacitor current can be canceled.

  An appropriate modulation rate offset value is tabulated through experiments and simulations using the carrier frequency of the power converter 10 and the carrier frequency of the inverter 24 as parameters. Thereby, an offset value for canceling the capacitor current can be set for any combination of carrier frequencies.

(Ninth embodiment)
Hereinafter, a control system according to a ninth embodiment of the present invention will be described. The control system according to the ninth embodiment differs from that of the previous seventh embodiment in that the carrier frequency in the control of the power converter 10 that is a series converter and the inverter 24 that is a generated power converter. The carrier frequency in the control is different. In the present embodiment, a case is assumed in which the carrier frequency of the power converter 10 is larger than the carrier frequency of the inverter 24. Specifically, the carrier frequency of the power converter 10 is twice the carrier frequency of the inverter 24. And In the following, the description common to the seventh embodiment will be omitted, and the description will focus on the differences.

In the present embodiment, the modulation rate command generation unit 56 of the second control unit 50 includes an initial modulation rate command generation unit 56a and an offset unit 56b. The initial modulation rate command generation unit 56a standardizes the three-phase output voltage commands Vu_g *, Vv_g *, and Vw_g * with the voltage Vdc1 of the power generation power source. As a result, initial modulation rate commands mug to mwg for each phase are generated. The offset unit 56b calculates final modulation rate commands mug_cmd to mwg_cmd based on the first and second offset values m1_off and m2_off calculated in the first control unit 40 and the initial modulation rate commands mug to mwg. . Specifically, the offset unit 56b calculates final modulation rate commands mug_cmd to mwg_cmd based on the following equations.

  Next, in the carrier generation unit 48 of the first control unit 40 and the carrier generation unit 58 of the second control unit 50, as shown in FIG. 29, the minimum value of the carrier in the control of the power converter 10, The carrier phase is set so that the minimum value of the carrier in the control of the inverter 24 is synchronized with the timing.

  According to such a configuration, the timing of the second bus current Ib2 and the fourth bus current Ib4 can be synchronized, and the capacitor current can be reduced.

  In addition, as shown in FIG. 30, in the case of so-called two-phase modulation in which the final modulation rate commands mu1_cmd to mw2_cmd of each power source of the power converter 10 are offset until they become equal to the maximum value or the minimum value of the carrier, The capacitor current may be canceled by a technique.

  As mentioned above, although each embodiment concerning the present invention was described, various changes are possible for the present invention within the scope of the present invention. Moreover, although each embodiment was demonstrated independently, it is also possible to implement each embodiment combining each other.

DESCRIPTION OF SYMBOLS 10 ... Power converter 20 ... 1st power supply 21 ... 2nd power supply 30 ... Motor 40 ... Control unit 41 ... Torque control part 42 ... Current control part 43 ... dq / 3 phase conversion part 44 ... Voltage distribution command generation part 45 ... Voltage distribution unit 46 ... Modulation rate command generation unit 46a ... Initial modulation rate command generation unit 46b ... Final modulation rate command generation unit 46c ... Offset unit 46d ... Limiting unit 46e ... Modulation rate amplitude calculation unit 46f ... Offset value generation unit 46g ... Offset processing unit 46h ... priority modulation rate selection unit 46i ... modulation rate limiting unit 47 ... conduction signal generation unit 48 ... carrier wave generation unit 49 ... 3-phase / dq conversion unit

Claims (28)

A power converter for generating a drive voltage of a load by output voltage pulses connected to a plurality of power sources in which each of them is connected in series to each other and connected to the negative electrode of the upper power source and the positive electrode of the lower power source,
Switch means for connecting between the positive electrode of the power supply and the load corresponding to each power supply, and first power conversion means for generating an output voltage pulse from the output voltage of each power supply;
First control means for controlling the respective conduction states of the switch means based on a comparison between the output voltage command value of each power supply and the modulation factor command for each power supply obtained from the voltage of each power supply and the first carrier. And
The first control means controls each switch means in one cycle of the first carrier from the lowest power supply to the highest power supply during the conduction period of the switch means corresponding to the lower power supply. A power conversion device characterized in that the switch means corresponding to the power source of the switch is made conductive. A power converter for generating a drive voltage of a load by output voltage pulses connected to a plurality of power sources in which each of them is connected in series to each other and connected to the negative electrode of the upper power source and the positive electrode of the lower power source,
First power conversion means for generating output voltage pulses from output voltages of individual power supplies;
First control means for controlling the first power conversion means based on a comparison between the output voltage command value of each power supply and the modulation rate command for each power supply obtained from the voltage of each power supply and the first carrier; Have
In the first control means, the output voltage pulse in one cycle of the first carrier is applied to the negative voltage of the lowest power source and the power source lower than itself from the lowest power source to the highest power source. The first power conversion means is controlled so as to be configured with a positive voltage output from each power source during a positive voltage output period. The plurality of power sources are composed of a first power source on the lower side and a second power source on the upper side,
The first control means includes
An initial modulation rate command for a first power source calculated based on a first distributed voltage command value, which is an output voltage command value for the first power source, and the voltage of the first power source, and the second By performing offset processing for offsetting the initial modulation rate command of the second power source calculated based on the second distribution voltage command value that is the output voltage command value relating to the power source and the voltage of the second power source, Final modulation rate command generation means for generating a final modulation rate command for the first power supply and a final modulation rate command for the second power supply;
A conduction control means for controlling each conduction state of the switch means based on a comparison between the final modulation rate command of the first power supply and the final modulation rate command of the second power supply and the first carrier; Have
The final modulation rate command generation means can compare each final modulation rate command of the first power source and the second power source with the first carrier, and the final modulation rate command of the first power source The power conversion apparatus according to claim 1 or 2, wherein the offset processing is performed so that the second modulation rate becomes equal to or greater than a final modulation factor command of the second power source.   4. The final modulation rate command generation means is set with a time for which only the switch means with a large electrical loss is conducted, and performs the offset processing based on the set time. The power converter described in 1.   The final modulation rate command generation means includes a final modulation rate command for the first power supply and a final modulation rate command for the second power supply that are equal to or less than 1/3 of a fundamental wave period for each initial modulation rate command. The power conversion apparatus according to claim 4, wherein the offset processing is performed so as to coincide with each other in time.   The final modulation rate command generation means includes the first initial modulation rate when the first and second power sources are powering or regenerating, respectively, or one of the power sources is stopped and the other power source is powering or regenerating. If the amplitude of the command is smaller than the amplitude of the initial modulation rate command of the second power supply, the upper part of the final modulation rate command of the first power supply is made to coincide with the upper part of the final modulation rate command of the second power supply. The power conversion apparatus according to claim 5, wherein the offset process is performed on the power conversion apparatus.   The final modulation rate command generation means includes the first initial modulation rate when the first and second power sources are powering or regenerating, respectively, or one of the power sources is stopped and the other power source is powering or regenerating. When the amplitude of the command is larger than the amplitude of the initial modulation rate command of the second power supply, the lower part of the final modulation rate command of the first power supply is made to coincide with the lower part of the final modulation rate command of the second power supply. The power conversion apparatus according to claim 5, wherein the offset process is performed on the power conversion apparatus.   In the final modulation rate command generation means, the switch means does not perform a switching operation during a part of the time when the final modulation rate command of the first power supply matches the final modulation rate command of the second power supply. The power converter according to claim 6 or 7, wherein the offset processing is performed as described above.   The final modulation rate command generating means, when one power source is power running and the other power source is regenerative, includes an upper portion of the final modulation rate command of the first power source and a lower portion of the second final modulation rate command. The power conversion apparatus according to claim 4, wherein the offset processing is performed so as to match.   When the voltage of the first power supply is smaller than the voltage of the second power supply, the final modulation rate command generating means is configured such that the switch means corresponding to the second power supply has one cycle or more of the first carrier, and The power converter according to claim 9, wherein the offset processing is performed so as to cut off a time equal to or shorter than 1/3 of a fundamental wave period for each initial modulation rate command.   When the voltage of the first power supply is equal to or higher than the voltage of the second power supply, the final modulation rate command generating means is configured such that the switch means corresponding to the first power supply has a period of 1st carrier or more, and The power converter according to claim 9, wherein the offset processing is performed so as to conduct for a time equal to or shorter than 1/3 of a fundamental wave period related to each initial modulation rate command.   The final modulation rate command generation means sets a time for which only the switch means having a large electrical loss is turned on by detecting the temperature of each switch means according to the detected temperature. The power conversion device described in any one of 4 to 11. The plurality of power sources are composed of a first power source on the lower side and a second power source on the upper side,
The first control means includes
An initial modulation rate command for a first power source calculated based on a first distributed voltage command value, which is an output voltage command value for the first power source, and the voltage of the first power source, and the second Offset means for performing an offset process for offsetting an initial modulation factor command of the second power source calculated based on a second distribution voltage command value that is an output voltage command value relating to the power source and the voltage of the second power source; ,
By performing a restriction process on the modulation rate command of each power source that has been subjected to the offset processing by the offset means, the final modulation rate command of the first power source and the final modulation rate command of the second power source are Final modulation factor command generation means for generating,
A conduction control means for controlling each conduction state of the switch means based on a comparison between the final modulation rate command of the first power supply and the final modulation rate command of the second power supply and the first carrier; Have
The offset means performs the offset process so that the switch means corresponding to the second power supply is conductive during the conduction period of the switch means corresponding to the first power supply;
The restriction means performs the restriction processing so that the conduction time of the switch means corresponding to the first power supply does not reverse the conduction time of the switch means corresponding to the second power supply. The power converter described in 1 or 2.   The limiting means sets the limit values for the initial modulation rate commands of the first power source and the second power source as the limit processing, respectively, and performs the offset processing according to the range of the set limit values. The power conversion device according to claim 13, further comprising a modulation rate limiting unit that limits each modulation rate command for which the operation is performed. The modulation rate limiting means includes
As a limit value related to the modulation factor command of the first power supply after the offset process, the maximum value of the first carrier is set as the upper limit, the minimum value of the first carrier as the lower limit, and the second value after the offset process Set the larger value of the power supply modulation rate command
As a limit value related to the modulation factor command of the second power supply after the offset process, the lower value of the maximum value of the first carrier and the modulation factor command of the first power supply after the offset process is set as an upper limit. The power conversion device according to claim 14, wherein the power conversion device is set and a minimum value of the first carrier is set as a lower limit. The limiting means further includes priority modulation rate selection means for selecting which one of the first power supply and the second power supply has priority for each modulation ratio command subjected to the offset processing. Have
The priority modulation rate selection unit is configured to control a power supply corresponding to a value greater than an output voltage command value generated by the output voltage command generation unit among the first distribution voltage command value and the second distribution voltage command value. The power conversion device according to claim 14, wherein a modulation rate command is selected.   The modulation rate limiting means sets a maximum value of the first carrier as an upper limit and a minimum value of the first carrier as a lower limit as a limit value related to the modulation rate command of the power source selected by the priority modulation rate selection means. The power conversion device according to claim 16, wherein the power conversion device is set.   When the modulation factor command of the first power source is selected by the priority modulation factor selection unit, the modulation factor limiting unit has an upper limit of the first carrier as a limit value related to the modulation factor command of the second power source. The minimum value of the first carrier is set as the lower limit of the limit value by setting the smaller value of the maximum value and the modulation factor command of the first power supply after the offset processing. The power converter described in 16.   When the modulation factor command of the second power source is selected by the priority modulation factor selection unit, the modulation factor limiting unit has an upper limit of the first carrier as a limit value related to the modulation factor command of the first power source. The maximum value is set, and the lower one of the minimum value of the first carrier and the modulation factor command of the second power supply after the offset process is set as the lower limit. Power converter. The first control means includes
Voltage distribution command generating means for generating a voltage distribution command indicating distribution of an output voltage to the first power source and the second power source;
Voltage distribution means for generating the first distribution voltage command value and the second distribution voltage command value based on the output voltage command value for the load and the voltage distribution command;
The voltage distribution command generation means includes
Voltage amplitude calculating means for calculating the amplitude of the output voltage command value;
Based on the amplitude of the output voltage command value and the voltage of each power supply, a distribution range capable of maintaining a relationship in which the first final modulation rate command is greater than or equal to the second final modulation rate command is calculated. A distribution range calculation means;
A voltage distribution command for outputting the voltage distribution command by limiting a target distribution ratio input as an output voltage distribution target value to the first power source and the second power source within the calculated distribution range. The power converter according to claim 3, further comprising a limiting unit.   In the final modulation rate command generation means, each of the switch means corresponding to each power supply performs a switching operation in a time period that is not less than one period of the first carrier and not more than 1/3 of the fundamental wave period for each initial modulation rate command The power conversion device according to claim 3 or 13, wherein the offset processing is performed so as not to occur.   The conduction control means, when conducting the switch means corresponding to the second power supply after conducting the switch means corresponding to the first power supply, during the conduction period of the switch means corresponding to the second power supply. 14. The power conversion device according to claim 3, wherein the switch unit corresponding to the first power supply is cut off on condition that there is a certain condition. One of the first power source and the second power source is composed of a power generation power source,
The generated power source is
AC motor,
Second power conversion means for converting AC power from the AC motor and outputting DC power;
Second control means for controlling the second power conversion means,
The second control means is output from the second power conversion means according to a pulsed current flowing through the other of the first power supply and the second power supply by switching of the first power conversion means. 14. The power conversion device according to claim 3, wherein the pulsed current flowing through the other of the first power supply and the second power supply is canceled by the pulsed current. The second control means includes
A power generation modulation rate generating means for generating an initial modulation rate command for the second power conversion means;
The first control means acquires an offset value for the initial modulation rate command of the power supply corresponding to the power generation power out of the first power supply and the second power supply, and according to the acquired offset value, the Power generation offset means for offsetting the initial modulation rate command generated by the power generation modulation rate generation means;
PWM control means for controlling the conduction state of the switch means included in the second power conversion means based on a comparison between the initial modulation rate command offset by the power generation offset means and the second carrier The power conversion device according to claim 23, wherein:   The power generation offset means, when the frequency of the first carrier and the frequency of the second carrier correspond to each other, sends an initial modulation rate command from the power generation modulation rate generation means to the first carrier 25. The power conversion device according to claim 24, wherein the offset is equal to the offset value acquired from the control means.   The offset unit variably offsets an initial modulation rate command from the power generation modulation rate generation unit when the frequency of the first carrier and the frequency of the second carrier are different. The power conversion device according to claim 24.   When the frequency of the second carrier is twice the frequency of the first carrier, the offset unit sends an initial modulation rate command from the power generation modulation rate generation unit to the first control unit. 27. The power conversion device according to claim 26, wherein the offset is offset by half of the acquired offset value.   When the frequency of the first carrier is twice the frequency of the second carrier, the offset means sets the offset for the initial modulation rate command from the power generation modulation rate generation means to zero, and 27. The power converter according to claim 26, wherein a minimum value of a first carrier and a minimum value of the second carrier are synchronized.

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