JP2010197202A - Semiconductor-testing device and method of diagnosing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor-testing device for easily diagnosing variations in the semiconductor-testing device without forcing troublesome work to a user, and to provide a method of diagnosing the semiconductor-testing device. <P>SOLUTION: The semiconductor-testing device 1 achieves a plurality of device embodiments (variations) where at least one of a scale and a function differs by an increase/decrease of card C1-Cn mounted on a test head 10. The semiconductor-testing device includes: a memory 22 for storing information indicating a card type in a block including slots for mounting different cards for each variation from among slots 11a-11n where cards are mounted; a flag setting section 21a for acquiring information indicating a card type mounted to a slot included in the block for storing as a slot block table TB in the memory 22; and a variation determination section 21b for determining an actual variation, based on the slot block table TB stored in the memory 22. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor test apparatus for testing a semiconductor device and a diagnostic method therefor.

  2. Description of the Related Art Generally, a semiconductor test apparatus for testing a semiconductor device (hereinafter referred to as DUT (Device Under Test)) is a control apparatus (tester) that controls the operation of a test head on which a DUT is mounted and the semiconductor test apparatus in an integrated manner. Controller) and the like. In recent years, various functions tend to be concentrated in a test head as the semiconductor test apparatus increases in speed and functionality, and many types of substrates (cards) are mounted in the test head.

  Examples of cards provided in the test head include a power card, a driver / pin electronics card (hereinafter referred to as a driver PE card), a level / pin electronics card (hereinafter referred to as a level PE card), a pin selector card, and a communication card. Can be mentioned. The power supply card is a card that generates power to be supplied to the DUT. The driver PE card is a card that generates a test signal to be applied to the DUT, and the level PE card is a card that has a higher degree of freedom in setting the level of the test signal than the driver PE card. The pin selector card is a card for selecting a pin (tester pin) used for the DUT test, and the communication card is a card for realizing communication with the test apparatus main body.

  Here, the configuration of the semiconductor test apparatus is not necessarily the same as long as it is the same model, but the scale and function can be increased or decreased according to the type of DUT and the same number of measurements (the number of DUTs that can be tested simultaneously). Designed to. That is, by adding, reducing, or replacing a card mounted on the test head, it is possible to realize an apparatus mode (hereinafter referred to as a variation) having a different scale and function even with the same model.

  FIG. 7 is a configuration definition table showing an example of a variation of a conventional semiconductor test apparatus. This configuration definition table shows, for each variation, card information indicating the type of card to be mounted (installed) for each slot of the test head. In the example shown in FIG. 7, five types of “full”, “type A”, “type B”, “type C”, and “half” are listed as variations of the semiconductor test apparatus.

  Referring to FIG. 7, “half” is specified by the power supply card installed in the slot specified by slot numbers “03” and “04” and slot numbers “13” to “18” compared to “full”. It can be seen that the driver PE card mounted in the slot is omitted, and the scale is literally about half of “full”. In “Type C”, it can be seen that the power supply card is mounted in the slot specified by the slot numbers “16” to “18”, and more power supply cards are mounted than “full”.

  As described above, since there are variations in the semiconductor test apparatus, the semiconductor test apparatus diagnoses the actual card mounting state according to a user instruction. Specifically, first, variation information (information specifying a variation) designated in advance by the user is read. Next, card information about the variation specified by the variation information is read from a configuration definition table stored in advance.

  Then, access to each slot is sequentially performed to determine whether or not the card indicated by the read card information is actually mounted in each slot, and a card different from the card indicated by the card information is mounted. If so, the card information is updated. Here, when a certain number or more of cards different from the card indicated by the read card information are mounted, an error occurs after the card information is updated. For details of the diagnosis performed by the conventional semiconductor test apparatus, see, for example, Patent Document 1 below.

JP 2004-163194 A

  By the way, the above-described diagnosis of the semiconductor test apparatus is not only executed after being shipped as a product, but also a stage of developing a test program used in the semiconductor test apparatus, a stage of assembling the semiconductor test apparatus and verifying its operation, It is also performed at the stage of investigating the cause of failure of the semiconductor test equipment. For this reason, the above diagnosis is not only performed as a product under a complete configuration, but also under an incomplete configuration.

  As described above, the conventional semiconductor test apparatus performs diagnosis based on variation information designated in advance by the user. For this reason, if there is a large discrepancy between the card to be mounted indicated by the card information for the variation specified by the variation information specified by the user and the actual mounting status of the test head, an error will occur and the variation information will be displayed. It is necessary to change the diagnosis again, and it is not always convenient.

  Here, the above-described configuration definition table is basically created assuming a complete configuration shipped as a product. For this reason, when a user performs diagnosis under an incomplete configuration, it is difficult to specify appropriate variation information to be specified, and the diagnosis can be extended by repeating the diagnosis while changing the specified variation information. There is a problem that it takes time, or a card for which diagnosis is to be executed may be excluded from the diagnosis target and the diagnosis may not be executed.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor test apparatus capable of easily diagnosing variations of a semiconductor test apparatus without forcing a user to perform complicated operations and a diagnosis method thereof. To do.

In order to solve the above-described problems, the semiconductor test apparatus of the present invention realizes a plurality of apparatus modes that differ in at least one of scale and function by increasing or decreasing the number of substrates (C1 to Cn) mounted on the test head (10). In a possible semiconductor test apparatus (1), among the mounting positions (11a to 11n) where the board is mounted, the type of the board at a characteristic position (B1 to B3) where a different board is mounted for each apparatus mode is shown. A storage unit (22) for storing information, an acquisition unit (21a) for acquiring board information indicating the type of board mounted at the characteristic position and storing the board information in the storage unit, and stored in the storage unit And a determination unit (21b) that determines an actual apparatus mode based on the substrate information.
According to the present invention, board information indicating the type of board mounted at a characteristic position where a board different for each device mode is mounted among the mounting positions where the board is mounted is acquired by the acquisition unit and stored in the storage unit. Then, the actual device mode is determined by the determination unit based on the substrate information stored in the storage unit.
The semiconductor test apparatus of the present invention stores, for each feature position, a table (TB) in which a flag for each type of the substrate indicating whether the storage unit is mounted at the feature position is set. The acquisition unit stores the substrate information in the storage unit by setting a flag of the table stored for each feature position based on the substrate information acquired for each feature position. It is said.
The semiconductor test apparatus according to the present invention is characterized in that the determination unit determines an actual apparatus mode based on whether or not a flag of the table stored for each feature position is set.
Further, in the semiconductor test apparatus of the present invention, the determining unit determines an actual apparatus mode with a preset priority by referring to the table stored for each feature position in a preset order. It is characterized by doing.
The method for diagnosing a semiconductor test apparatus according to the present invention is a semiconductor test apparatus capable of realizing a plurality of apparatus modes that differ in at least one of scale and function by increasing or decreasing the number of substrates (C1 to Cn) mounted on the test head (10). (1) A diagnostic method for a semiconductor test apparatus for diagnosing a device mode, wherein among the mounting positions (11a to 11n) where the substrate is mounted, a characteristic position (B1) where a different substrate is mounted for each device mode To B3) a first step (S12 to S22) for acquiring and storing board information indicating the type of board mounted, and an actual apparatus mode based on the board information stored in the first step. And a second step of determining (S25, S31 to S39).
In the semiconductor test apparatus diagnostic method of the present invention, the second step refers to the substrate method for each feature position stored in the first step in a preset order. It is a step of determining an actual device mode with the set priority.

  According to the present invention, among the mounting positions where the board is mounted, the board information indicating the type of board mounted at the characteristic position where a different board is mounted for each device mode is acquired by the acquisition unit and stored in the storage unit. Since the actual device mode is determined by the determination unit based on the substrate information stored and stored in the storage unit, variations in the semiconductor test apparatus can be easily diagnosed without forcing the user to perform complicated operations. There is an effect.

It is a block diagram which shows the principal part structure of the semiconductor test apparatus by one Embodiment of this invention. It is a structure definition table which shows an example of the variation of the semiconductor test apparatus by one Embodiment of this invention. It is a figure which shows the kind and number of cards which are mounted in blocks B1 to B3 shown in FIG. 2 for each variation. 4 is a diagram illustrating an example of a slot block table TB stored in a memory 22. FIG. It is a flowchart which shows the operation | movement at the time of the diagnosis of the semiconductor test apparatus by one Embodiment of this invention. It is a flowchart which shows the operation | movement at the time of the diagnosis of the semiconductor test apparatus by one Embodiment of this invention. It is a structure definition table which shows an example of the variation of the conventional semiconductor test apparatus.

  Hereinafter, a semiconductor test apparatus and a diagnostic method thereof according to an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a main configuration of a semiconductor test apparatus according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor test apparatus 1 of the present embodiment includes a test head 10 and a test apparatus body 20 that are connected to each other via a bus B, and under the control of the test apparatus body 20, A device aspect (variation) of the semiconductor test apparatus 1 is diagnosed, and a DUT (not shown) placed on the test head 10 is tested.

  The test head 10 includes a plurality of slots 11a to 11n (mounting positions) on which cards C1 to Cn (boards) are mounted (mounted), and are mounted in the slots 11a to 11n under the control of the test apparatus main body 20. Information indicating the type of the cards C1 to Cn being obtained is obtained. The semiconductor test apparatus 1 can realize a variation in which at least one of the scale and the function is different even in the same model by increasing / decreasing the cards C1 to Cn mounted on the test head 10.

  The test head 10 is electrically connected through various jigs (performance board, contact ring, probe card, etc.) placed on the test head 10 under the control of the test apparatus body 20. Conduct DUT testing. Specifically, various patterns (test pattern and expected value pattern) used for testing the DUT based on the test signal output from the test apparatus body 20 should be generated and applied to the DUT using the test pattern. A test signal is generated, and a pass / fail is determined by comparing the signal output from the DUT with the test signal and the expected value generated using the expected value pattern. The determination result is output to the test apparatus body 20 via the bus B.

  Here, variations that can be realized by the semiconductor test apparatus 1 will be described. FIG. 2 is a configuration definition table showing an example of variations of the semiconductor test apparatus according to the embodiment of the present invention. This configuration definition table shows, for each variation, card information indicating the types of cards C1 to Cn to be mounted in the slots 11a to 11n of the test head 10. In the example shown in FIG. 2, five types of “full”, “type A”, “type B”, “type C”, and “half” are listed as variations of the semiconductor test apparatus 1.

  Referring to FIG. 2, for slots specified by slot numbers “01”, “02”, “06” to “12”, “19”, “20”, “full”, “type A”, “type” It can be seen that the same type of card is mounted in all of the five types of variations “B”, “Type C”, and “Half”. It can also be seen that different types of cards are mounted for each variation in the slots specified by the slot numbers “03” to “05” and “13” to “18”.

  Note that “power supply” in FIG. 2 means a power supply card that generates power to be supplied to the DUT. “Driver PE” means a driver pin electronics card (driver PE card) that generates a test signal to be applied to the DUT. “Level PE” has a higher degree of freedom in setting the level of the test signal than the driver PE card. It means level pin electronics card (level PE card). Further, “pin selector” means a pin selector card for selecting a pin (tester pin) used for the DUT test, and “communication” means a communication card for realizing communication with the test apparatus main body 20.

  In the present embodiment, among slots in which different types of cards are mounted for each variation shown in FIG. 2, slots in which characteristic cards are mounted for each variation are blocked and included in each block (characteristic position). Variations are diagnosed based on the type of card installed in the slot. In the example shown in FIG. 2, the slot specified by the slot number “04” is in the block B1, the slots specified by the slot numbers “13” to “15” are in the block B2, and the slot numbers “16” to “18”. The slots specified in (1) are each divided into blocks B3.

  FIG. 3 is a diagram illustrating, for each variation, the types and number of cards mounted in the blocks B1 to B3 illustrated in FIG. Referring to FIG. 3, it can be seen that one or more level PE cards are mounted in block B1 when the variation is “type B”, and no card is mounted when the variation is “type A”. In block B2, one or more driver PE cards are mounted when the variation is “type A”, “type B”, or “type C”, and when the variation is “half”. It can be seen that is not implemented.

  In block B3, when the variation is “full”, one or more driver PE cards are mounted, and the variation is “type A”, “type B”, “type C”, or “half”. It can be seen that the card is not mounted in some cases. In addition, it can be seen that one or more power supply cards are mounted in the block B3 when the variation is “type C”, and no card is mounted when the variation is “type A”. The tester controller 21 provided in the test apparatus body 20 diagnoses variations based on the types of cards mounted in the slots included in the blocks B1 to B3. Details of the diagnosis performed by the tester controller 21 will be described later.

  The test apparatus body 20 includes a tester controller 21, a memory 22 (storage unit), and a hard disk 23, and controls the test head 10 to perform a diagnosis of variations of the semiconductor test apparatus 1 and a DUT test. The tester controller 21 controls the overall operation of the semiconductor test apparatus 1. Specifically, information indicating the type of card mounted on the test head 10 is acquired via the bus B, and the variation is determined. Also, various control signals such as control signals for generating various patterns (test patterns and expected value patterns) used for testing the DUT are output to the test head 10 via the bus B to execute the DUT test. .

  The tester controller 21 includes a flag setting unit 21a (acquisition unit) and a variation determination unit 21b (determination unit), which diagnoses variations of the semiconductor test apparatus 1. The flag setting unit 21a and the variation determination unit 21b are realized in software by the tester controller 21 loading and executing the diagnostic program DP stored in the hard disk 23.

  The flag setting unit 21a is mounted in a slot (for example, a slot included in the blocks B1 to B3 illustrated in FIG. 2) in which different cards are mounted among the plurality of slots 11a to 11n provided in the test head 10. Information (substrate information) indicating the type of the card that has been read is acquired and stored in the memory 22 as a slot block table TB. Here, the slot block table TB stored in the memory 22 will be described.

  FIG. 4 is a diagram illustrating an example of the slot block table TB stored in the memory 22. As shown in FIG. 4, the slot block table TB includes a field F1 in which a flag indicating the presence / absence of a driver PE card is stored, a field F2 in which a flag indicating the presence / absence of a level PE card is stored, and a flag indicating the presence / absence of a power supply card. Is a table in which a field F3 is stored for each of the blocks B1 to B3. The fields F1 to F3 provided corresponding to the block B1 are provided corresponding to the address A0 of the memory 22, and the fields F1 to F3 provided corresponding to the block B2 are provided corresponding to the address A1 of the memory 22 and corresponding to the block B3. It is assumed that the fields F1 to F3 are stored in the address A2 of the memory 22, respectively.

  For example, when the flag setting unit 21a acquires information indicating that the card mounted in the slot (slot specified by the slot number “4”) included in the block B1 illustrated in FIG. 2 is a level PE card. Sets a flag in the field F2 stored in the address A0 of the memory 22. Similarly, when information indicating that the card mounted in the slot (slot specified by slot numbers “13” to “15”) included in the block B2 shown in FIG. 2 is a driver PE card is acquired. Sets a flag in the field F1 stored in the address A1 of the memory 22. In this way, the flag setting unit 21a acquires the flag by setting the flag in the slot block table TB based on the information acquired via the bus B (information indicating the type of card installed in the slot). Information is stored in the memory 22 as a slot block table TB.

  The variation determination unit 21 b determines an actual variation of the semiconductor test apparatus 1 based on the presence / absence of a flag set in the slot block table TB stored in the memory 22. Depending on the contents of the flag set in the slot block table TB, a plurality of variation candidates to be determined may appear. For this reason, the variation determination unit 21b refers to the slot block table TB stored in the memory 22 in a preset order, thereby determining an actual variation with a preset priority. Details of the processing performed by the variation determination unit 21b will be described later.

  The memory 22 is realized by, for example, a volatile memory such as a DRAM (Dynamic Random Access Memory), and stores the slot block table TB shown in FIG. 4 and variation information V1 for specifying variations of the semiconductor test apparatus 1 and the like. The hard disk 23 stores a diagnostic program DP that implements the flag setting unit 21a and the variation determination unit 21b described above. Although not shown in FIG. 1, a test program created by the user and used for testing the DUT is also stored in the hard disk 23. Here, although not shown in FIG. 1, the test apparatus main body 20 includes an input device for inputting a user instruction, and various processing results and DUT test results performed based on the user instruction. A display device for displaying is also provided.

  Next, the operation of the semiconductor test apparatus 1 having the above configuration will be described. 5 and 6 are flowcharts showing the operation at the time of diagnosis of the semiconductor test apparatus according to the embodiment of the present invention. The process shown in the flowchart shown in FIG. 5 is started when a user operates an input device (not shown) and issues a diagnosis start instruction to the tester controller 21 provided in the test apparatus body 20.

  When the diagnosis is started, the flag setting unit 21a performs a process of initializing a slot number (hereinafter referred to as an access number) for specifying a slot to be accessed among the plurality of slots 11a to 11n provided in the test head 10. Performed (step S11). For example, in order to identify the slot 11a shown in FIG. 1, processing for setting the access number to “01” is performed.

  Next, the flag setting unit 21a performs processing for obtaining information indicating the type of card installed in the slot specified by the access number initialized in step S11 (step S12). Specifically, a control signal for requesting information indicating the type is output from the tester controller 21 to the card C1 mounted in the slot 11a of the test head 10 via the bus B. As a response to this control signal, information indicating the type of the card C1 is output from the card C1 to the tester controller 21 via the bus B.

  Next, the flag setting unit 21a determines whether or not the access number is included in any of the blocks B1 to B3 shown in FIG. 2 (step S13). That is, it is determined whether or not the access number corresponds to one of the slot numbers “04”, “13” to “15”, and “16” to “18”. If the access number corresponds to the slot number “04”, the flag setting unit 21a performs processing for setting the address pointer for writing to the slot block table TB stored in the memory 22 to “A0” ( Step S14).

  If the access number corresponds to the slot numbers “13” to “15”, the flag setting unit 21a performs processing for setting the address pointer to “A1” (step S15), and the access number is “16”. If it corresponds to “18” to “18”, the process of setting the address pointer to “A2” is performed by the flag setting unit 21a (step S16). If the access does not correspond to any of the slot numbers “04”, “13” to “15”, and “16” to “18”, the process proceeds to step S23.

  Here, since the access number is set to the slot number “01” in step S11, the process proceeds from step S13 to step S23, and the flag setting unit 21a determines whether there is a remaining slot to be accessed. Here, since there are remaining slots to be accessed, the determination result in step S23 is “YES”. Then, the access number is incremented by the flag setting unit 21a, and the flag setting unit 21a performs processing for obtaining information indicating the type of card installed in the slot specified by the newly set access number (step S21). S12). As described above, when the access number does not correspond to any of the slot numbers “04”, “13” to “15”, and “16” to “18”, the processes of steps S13, S23, S24, and S12 are repeated. It is.

  On the other hand, when the access number corresponds to one of the slot numbers “04”, “13” to “15”, and “16” to “18”, the type of card indicated by the information acquired in step S12. The flag setting unit 21a sequentially determines whether or not the driver PE card is a driver PE card (step S17), is a level PE card (step S18), and is a power supply card (step S19). If it is a driver PE card (if the determination result in step S17 is “YES”), the flag setting unit 21a sets the field F1 specified by the address pointer set in any one of steps S14 to S16. A flag is set (step S20).

  If the card is a level PE card (if the determination result in step S18 is “YES”), the field specified by the address pointer set in any one of steps S14 to S16 by the flag setting unit 21a. A flag is set in F2 (step S21). If the card is a power supply card (if the determination result in step S19 is “YES”), the flag setting unit 21a specifies the field F3 specified by the address pointer set in any one of steps S14 to S16. Is set to a flag (step S22).

  If the flag is set in any of the above steps S20 to S22, or if all the determination results in steps S17 to S19 are “NO”, the flag setting unit 21a determines whether there is a remaining slot to be accessed. Is determined (step S23). When it is determined that there is a slot to be accessed (when the determination result of step S23 is “YES”), the access number is incremented by the flag setting unit 21a (step S24), and the process of step S12 is performed again. On the other hand, when it is determined that there is no slot to be accessed (when the determination result of step S23 is “NO”), the variation determination unit 21b performs a process of determining a variation of the semiconductor test apparatus 1 ( Step S25).

  In the process of determining the variation of the semiconductor test apparatus 1, the slot block table TB stored in the memory 22 by the variation determining unit 21b is referred to in a preset order by the variation determining unit 21b. Specifically, reference is made in the order of field F1 of address A2, field F1 of address A1, field F2 of address A0, and field F3 of address A2 shown in FIG.

  When the field F1 of the address A2 shown in FIG. 4 is referred to, as shown in FIG. 6, the variation determining unit 21b determines whether or not the driver PE card is mounted in the block B3 (step S31). When the determination result is “YES”, the variation of the semiconductor test apparatus 1 is determined to be “full” by the variation determining unit 21b, and information indicating “full” is stored in the memory 22 as variation information V1 (step S1). S32).

  On the other hand, when the determination result of step S31 is “NO”, the field F1 of the address A1 shown in FIG. 4 is referred to by the variation determination unit 21b. Then, as shown in FIG. 6, it is judged by the variation determination part 21b whether the driver PE card is mounted in the block B2 (step S33). When the determination result is “NO”, the variation of the semiconductor test apparatus 1 is determined as “half” by the variation determining unit 21b, and information indicating “half” is stored in the memory 22 as variation information V1 (step S1). S34).

  On the other hand, if the determination result in step S33 is “YES”, the field F2 of the address A0 shown in FIG. 4 is referred to by the variation determination unit 21b. Then, it is judged by the variation determination part 21b whether the level PE card is mounted in the block B1 (step S35). When the determination result is “NO”, the variation of the semiconductor test apparatus 1 is determined as “type B” by the variation determination unit 21b, and information indicating “type B” is stored in the memory 22 as variation information V1. (Step S36).

  On the other hand, when the determination result in step S35 is “YES”, the field F3 of the address A2 shown in FIG. 4 is referred to by the variation determination unit 21b. Then, it is judged by the variation determination part 21b whether the power supply card is mounted in the block B1 (step S37). When the determination result is “NO”, the variation of the semiconductor test apparatus 1 is determined as “type C” by the variation determination unit 21b, and information indicating “type C” is stored in the memory 22 as variation information V1. (Step S36). On the other hand, if the determination result in step S37 is “YES”, the variation of the semiconductor test apparatus 1 is determined as “type A” by the variation determination unit 21b, and information indicating “type A” is stored in the memory 22 as variation information V1. (Step S39).

  Through the processing described above, the variation of the semiconductor test apparatus 1 is automatically determined by merely issuing a diagnosis instruction, even if the user does not instruct variation information. The card to be mounted indicated by the card information about the variation specified by the variation information V1 stored in the memory 22 may be slightly different from the card actually mounted on the test head 10. In this case, since the information indicating the types of the cards C1 to Cn mounted in the slots 11a to 11n is acquired in the process shown in FIG. 5, the card information is updated using this information. It is desirable to perform processing.

  As described above, in the present embodiment, among the slots 11a to 11n of the test head 10 in which the cards C1 to Cn are mounted, the slots in which characteristic cards are mounted for each variation are blocked and included in each block. Variations are determined based on the type of card installed in the slot. For this reason, the variation of the semiconductor test apparatus 1 can be easily diagnosed without performing a complicated operation of the user inputting variation information.

  The semiconductor test apparatus and the diagnostic method thereof according to the embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and can be freely changed within the scope of the present invention. For example, in the above embodiment, as illustrated in FIG. 5, the example in which all of the slots provided in the test head 10 are accessed has been described. However, only the slots included in any of the blocks B1 to B3 are accessed, and variations are made. You may decide. Thereby, the time required for diagnosis can be significantly shortened.

DESCRIPTION OF SYMBOLS 1 Semiconductor test apparatus 10 Test head 11a-11n Slot 21a Flag setting part 21b Variation determination part 22 Memory B1-B3 block C1-Cn card TB Slot block table

Claims (6)

In a semiconductor test apparatus capable of realizing a plurality of apparatus modes having different scales and functions by increasing or decreasing the number of substrates mounted on the test head,
A storage unit that stores information indicating a type of a substrate at a characteristic position where a different substrate is mounted for each device mode among mounting positions where the substrate is mounted;
An acquisition unit that acquires board information indicating the type of board mounted at the feature position and stores the board information in the storage unit;
And a determination unit that determines an actual apparatus mode based on the substrate information stored in the storage unit. The storage unit stores, for each feature position, a table in which a flag for each type of substrate indicating whether or not the feature position is mounted is set.
The acquisition unit stores the substrate information in the storage unit by setting a flag of the table stored for each feature position based on the substrate information acquired for each feature position. The semiconductor test apparatus according to claim 1.   The semiconductor test apparatus according to claim 2, wherein the determining unit determines an actual apparatus mode based on whether or not a flag of the table stored for each feature position is set.   The said determination part determines an actual apparatus aspect with the preset priority by referring the said table memorize | stored for every said feature position in the preset order. Semiconductor test equipment. A semiconductor test apparatus diagnosis method for diagnosing a device aspect of a semiconductor test apparatus capable of realizing a plurality of device aspects having different scales and functions by increasing or decreasing the number of substrates mounted on a test head,
A first step of acquiring and storing board information indicating a type of board mounted at a characteristic position at which a different board is mounted for each of the device modes among mounting positions at which the board is mounted;
A second step of determining an actual device mode based on the substrate information stored in the first step.   In the second step, an actual apparatus mode is determined with a preset priority by referring to the substrate method for each feature position stored in the first step in a preset order. 6. The semiconductor test apparatus diagnosis method according to claim 5, wherein the method is a step.

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