JP2010187251A - Serial communication device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that, when noise is superposed on output signals of transmitting parts which do not perform transmission, the noise is superposed on transmission signals to receive incorrect data in the case of a serial communication device configured so that a plurality of transmitting parts are operated by time division and transmission signals to be output by the plurality of transmitting parts are transmitted by one communication path. <P>SOLUTION: The serial communication device is provided with a start bit detection part which corresponds one-to-one to the transmitting parts, and in which the transmission signals of the corresponding transmitting parts are input, and when the start bit detection part detects a start bit, the output signals of the transmitting parts which do not perform transmission for a fixed period are masked. Even when the noise is superposed on output of the transmitting parts which do not perform transmission, since the noise is masked, correct signals without being affected by the noise are transmitted. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a serial communication apparatus that performs time division multiplexing transmission of a transmission signal having a start bit.

  FIG. 4 shows the configuration of a serial communication apparatus that performs time division multiplex transmission of digital data in an asynchronous manner. In FIG. 4, reference numerals 10 and 11 denote transmission units that transmit digital data in an asynchronous manner. The transmission units 10 and 11 transmit transmission data serially so that communication times do not overlap each other.

  A negative logic OR gate 12 operates as a coupler. A transmission signal output from the transmission units 10 and 11 is input to the OR gate 12. The OR gate 12 calculates the logical sum of the input transmission signals and outputs it to the communication path 13.

  A receiver 14 is connected to the communication path 13. The receiving unit 14 analyzes the transmission signal output from the OR gate 12 and converts it into digital data. By doing so, it is possible to transmit transmission signals from the two transmission units through one communication path 13.

  FIG. 5 shows a format of a transmission signal by the asynchronous method. The transmission signal is composed of four parts: a start bit Sta, transmission data D, a parity bit P, and a stop bit Sto.

  When not transmitting, the output signals of the transmitters 10 and 11 are maintained at a high level. At the start of transmission, the transmission signal is set to a low level for one clock. This is called a start bit. After the start bit, transmission data D of 7 to 8 bits is transmitted.

  When the transmission data D ends, the parity bit P is transmitted. The parity bit P is a bit for checking whether the transmitted data is correctly received. When the parity bit P ends, 1 to 2 stop bits Sto (high level) are transmitted, and transmission ends.

  FIG. 6 shows an example of a transmission signal. 6A and 6B are waveform diagrams of transmission signals output from the transmission units 10 and 11, respectively, and FIG. 6C is a waveform diagram of reception signals received by the reception unit 14. T1 and T2 represent transmission periods of the transmission units 10 and 11, respectively, and R1 and R2 represent reception periods of the reception unit 14.

Since the outputs of the transmitters 10 and 11 when not transmitting are both high, the output of the OR gate 12 is also high. When one of the transmission units 10 and 11 starts transmission and its output becomes low level, the output of the OR gate 12 also becomes low level. As described above, since the transmission units 10 and 11 transmit in time division, the reception unit 14 can receive correct data.
Japanese Patent Laid-Open No. 11-088442

  However, such a serial communication device has the following problems. Since the OR gate 12 only outputs the logical sum of the output signals of the transmission units 10 and 11, as shown at 20, when the output signal of the transmission unit on the non-transmission side becomes low level due to noise or the like, the OR gate 12 The output of is changed to a low level even if the output of the transmitting unit on the transmitting side is at a high level. Therefore, as shown in 21, there is a problem that the receiving unit 14 receives an incorrect signal and garbled characters cannot be reproduced to reproduce accurate digital data.

  Accordingly, an object of the present invention is to provide a serial communication device capable of transmitting and receiving accurate digital data by masking the output signal of the transmitting unit on the side not transmitting data.

In order to solve such a problem, the invention according to claim 1 of the present invention,
At least two transmitters for transmitting in a time division manner a transmission signal having a start bit indicating the start of transmission;
A transmission signal output by the transmission unit is input, and a start bit detection unit that activates the output signal for a predetermined period after detecting the start bit;
A transmission signal output from the transmission unit, and an output signal of the start bit detection unit, and a signal mask unit that masks an output signal of the transmission unit that is not transmitting based on the output signal of the start bit detection unit; ,
Is provided. Even if noise is superimposed on the output signal of the transmitter that is not transmitting, correct data can be received.

The invention according to claim 2 is the invention according to claim 1,
The period during which the start bit detection unit activates the output signal is the period during which the corresponding transmission unit transmits the transmission signal. Transmission efficiency can be increased.

The invention according to claim 3 is the invention according to claim 1 or claim 2,
The transmission unit transmits data in an asynchronous manner. It can cope with communication methods often used.

The invention according to claim 4 is the invention according to any one of claims 1 to 3,
The signal mask portion;
The transmission signal transmitted by the transmission unit and the output signal of the start bit detection unit to which the output signal of the transmission unit other than the transmission unit is input are input, and the input signal is input when the output signal of the start bit detection unit is active A first gate for masking the transmitted signal,
A second gate that receives an output signal of the first gate and outputs a logical sum of the input signals;
It is composed of The configuration of the signal mask portion can be simplified.

The invention according to claim 5 is the invention according to any one of claims 1 to 4,
The number of transmission units is two. It can be applied to a frequently used configuration.

As is apparent from the above description, the present invention has the following effects.
According to the first, second, third, fourth, and fifth aspects of the present invention, there is provided a serial communication device that transmits digital data from a plurality of transmission units in a time-sharing manner. When a start bit of a transmission signal output from the transmission unit is detected, a start bit detection unit that activates the output for a predetermined period of time, and outputs of the start bit detection unit and the transmission unit are input, and one of the start bit detection units A signal masking unit for masking the output signal of the transmitting unit that is not transmitting the transmission signal while the output is active is provided.

  Even if noise is superimposed on the output signal of the transmission unit that is not transmitting the transmission signal, the noise is masked by the signal masking unit, so that the reception unit can receive an accurate signal.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing Embodiment 1 of a serial communication apparatus according to the present invention. The same elements as those in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted.

  In FIG. 1, reference numerals 30 and 31 denote start bit detection units, which receive transmission signals output from the transmission units 10 and 11, respectively. When the start bit detectors 30 and 31 detect the start bit, they activate their outputs for a certain period. That is, the transmission unit and the start bit detection unit have a one-to-one correspondence. When the start bit detection unit detects the start bit of the transmission signal output by the corresponding transmission unit, the output is activated for a certain period.

  Reference numeral 32 denotes a signal mask unit, which includes negative logic AND gates 33 and 34 and a negative logic OR gate 35. The AND gates 33 and 34 correspond to the first gate, and the OR gate 35 corresponds to the second gate.

  A transmission signal output from the transmission unit 10 and an output signal from the start bit detection unit 31 are input to the AND gate 33, and a transmission signal output from the transmission unit 11 and an output signal from the start bit detection unit 30 are input to the AND gate 34. Is done. Further, the outputs of the AND gates 33 and 34 are input to the OR gate 35. The output of the OR gate 35 is input to the receiving unit 14 via the communication path 13.

  Although FIG. 1 shows an example in which the start bit detection units 30 and 31 and the signal mask unit 32 are on the transmission units 10 and 11 side, the present invention is not limited to this configuration, and the start bit detection units 30 and 31 are not limited to this configuration. All or part of the signal mask unit 32 may be on the receiving unit side.

  Next, the operation of the first embodiment will be described with reference to FIG. 2A to 2E respectively show a transmission signal output from the transmission unit 10, an output signal from the start bit detection unit 30, a transmission signal output from the transmission unit 11, an output signal from the start bit detection unit 31, and a reception unit 14. Is a received signal. It is assumed that the output signals of the start bit detection units 30 and 31 are active at a high level.

  As described with reference to FIG. 5, the transmission signals output from the transmission units 10 and 11 are at a high level when not being transmitted. Further, a start bit is transmitted at the start of transmission, and the transmission signal is at a low level for one clock. Therefore, the start bit can be detected by detecting the falling edge of the transmission signal. As the start bit detector, for example, a one-shot multivibrator can be used.

  When the transmission signal of the transmission unit 10 falls, the start bit detection unit 30 makes its output high for a certain period. In FIG. 2, since the transmission signal of the transmission unit 10 falls at time t1, the output signal of the start bit detection unit 30 in (B) becomes a high level from t1 to t3.

  Since the transmission signals of the start bit detection unit 30 and the transmission unit 11 are input to the AND gate 34, the output signal of the AND gate 34 is high regardless of the level of the output signal of the transmission unit 11 from time t1 to time t3. Become a level.

  As shown in (D), when the output signal of the transmission unit 11 falls at time t4, the start bit detection unit 31 sets its output to high level from time t4 to time t5. Since the output signals of the start bit detection unit 31 and the transmission unit 10 are input to the AND gate 33, the output of the AND gate 33 is high between time t4 and t5 regardless of the level of the output signal of the transmission unit 10. Become a level.

  As shown in (C), it is assumed that the output signal of the transmission unit 11 becomes low level due to the influence of noise at time t2. At this time, since the output of the start bit detector 30 is at a high level, this low level signal is blocked by the AND gate 34 and is not transmitted to the receiver 14. Therefore, the receiving unit 14 can receive a correct signal.

  As described above, when the start bit detection units 30 and 31 detect the start bit, the output is activated for a certain period, and the signal mask unit 32 masks the output of the transmission unit on the side not transmitting by the output of the start bit detection unit. I tried to do it. For this reason, even if noise is superimposed on the output signal of the transmission unit on the non-transmitting side, this noise is blocked by the signal mask unit 32, so that a correct signal can be transmitted to the reception unit 14.

  The period during which the start bit detection units 30 and 31 activate the output signal is a period during which the corresponding transmission unit transmits a signal, that is, a period from the start bit Sta to the stop bit Sto. As described with reference to FIG. 5, in the asynchronous method, the transmission signal is composed of the start bit Sta, the transmission data D, the parity bit P, and the stop bit Sto, and the number of bits is fixed, so that the transmission period is constant. Value. Therefore, the period during which the start bit detectors 30 and 31 activate their outputs is also a constant value.

  FIG. 3 shows the configuration of the second embodiment of the present invention. The second embodiment uses three or more transmission units. With this configuration, the communication path 13 can be used more efficiently. In addition, the same code | symbol is attached | subjected to the same element as FIG. 1, and description is abbreviate | omitted.

  In FIG. 3, reference numerals 40a, 40b to 40n denote N transmission units, which transmit transmission data in an asynchronous manner. The transmission units 40a and 40b to 40n transmit transmission signals in a time division manner so as not to overlap each other.

  Reference numerals 41a and 41b to 41n denote start bit detection units, to which transmission signals output from the transmission units 40a and 40b to 40n are input, respectively. That is, the transmission units 40a and 40b to 40n and the start bit detection units 41a and 41b to 41n have a one-to-one correspondence. When the start bit detectors 41a and 41b to 41n detect the start bit of the input transmission signal, they set the output signal to a high level (active) for a certain period.

  Reference numeral 42 denotes a signal mask unit which includes negative logic N-input AND gates 43a and 43b to 43n and an N-input negative logic OR gate 44. The AND gates 43a and 43b to 43n correspond to the first gate, and the OR gate 44 corresponds to the second gate.

  The output signal of the transmission unit 40a and the output signals of the start bit detection units 41b to 41n are input to the AND gate 43a. The AND gate 43b receives an output signal from the transmission unit 40b and output signals from the start bit detection units 41a and 41c (not shown) to 41n. Similarly, the output signal of the transmission unit 40n and the output signal of the start bit detection unit excluding the start bit detection unit 41n are input to the AND gate 43n. The transmission units 40a and 40b to 40n and the AND gates 43a and 43b to 43n have a one-to-one correspondence.

  The output signals of the AND gates 43a and 43b to 43n are input to the OR gate 44. The output signal of the OR gate 44 is input to the receiver 14 via the communication path 13.

  While the transmission unit 40a is transmitting data, the output signal of the start bit detection unit 41a is at a high level (active). Therefore, the output signals of the transmission units 40b to 40n are masked by the AND gates 43b to 43n.

  Similarly, when the transmission unit 40n is transmitting data, the output signal of the start bit detection unit 41n becomes high level (active), and the output signals of the other transmission units are masked. That is, the output signal of the transmission unit excluding the transmission unit transmitting data is masked by the signal mask unit 42. Therefore, even if noise is superimposed on the output signal of a transmission unit other than the transmission unit that is transmitting data, the noise is masked by the signal mask unit 42, so that the reception unit 14 can receive an accurate signal. it can.

  FIG. 3 shows an example in which the start bit detection units 41a to 41n and the signal mask unit 42 are on the transmission units 40a to 40n side, but the present invention is not limited to this configuration, and the start bit detection units 41a to 41n are not limited to this configuration. All or a part of the signal mask unit 42 may be on the receiving unit side.

  In the first and second embodiments, the signal mask portion is configured by an AND gate and an OR gate, but is not limited to this configuration. In short, any configuration may be used as long as the output signal of the transmission unit not transmitting is masked using the output signal of the start bit detection unit.

  In these embodiments, a transmission signal having a high level when no signal is transmitted and having a low-level start bit for one clock at the start of the signal has been described. The present invention can also be applied to a transmission signal whose bit is high. In this case, when the start bit detection units 30, 31, 41a to 41n detect the start bit, the output signal is set to a low level for a certain period, and a positive logic gate may be used as the gate of the signal mask units 32, 42.

  In these embodiments, the asynchronous transmission signal is described, but the transmission signal is not limited to this signal. In short, any transmission signal having a start bit whose level changes for a certain period at the start of transmission may be used.

  In addition, the period during which the output signals of the start bit detection units 30, 31, 41a to 41n are activated may be longer than the period during which the transmission signal is transmitted. However, since it is not possible to transmit during the active period, the communication efficiency can be increased if the length of the transmission signal is the same as the active period.

  In these embodiments, the start bit is detected at the falling edge of the transmission signal, but may be detected at the rising edge of the transmission signal. If the transmission data following the start bit is “0”, the transmission signal corresponding to this transmission data is at a low level, so the time point for detecting the start bit is shifted, but the start bit is still detected. . However, if the detection time is shifted, unless the active period of the start bit detection unit output is shortened accordingly, a period during which transmission cannot be performed occurs and communication efficiency decreases.

  Furthermore, the start bit may be detected in addition to the rising and falling edges of the transmission signal or without using the rising and falling edges. For example, if the start bit is detected after confirming that the level of the start bit continues for a certain period (one clock), the start bit can be detected more reliably.

1 is a configuration diagram of Example 1. FIG. FIG. 6 is a characteristic diagram for explaining the operation of the first embodiment. FIG. 6 is a configuration diagram of Example 2. It is a block diagram of the conventional serial communication apparatus. It is a figure for demonstrating the format of an asynchronous method. It is a characteristic view for demonstrating operation | movement of the conventional serial communication apparatus.

10, 11, 40a, 40b to 40n Transmitter 13 Communication path 14 Receivers 30, 31, 41a, 41b to 41n Start bit detector 32, 42 Signal mask units 33, 34, 43a, 43b to 43n AND gates 35, 44 Orgate

Claims (5)

At least two transmitters for transmitting in a time division manner a transmission signal having a start bit indicating the start of transmission;
A transmission signal output by the transmission unit is input, and a start bit detection unit that activates the output signal for a predetermined period after detecting the start bit;
A transmission signal output from the transmission unit, and an output signal of the start bit detection unit, and a signal mask unit that masks an output signal of the transmission unit that is not transmitting based on the output signal of the start bit detection unit; ,
A serial communication device comprising:   2. The serial communication apparatus according to claim 1, wherein a period during which the start bit detection unit activates the output signal is a period during which a corresponding transmission unit transmits a transmission signal.   The serial communication device according to claim 1, wherein the transmission unit transmits data in an asynchronous manner. The signal mask portion is
The transmission signal transmitted by the transmission unit and the output signal of the start bit detection unit to which the output signal of the transmission unit other than the transmission unit is input are input, and the input signal is input when the output signal of the start bit detection unit is active A first gate for masking the transmitted signal,
A second gate that receives an output signal of the first gate and outputs a logical sum of the input signals;
The serial communication device according to claim 1, wherein the serial communication device is configured as follows.   The serial communication apparatus according to claim 1, wherein the number of the transmission units is two.

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