JP2010186858A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To remove a carbon nanotube formed on an insulating film and in a hole from the upper part of the insulating film without damaging the insulating film. <P>SOLUTION: A method includes the following steps. The insulating films 17 and 18 are formed to the upper part of a wiring 15a, and the hole 17a reaching the wiring 15a is formed by patterning the insulating films 17 and 18. The carbon nanotube 22 is formed to the upper surfaces of the insulating films 17 and 18 in the hole 17a, and second insulating films 23 are formed on the layer of the carbon nanotube 22. The carbon nanotube 22 is exposed by etching the second insulating films 23 while the second insulating films 23 are left in the recess of the layer of the carbon nanotube 22. The places of the upper ends of the carbon nanotube 22 are equalized by etching the carbon nanotube 22, the second insulating films 23 on the carbon nanotube 22 are etched and the carbon nanotube 22 is etched and removed from the upper surface of the insulating film 17 while being left in the hole 17a. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  As a wiring of a semiconductor device, a copper wiring having a damascene structure having a resistance lower than that of an aluminum wiring and a high current density is used. In addition, in a semiconductor device having a copper wiring, the wiring structure is required to further reduce the line width and further increase the current density tolerance in order to achieve higher integration. As one candidate for solving such a problem, carbon nanotubes having low resistance and high current density resistance are attracting attention.

Carbon nanotubes are superior in electromigration resistance, because electrons flow through ballistic conduction due to the shape anisotropy due to shape anisotropy, and about 1,000 times more current per unit area than copper. ing.
As a wiring structure of a semiconductor device using carbon nanotubes, a structure in which carbon nanotubes are extended from the bottom of holes in an insulating film in the film thickness direction and used as vias is known. Such a via is formed by the following method, for example.

  First, holes are formed on the wiring in the insulating film. Thereafter, a metal serving as a catalyst is formed on the wiring at the bottom of the hole, and carbon nanotubes are formed at the bottom of the hole by a CVD method. In this case, the carbon nanotube is controlled to a height equal to the depth of the hole. Subsequently, after forming a conductive film in the hole in which the carbon nanotube is formed and on the insulating film, the conductive film on the upper surface of the insulating film is patterned to form a wiring, or the conductive film is subjected to chemical mechanical polishing ( CMP) method or etch back.

Further, a structure in which electrodes formed on an insulating film are connected in the lateral direction by carbon nanotubes is known, and is formed by the following method.
First, after covering two electrodes adjacent in the horizontal direction with an insulating film, an opening is formed in a region straddling a part of the electrodes. Subsequently, after forming a catalyst film on the two electrodes exposed from the openings, carbon nanotubes connecting the two electrodes are formed in the openings. Thereafter, an insulating buried film is formed in the opening and on the insulating film, and the carbon nanotubes in the buried film that do not connect the electrodes are polished by CMP or removed by etching.

JP-A-2005-109465 JP 2006-49459 A

  When the carbon nanotubes are formed on the insulating film and in the holes of the insulating film, if the insulating film is polished by CMP, the upper surface of the insulating film is easily damaged by the hard carbon nanotubes. Further, since carbon nanotubes are difficult to chemically polish, they are likely to remain on the insulating film after CMP. Therefore, removal of the carbon nanotubes by CMP causes a decrease in the yield of the semiconductor device.

In addition, when a low-k insulating film is formed as an insulating film, an abrasive used for CMP enters the hole from between the carbon nanotubes, and further penetrates and damages the low-k insulating film. There is a risk of reducing the performance.
An object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving the yield.

According to one aspect of the present invention, a step of forming a first wiring over a semiconductor substrate, a step of forming a first insulating film over the first wiring, patterning the first insulating film, Forming a hole reaching the first wiring; forming a carbon nanotube layer in the hole and on the upper surface of the first insulating film; forming a second insulating film on the carbon nanotube layer; Etching the second insulating film to expose the carbon nanotube layer and leaving the second insulating film in a recess of the carbon nanotube layer; and etching the carbon nanotube layer to form an upper end of the carbon nanotube layer. Aligning the positions of the carbon nanotubes, etching the second insulating film on the carbon nanotube layer, and the carbon nanotubes The etching method of manufacturing a semiconductor device characterized by having the steps of leaving said holes thereby removing from the top surface of the first insulating film is provided.
The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not intended to limit the invention.

According to the present invention, after the second insulating film is formed in the holes of the first insulating film and on the carbon nanotubes on the first insulating film, the second insulating film and the carbon nanotubes are alternately etched to thereby form the carbon nanotubes. The top edges of the are aligned. Thereafter, the carbon nanotubes are etched until the first insulating film is exposed, leaving the carbon nanotubes in the holes of the first insulating film.
Therefore, the polishing process for leaving the carbon nanotubes in the holes and removing the carbon nanotubes from the first insulating film becomes unnecessary, and the first insulating film is caused by the occurrence of damage to the first insulating film due to the polishing agent or the polishing residue of the carbon nanotubes. Damage can be avoided.

FIG. 1 is a cross-sectional view (No. 1) showing a step of forming a semiconductor device according to the first embodiment of the present invention. 2A to 2C are cross-sectional views (part 2) illustrating the process of forming the semiconductor device according to the first embodiment of the invention. 2D to 2F are cross-sectional views (part 3) illustrating the process of forming the semiconductor device according to the first embodiment of the invention. 2G to 2I are cross-sectional views (part 4) illustrating the process of forming the semiconductor device according to the first embodiment of the invention. 2J to 2L are cross-sectional views (part 5) illustrating the process of forming the semiconductor device according to the first embodiment of the invention. 2M and 2N are cross-sectional views (part 6) illustrating the process of forming the semiconductor device according to the first embodiment of the invention. 2O and 2P are cross-sectional views (part 7) illustrating the process of forming the semiconductor device according to the first embodiment of the invention. FIG. 3 is a cross-sectional view showing the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a diagram showing the etching rate values of the SOG film and the carbon nanotube depending on the flow rate ratio of O ₂ and CF _{4 in} the process of forming the semiconductor device according to the embodiment of the present invention. 5A to 5C are cross-sectional views showing other examples in the process of forming the semiconductor device according to the first embodiment of the present invention. 6A to 6C are cross-sectional views illustrating a process for forming a semiconductor device according to the second embodiment of the present invention. 7A to 7C are cross-sectional views (No. 1) showing a process for forming a semiconductor device according to the third embodiment of the present invention. 7D to 7F are cross-sectional views (part 2) illustrating the process of forming the semiconductor device according to the third embodiment of the invention. 8A to 8C are cross-sectional views (part 1) illustrating the process of forming the semiconductor device according to the fourth embodiment of the invention. 8D to 8F are cross-sectional views (part 2) illustrating the process of forming the semiconductor device according to the fourth embodiment of the invention. 8G to 8I are cross-sectional views (part 3) illustrating the process of forming the semiconductor device according to the fourth embodiment of the invention. 8J to 8L are cross-sectional views (part 4) illustrating the process of forming the semiconductor device according to the fourth embodiment of the invention. 8M to 8O are cross-sectional views (part 5) illustrating the process of forming the semiconductor device according to the fourth embodiment of the invention. FIG. 9 is a sectional view showing a semiconductor device according to the fourth embodiment of the present invention. FIG. 10A is a cross-sectional view showing a semiconductor device according to the fifth embodiment of the present invention, and FIG. 10B is a plan view showing a formation region of the semiconductor device according to the fifth embodiment of the present invention. FIGS. 11A and 11B are cross-sectional views (part 1) illustrating the process of forming the semiconductor device according to the fifth embodiment of the invention. 11C and 11D are cross-sectional views (part 2) illustrating the process of forming the semiconductor device according to the fifth embodiment of the invention. 11E and 11F are cross-sectional views (part 3) illustrating the process of forming the semiconductor device according to the fifth embodiment of the invention. 11G and 11H are cross-sectional views (part 4) illustrating the process of forming the semiconductor device according to the fifth embodiment of the invention. FIGS. 11I and 11J are cross-sectional views (part 5) illustrating the process of forming the semiconductor device according to the fifth embodiment of the invention. 11K and 11L are cross-sectional views (part 6) illustrating the process of forming the semiconductor device according to the fifth embodiment of the invention. 11M and 11N are cross-sectional views (No. 7) showing the process of forming the semiconductor device according to the fifth embodiment of the invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the drawings, similar components are given the same reference numerals.
₍ First embodiment)
1 and 2A to 2P are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention.
Next, steps required until a structure shown in FIG.
First, an element isolation insulating film 2, for example, a shallow trench isolation (STI) is formed in a silicon substrate 1 that is a semiconductor substrate. The STI is formed by forming a groove in the element isolation region of the silicon substrate 1 and then embedding an insulating film such as a silicon oxide film in the groove. Note that a silicon oxide film formed on the surface of the silicon substrate 1 by the LOCOS method may be employed as the element isolation insulating film 2.

Next, in the silicon substrate 1, an active region surrounded by the element isolation insulating film 2, for example, N-type MO
A p-well 3 is formed by ion implantation of a p-type impurity such as boron into the S transistor formation region. In the region where the P-type MOS transistor is to be formed, an n-well is formed in the active region of the silicon substrate 1.

  Subsequently, a gate insulating film 4 is formed on the surface of the silicon substrate 1 by, for example, a thermal oxidation method, and a gate electrode 5 is formed on the p-well 3 via the gate insulating film 4. The method for forming the gate electrode 5 includes, for example, a step of patterning the silicon film by photolithography using a resist pattern after forming a silicon film on the gate insulating film 4.

Next, n-type extension regions 7 a and 8 a are formed in the p-well 3 on both sides of the gate electrode 5 by ion-implanting n-type impurities such as phosphorus or arsenic using the gate electrode 5 as a mask.
Subsequently, for example, after a silicon oxide film is formed as an insulating film on the silicon substrate 1 and the gate electrode 5 by the CVD method, the insulating film is etched back and left on the side surface of the gate electrode 5. To do.

  Further, by using the gate electrode 5 and the sidewall 6 as a mask, n-type impurities are ion-implanted into the p-well 3, whereby the n-type impurity high-concentration region 7 b and the p-well 3 on both sides of the gate electrode 5 are formed. 8b is formed. Here, the n-type impurity high concentration regions 7b and 8b and the n-type extension regions 7a and 8b connected to each other become the source / drain regions 7 and 8, respectively.

An N-type MOS transistor is formed by the source / drain regions 7 and 8, the gate electrode 5, the p-well 3, and the like.
Subsequently, a cover film 9, for example, a silicon nitride film covering the N-type MOS transistor is formed on the silicon substrate 1 by the CVD method. Further, a silicon oxide film is formed as a first interlayer insulating film 10 on the cover film 9 by a CVD method.

  Next, after planarizing the upper surface of the first interlayer insulating film 10 by a CMP method, the first interlayer insulating film 10 and the cover film 9 are patterned by a photolithography method using a resist pattern. As a result, contact holes 10 a and 10 b are formed on the source / drain regions 7 and 8. A hole (not shown) is also formed on the wiring connected to the gate electrode 5.

  Further, after forming titanium (Ti) and titanium nitride (TiN) in the contact holes 10a and 10b by sputtering, a tungsten (W) film is formed on the TiN film by CVD. Thereafter, the W film, the TiN film, and the Ti film on the first interlayer insulating film 10 are removed by a CMP method. As a result, the W film, TiN film, and Ti film remaining in the contact holes 10a and 10b are used as contact plugs 11 and 12, respectively.

  Next, a first low-k insulating film 13 that is a second interlayer insulating film is formed on the first interlayer insulating film 10. A carbon-containing silicon oxide (SiOC) film is formed as the low-k insulating film 13 by a CVD method, but other films, for example, an SOG film may be formed by a coating method. The low-k material is a material having a dielectric constant lower than that of the silicon oxide film.

Further, a mask (not shown) having a wiring-shaped opening is formed on the first Low-k insulating film 13 in a region including the contact plugs 11 and 12. Next, the first low-k insulating film 13 is etched through the opening of the mask to form first wiring grooves 13a and 13b. Etching of the first Low-k insulating film 13 is performed by a plasma etching method or a reactive ion etching (RIE) method using, for example, a gas containing CF ₄ .

  Subsequently, a barrier metal film 14a and a copper (Cu) seed film (not shown) are sequentially formed in the first wiring grooves 13a and 13b by a sputtering method. After that, a barrier metal film 14a and a copper seed film are used as electrodes, and a copper film 14b is formed thereon by an electrolytic plating method. Thus, the Cu film 14b is embedded in the first wiring grooves 13a and 13b. The Cu film may be a copper alloy, and the same applies to the following embodiments.

  Thereafter, the Cu film 14b and the barrier metal film 14a on the upper surface of the first Low-k insulating film 13 are removed by a CMP method. As a result, the Cu film 14b and the barrier metal film 14a remaining in the first wiring grooves 13a and 13b are used as first-layer wirings 15a and 15b. The barrier metal film 14a is a film for preventing copper diffusion, and for example, a tantalum (Ta) film is formed.

Next, a first barrier insulating film 16 and a second Low-k insulating film 17 are formed as a third interlayer insulating film on the first-layer wirings 15 a and 15 b and the first Low-k insulating film 13. Then, the cap insulating film 18 is formed in order. For example, a carbon hydrogenated silicon (SiCH) film is formed as the first barrier insulating film 16 to a thickness of, for example, about 30 nm by a plasma CVD method, and a SiOC film is formed as the second low-k insulating film 17 by a plasma CVD method. For example, it is formed to a thickness of about 150 nm. Further, although the SiCH film is formed as the cap insulating film 18 to a thickness of about 30 nm by the plasma CVD method, other low dielectric SiO type films such as SiOC and SiO ₂ may be formed.
Subsequently, a first antireflection (BARC) film 19 is formed on the cap insulating film 18. In this embodiment, an organic insulating film is formed as the first BARC film 19, but an inorganic insulating film may be formed.

Next, the formation process of the second layer wiring will be described with reference to FIGS. 2A to 2P. 2A to 2P show the upper portion of the first interlayer insulating film 10 shown in FIG. 1 and the structure thereon.
First, as shown in FIG. 2A, a photoresist is applied on the first BARC film 19, and this is exposed and developed to form via holes on the first-layer wirings 15a and 15b. A resist pattern 20 having openings 20a and 20b is formed.

Subsequently, using the resist pattern 20 as a mask, the cap insulating film 18 is exposed from the openings 20a and 20b by dry etching the first BARC film 19 by, for example, plasma etching or RIE. For example, a gas having CF ₄ is used as a reactive gas used for etching the first BARC film 19 made of an organic material.

Next, as shown in FIG. 2B, via holes 17a and 17b are formed in the first barrier insulating film 16, the second low-k insulating film 17, and the cap insulating film 18 by the following method.
First, the cap insulating film 18 is etched by plasma etching through the openings 20a, 20b of the resist pattern 20, thereby forming via holes 17a, 17b. For example, a gas containing CH ₂ F ₂ is used as an etching gas for the SiCH film that is the cap insulating film 18.

For example, CH ₂ F ₂ is introduced into the etching chamber at a flow rate of about 30 sccm, O ₂ is about 10 sccm, and N ₂ is about 50 sccm, and the exhaust amount is adjusted so that the pressure in the etching chamber becomes 20 mTorr. In this case, 300 W of high frequency power is applied to the electrode of the etching chamber.

Further, by using the resist pattern 20 and the cap insulating film 18 as a mask, the second low-k insulating film 17 is etched by, for example, a plasma etching method to deepen the via holes 17a and 17b. As an etching gas in this case, a gas having a high etching selectivity with respect to the cap insulating film 18 and the first barrier insulating film 16, that is, the SiCH film, for example, a gas containing C ₄ F ₆ , O ₂ and Ar is used.

  Further, by using the resist pattern 20, the first BARC film 19 and the cap insulating film 18 as a mask, the first barrier insulating film 16 is etched by, for example, a plasma etching method to further deepen the via holes 17a and 17b. A part of the wiring 15a, 15b of the eye is exposed. As the etching conditions, for example, the same etching conditions as those for the cap insulating film 18 are set.

  After removing the resist pattern 20 and the first BARC film 19, as shown in FIG. 2C, the catalyst is formed on the first layer wirings 15a and 15b at the bottom of the via holes 17a and 17b and on the cap insulating film 18, respectively. Metal fine particles 21 are formed. In this embodiment, cobalt (Co) particles are formed as the catalyst metal fine particles 21. Instead of the catalytic metal particles 21, a catalytic metal film having a thickness of about 1 nm may be formed.

  As the catalytic metal fine particles 21, in addition to Co, iron (Fe), nickel (Ni), or a binary metal containing any one of them may be used, for example, TiCo. The catalytic metal fine particles 21 are formed by a laser ablation method, a sputtering method, a vapor deposition method, or the like. In these methods, it is preferable to set conditions for increasing the catalyst element deposition anisotropy in the direction perpendicular to the upper surface of the silicon substrate 1.

Next, as shown in FIG. 2D, a plurality of carbon nanotubes 22 extending in a substantially vertical direction from the upper surfaces of the first-layer wirings 15a and 15b on which the catalytic metal fine particles 21 are formed and the upper surface of the cap insulating film 18 are formed by a CVD method. To form. The carbon nanotube 22 is formed to have a length at least equal to the depth of the via holes 17a and 17b or longer.
Since the carbon nanotubes 22 are formed to have almost the same length above the silicon substrate 1, the layers made of a large number of carbon nanotubes 22 have depressions on the via holes 17a and 17b.

  Examples of the CVD method for forming the carbon nanotube 22 include a thermal CVD method, a hot filament method, and a plasma CVD method. When the thermal CVD method is employed, for example, a mixed gas of acetylene and argon is introduced as a reaction gas into a vacuum chamber that is a growth atmosphere. For example, the flow rates of acetylene and argon gas are 0.5 sccm and 1000 sccm, respectively. As other growth conditions, the pressure in the vacuum chamber is set to 1 kPa, and the substrate temperature is set to 400 ° C. to 450 ° C.

Subsequently, the carbon nanotubes 22 are removed from the upper surface of the cap insulating film 18 by the following method, while being left short in the via holes 17a and 17b.
First, as shown in FIG. 2E, a spin-on-glass (SOG) film 23 is formed as a coating system insulating film on a number of carbon nanotube 22 layers. As a method for forming the SOG film 23, for example, SOG is applied by spin coating, and after the formation, the SOG is baked by heating at a temperature of about 250 ° C. for about 5 minutes, and subsequently, for example, at a temperature of about 400 ° C. for about 3 minutes. A method of curing and curing SOG by heating is employed.

The SOG film 23 is formed on the carbon nanotube 22 layer to a thickness of about 300 nm, for example, and the upper surface thereof is almost flattened. A part of the SOG film 23 enters a gap between the carbon nanotubes 22.
Thereafter, the silicon substrate 1 is placed in, for example, an etching chamber of a plasma etching apparatus, and the SOG film 23 and the carbon nanotube 22 are alternately etched as follows.

First, as shown in FIG. 2F, the SOG film 23 is etched until the carbon nanotubes 22 are exposed.
In the etching of the SOG film 23, a fluorocarbon-based gas such as CF ₄ as a reaction gas is introduced into the etching chamber at a flow rate of 100 sccm to 200 sccm, and the pressure in the etching chamber becomes 20 mTorr to 200 mTorr (2.7 Pa to 27 Pa). Adjust the displacement so that. In this case, a high frequency power of 100 to 500 W is applied to the electrodes of the etching chamber. Fluorocarbon-based gas includes C ₄ F ₆ and C ₄ F _{8 in} addition to CF ₄ .

As a result, the SOG film 23 remains thick in the recesses on the via holes 17a and 17b in the layer of the carbon nanotubes 22 and is removed in the other regions to expose the upper ends of the carbon nanotubes 22.
Subsequently, the carbon nanotubes 22 are etched by switching the reaction gas introduced into the etching chamber from a fluorocarbon system to an oxygen system. As a result, as shown in FIG. 2G, the side portions of the thick SOG film 23 above the via holes 17a and 17b are exposed.

In the etching, for example, O ₂ is introduced as a reaction gas at a flow rate ratio of about 200 sccm and CF ₄ at a flow rate ratio of 10 to 50 sccm, and the exhaust amount is adjusted so that the pressure in the etching chamber becomes 20 mTorr to 200 mTorr. . In this case, high frequency power of 100 W to 500 W is applied to the electrodes of the etching chamber.

  Under such an etching condition, the SOG film 23 that remains partially thick on the carbon nanotube 22 layer functions as an etching mask, and the length of the carbon nanotube 22 under the SOG film 23 does not change substantially. The carbon nanotube 22 becomes shorter. Note that the slight SOG in the gap between the carbon nanotubes 22 is etched together with the carbon nanotubes 22.

  Subsequently, as shown in FIG. 2H, the SOG film 23 is etched by switching the reaction gas introduced into the etching chamber from the oxygen system to the fluorocarbon system. The etching conditions are set to be the same as the etching conditions for the SOG film 23 shown in FIG. 2F. As a result, the SOG film 23 above the via holes 17a and 17b becomes thin.

  Next, as shown in FIG. 2I, the reaction gas introduced into the etching chamber is switched from the fluorocarbon system to the oxygen system to etch the carbon nanotubes 22, thereby aligning the upper end positions of the layers of the carbon nanotubes 22. The etching conditions are set to be the same as the etching conditions for the carbon nanotube 22 shown in FIG. 2G.

  Subsequently, as shown in FIG. 2J, the reaction gas introduced into the etching chamber is switched from the oxygen system to the fluorocarbon system and the SOG film 23 is etched to remove it from the upper end of the carbon nanotube 22. The etching conditions are set to be the same as the etching conditions shown in FIG. 2F.

  Next, as shown in FIG. 2K, the reactive gas introduced into the etching chamber is switched from the fluorocarbon system to the oxygen system, and the carbon nanotubes 22 are etched until the catalyst metal fine particles 21 or the cap insulating film 18 are exposed. The etching conditions are set to be the same as the etching conditions shown in FIG. 2G.

As a result, the carbon nanotubes 22 left in the via holes 17a and 17b are used as vias 22a and 22b for connecting the upper and lower wirings. Since the cap insulating film 18 is made of SiCH, the second Low-k insulating film 17 is shielded from oxygen plasma generated in the etching chamber, and damage to the second Low-k insulating film 17 is prevented. be able to.

By the way, in the above etching, in order to selectively etch one of the carbon nanotubes 22 and the SOG film 23, the gas introduced into one etching chamber is switched between an oxygen system and a fluorocarbon system. These gases are preferably set to conditions utilizing the properties shown in FIG.
FIG. 4 shows the change in the etching rate of the SOG film and the carbon nanotube (CNT) by changing the flow rate ratio between O ₂ introduced into the etching chamber and CF ₄ which is fluorocarbon.

In FIG. 4, if the O ₂ flow rate is too small relative to the CF ₄ flow rate, the etching rate of the SOG film 23 increases and the etching rate of the carbon nanotubes 22 decreases. On the other hand, if the O ₂ flow rate is excessively increased with respect to the CF ₄ flow rate, the etching rate of the SOG film 23 is lowered while the etching rate of the carbon nanotubes 22 is raised.

When the flow rate ratio of O ₂ to CF ₄ is changed in this way, a peak exists in the etching rate of the carbon nanotubes 22, and the etching rate of the SOG film 23 becomes extremely low at the flow rate ratio of the peak.
According to experiments, in order to selectively etch the carbon nanotubes 22 with respect to the SOG film 23, the ratio of the CF ₄ flow rate to the total gas flow rate of O ₂ and CF ₄ is 20 flow% or less, for example, 20 flow% to It is desirable to set the flow rate to 5%, and the introduction of CF ₄ may be stopped and only O ₂ may be introduced. Such a gas flow ratio is defined as the oxygen-based gas.

On the other hand, in order to selectively etch the SOG film 23, the ratio of the CF ₄ flow rate to the total gas flow rate of O ₂ and CF ₄ is preferably larger than 20 flow%, and the introduction of O ₂ is stopped. Thus, only CF ₄ may be introduced. Such a gas flow rate ratio is the above-described fluorocarbon system. Also, argon (Ar), for example, may be introduced into the etching chamber as an inert gas simultaneously with O ₂ and CF ₄ to form a mixed gas of CF ₄ , O ₂ , and Ar.

Note that another fluorocarbon such as CF ₄ , for example, C ₄ F ₈ may be used. When the SOG film 23 is selectively etched, CF ₄ is mixed with a deposition gas such as CHF ₃ , CH ₂ F ₂ , C ₄ F ₆ , C ₄ F _8, etc. You may set it as the conditions which make high.

Next, the catalyst metal fine particles 21 on the cap insulating film 18 are removed by, for example, plasma etching. For example, a fluorocarbon-based gas containing CF ₄ is used as the etching gas for the catalytic metal fine particles 21. Details thereof will be described later.

  Next, as shown in FIG. 2L, a third Low-k insulating film 25 and a hard mask layer 26 are formed on the cap insulating film 18 and the vias 22a and 22b as a fourth interlayer insulating film, for example, about 150 nm. They are formed in order to a thickness of 30 nm. For example, a SiOC film is formed as the third Low-k insulating film 25 by a plasma CVD method, and a SiCH film is formed as the hard mask layer 26 by a plasma CVD method.

  Subsequently, as shown in FIG. 2M, a second BARC film 27 is formed on the hard mask layer 26. In this embodiment, an organic material is used as the second BARC film 27, but an inorganic material may be used. Further, a photoresist is applied on the second BARC film 27, and this is exposed, developed, and the like. As a result, a resist pattern 28 having wiring openings 28a and 28b passing over the first and second vias 22a and 22b is formed.

Subsequently, the second BARC film 27 is etched using the resist pattern 28 as a mask, thereby exposing a part of the hard mask layer 26 from the wiring openings 28a and 28b. Further, by etching the hard mask layer 26 using the resist pattern 28 as a mask, openings are further formed under the wiring openings 28a and 28b.
The etching of the second BARC film 27 is performed under the same conditions as the etching of the first BARC film 18, and the etching of the SiCH film as the hard mask layer 26 is performed under the same conditions as the etching of the cap insulating film 18. Is called.

  Further, the third low-k insulating film 25 is etched using the resist pattern 28, the second BARC film 27, and the hard mask layer 26 as a mask. Thereby, as shown in FIG. 2N, second wiring grooves 25a and 25b are formed under the openings 28a and 28b of the resist pattern 28, and vias 22a and 22b, that is, the upper ends of the carbon nanotubes 22 are formed from a part thereof. Exposed. The etching of the third Low-k insulating film 25 is performed under the same conditions as the etching of the second Low-k insulating film 17.

  Subsequently, after removing the resist pattern 28 and the second BARC film 27, as shown in FIG. 2O, a barrier metal film 29a and a copper seed film (not shown) are formed in the second wiring grooves 25a and 25b. It forms in order by sputtering method. Thereafter, a Cu film 29b is formed in the second wiring grooves 25a and 25b. The Cu film 29b is formed by electrolytic plating using the barrier metal film 29a and the copper seed film as electrodes. For example, a Ta film is formed as the barrier metal film 29a.

  Further, as shown in FIG. 2P, the Cu film 29b, the barrier metal film 29a, and the hard mask layer 26 on the upper surface of the third Low-k insulating film 25 are removed by the CMP method. As a result, the Cu film 29b remaining in the second wiring grooves 25a and 25b is used as second-layer wirings 30a and 30b. The second layer wirings 30a and 30b are electrically connected to the first layer wirings 15a and 15b through the vias 22a and 22b.

Next, as shown in FIG. 3, a SiCH film is formed as a second barrier insulating film 31 on the second layer wirings 30a and 30b and the third Low-k insulating film 25 to a thickness of about 30 nm. To do.
After that, by repeatedly forming vias, wirings, insulating films and the like connected to the second layer wirings 30a and 30b, a multilayer wiring structure is formed.

  As described above, according to the present embodiment, the carbon nanotubes 22 are formed on the cap insulating film 18 and in the via holes 17a and 17b, and the SOG film 23 is further formed on the carbon nanotube 22 layer. Yes. Thereafter, the SOG film 23 is etched to expose the carbon nanotubes 22, leave the SOG film 23 in the recesses of the carbon nanotube 22 layer, and further etch the carbon nanotubes 22 using the SOG film 23 as a mask.

  Thereby, even if unevenness occurs in the upper part of the layer of the carbon nanotubes 22, the upper end of the layer can be flattened by etching the carbon nanotubes 22 in the protruding parts while leaving the SOG film in the recessed parts. Then, after removing the SOG film 23, the carbon nanotubes 22 are etched from the upper surface of the cap insulating film 18 by dry etching to selectively leave the carbon nanotubes 22 in the via holes 17 a and 17 b. Thereby, the carbon nanotubes 22 in the via holes 17a and 17b can be used as the vias 22a and 22b.

Therefore, polishing for selectively leaving the carbon nanotubes 22 in the via holes 17a and 17b becomes unnecessary. As a result, the low-k insulating film is not damaged by the polishing agent, and the interlayer insulating film is not damaged by the polishing residue of the carbon nanotubes 22.

  Further, by setting conditions for selectively etching the carbon nanotubes 22 with respect to the cap insulating film 18 thereunder, the cap insulating film 18 can be used as an etching end point detection surface, and the carbon in the via holes 17a and 17b can be obtained. Excessive etching of the nanotubes 22 can be prevented.

  Furthermore, since the cap insulating film 18 is formed on the second Low-k insulating film 17, damage to the Low-k insulating film 17 due to oxygen plasma that is an etchant of the carbon nanotubes 22 can be prevented.

Incidentally, CF ₄ which is a fluorocarbon-based gas may be used as an etching gas used for removing the catalyst metal fine particles 21 on the cap insulating film 18 described above. In order to increase the etching rate of the catalytic metal fine particles 21, it is preferable to include carbon monoxide (CO) in the fluorocarbon-based gas.

  For example, by the above method, the upper end of the carbon nanotube 22 layer is aligned above the silicon substrate 1 as shown in FIG. 5A, and then oxygen-based gas is used under the above conditions as shown in FIG. 5B. Then, the carbon nanotubes 22 are etched. Thereby, the catalyst metal particles 21 are exposed. Therefore, the gas introduced into the etching chamber is switched to a fluorocarbon system, and CO gas is also introduced.

For example, as etching conditions for the catalytic metal particles 21, CF ₄ is introduced into the etching chamber at a flow rate ratio of about 200 sccm and CO is flowed at a rate of 100 sccm to 400 sccm, and the exhaust amount is set so that the pressure in the etching chamber is 20 mTorr to 200 mTorr. adjust. In this case, high frequency power of 100 W to 500 W is applied to the electrodes in the etching chamber.

When CO gas is introduced, Co or Ni which is the catalytic metal particle 21 reacts with CO to generate Ni (CO) ₄ and Co ₂ (CO) _{8 which} are metal carbonyl compounds, which are sublimated, and the catalytic metal particle 21 Etching is accelerated. Thereby, as shown in FIG. 5C, the catalyst metal particles 21 are removed from the cap insulating film 18.

(Second Embodiment)
6A to 6C are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the second embodiment of the present invention. 6A to 6C show structures from the top to the upper side of the first interlayer insulating film 10 in the structure shown in FIG.

  First, as shown in FIG. 1, after forming the cover film 9 and the first interlayer insulating film 10 on the N-type MOS transistor formed on the silicon substrate 1, the source / drain regions 7, 8 of the N-type MOS transistor are formed. Contact plugs 11 and 12 are formed to be connected to.

  Further, a first low-k insulating film 11 is formed on the first interlayer insulating film 10 and the contact plugs 11 and 12, and first-layer wirings 13a and 13b connected to the contact plugs 15a and 15b are formed therein. Form. Thereafter, the first barrier insulating film 16, the second Low-k insulating film 17, and the cap insulating film 18 are formed in this order on the first Low-k insulating film 11 and the first-layer wirings 13a and 13b. . The formation method is the same as in the first embodiment.

Further, as in the first embodiment shown in FIG. 2B, the first barrier insulating film 16 and the second Low
-K insulating film 17 and cap insulating film 18 are patterned to form via holes 17a and 17b.
Next, similarly to the first embodiment shown in FIG. 2C, after forming the catalytic metal particles 21 on the upper surfaces of the first-layer wirings 15a and 15b at the bottom of the via holes 17a and 17b and the upper surface of the cap insulating film 18, Carbon nanotubes 22 are formed on those surfaces as shown in FIG. 2D.

Next, as shown in FIG. 6A, a photoresist film 32 is formed as a coating-based organic film on the carbon nanotube 22 layer. As a method of forming the photoresist film 32, for example, a photoresist such as a novolac resin is applied by a spin coating method, and the upper surface thereof is flattened. Further, the photoresist film 32 is baked and cured at about 300 ° C., for example.
In place of the photoresist film 32, a resin film such as polyimide may be formed.

For example, the thickness of the photoresist film 32 is set to about 300 nm in the thinnest region on the carbon nanotube 22. A part of the photoresist film 32 enters a state above the gap between the carbon nanotubes 22.
Next, the silicon substrate 1 is put into an etching chamber of a plasma etching apparatus, for example, and the photoresist film 32 and the carbon nanotube 22 are etched until the cap insulating film 18 or the catalytic metal 21 is exposed as shown in FIGS. 6B and 6C. . Etching of the photoresist film 32 and the carbon nanotube 22 may be performed continuously under the same conditions, but in order to ensure superiority in etching selectivity, etching rate, etc., it is preferable to change as follows.

First, as shown in FIG. 6B, the photoresist film 32 is etched until the carbon nanotubes 22 are exposed. As the etching conditions, for example, O ₂ is introduced as a reactive gas into the etching chamber at a flow rate of 200 sccm, and the exhaust amount is adjusted so that the pressure in the etching chamber becomes 50 mTorr to 200 mTorr. In this case, high frequency power of 200 W to 500 W is applied to the electrodes of the etching chamber.

  Subsequently, the carbon nanotubes 22 and the photoresist film 32 are simultaneously etched until the photoresist film 32 disappears, as shown in FIG. 6C, with the photoresist film 32 remaining in the concave portion of the layer of the carbon nanotubes 22. Thereby, the upper end of the carbon nanotube 22 is flattened above the via holes 17a and 17b.

As the conditions, for example, O ₂ is introduced as a reaction gas at a rate of 200 sccm and CF ₄ is introduced into the etching chamber at a flow rate of 100 sccm to 400 sccm, and the exhaust amount is adjusted so that the pressure in the etching chamber is 50 mTorr to 100 mTorr. . In this case, high frequency power of 200 W to 500 W is applied to the electrodes of the etching chamber. Here, the reason why CF ₄ which is a fluorocarbon is added is derived from the result shown in FIG.

  Thereafter, the etching conditions are changed to increase the etching selectivity of the carbon nanotubes 22 with respect to the cap insulating film 18, and the carbon nanotubes 22 on the cap insulating film 18 are etched in the same manner as shown in FIG. 2K. The etching conditions are set in the same manner as in the first embodiment.

  Thus, the carbon nanotubes 22 left selectively in the via holes 17a and 17b are defined as vias 22a and 22b. Note that the cap insulating film 18 can prevent damage to the second low-k insulating film 17 due to oxygen plasma generated in the etching chamber.

  Next, as in the first embodiment, the catalyst metal fine particles 21 on the cap insulating film 18 are removed. Thereafter, the third low-k insulating film 25, the hard mask layer 26, and the like are formed by the method described in the first embodiment. Further, the second layer wirings 30a and 30b connected to the vias 22a and 22b are formed in the third Low-k insulating film 25 by the same method as in the first embodiment, as shown in FIG. .

As described above, according to the present embodiment, after the carbon nanotube 22 is formed on the cap insulating film 18 and in the via holes 17a and 17b therein, the photoresist film 32 is formed on the carbon nanotube 22. The upper surface is made flat.
Since the photoresist film 32 is formed of an organic material, the photoresist film 32 and the carbon nanotube 22 can be etched at substantially the same etching rate by using an oxygen-based gas by adjusting the conditions.

  Thereby, when the carbon nanotubes 22 on the upper surface of the cap insulating film 18 are removed, the carbon nanotubes 22 can be left as the vias 22a and 22b in the via holes 17a and 17b.

  Therefore, a polishing step for selectively leaving the carbon nanotubes 22 in the via holes 17a and 17b is unnecessary, and the abrasive enters the via holes 17a and 17b and damages the second Low-k insulating film 17. There is no. Further, since the carbon nanotubes 22 are dry-etched, the surface of the interlayer insulating film is not damaged by the carbon nanotube residues. In addition, by setting conditions for selectively etching the carbon nanotubes 22 with respect to the first hard mask insulating film 18 thereunder, the exposure of the first hard mask insulating film 18 is used as an etching end point detection surface. And excessive etching can be prevented.

(Third embodiment)
7A to 7F are cross-sectional views illustrating manufacturing steps of the semiconductor device according to the third embodiment of the present invention. 7A to 7F show structures on the upper side of the first interlayer insulating film 10 in the structure shown in FIG.

  First, similarly to the first embodiment shown in FIG. 1, after forming a cover film 9 and a first interlayer insulating film 10 covering the N-type MOS transistor on the silicon substrate 1, the source / drain of the N-type MOS transistor is formed. Contact plugs 11 and 12 connected to the regions 7 and 8 are formed.

  Further, a first low-k insulating film 13 is formed on the first interlayer insulating film 10 and the contact plugs 11 and 12, and first-layer wirings 15a and 15b connected to the contact plugs 11 and 12 are formed therein. Form. Thereafter, the first barrier insulating film 16, the second Low-k insulating film 17, and the cap insulating film 18 are formed in this order on the first Low-k insulating film 11 and the first-layer wirings 15a and 15b. .

Further, similarly to the first embodiment shown in FIG. 2B, the first barrier insulating film 16, the second low-k insulating film 17, and the cap insulating film 18 are patterned to form via holes 17a and 17b.
Next, as shown in FIG. 7A, catalytic metal particles 21 are formed on the upper surfaces of the first-layer wirings 15 a and 15 b at the bottom of the via holes 17 a and 17 b and the upper surface of the cap insulating film 18. The catalytic metal particles 21 are formed by, for example, the method shown in the first embodiment.

Subsequently, as shown in FIG. 7B, the silicon substrate 1 is placed in an etching chamber of a plasma etching apparatus, for example, a capacitively coupled plasma etching apparatus, and catalytic metal particles 21 are removed from the upper surface of the cap insulating film 18 using a fluorocarbon-based gas. Remove. In this case, the catalytic metal particles 21 are selectively left on the bottoms of the via holes 17a and 17b under the following conditions.

As the conditions, for example, CF ₄ which is fluorocarbon is introduced into the etching chamber at a flow rate ratio of about 200 sccm and CO at 100 sccm to 400 sccm. In this case, the pressure in the etching chamber is set to 200 mTorr or more, for example, 200 mTorr to 300 mTorr. Further, high frequency power of 100 W to 500 W is applied to the electrodes of the etching chamber.

  Next, as shown in FIG. 7C, carbon nanotubes 22 are selectively formed by CVD in the via holes 17a and 17b on the first-layer wirings 15a and 15b where the catalytic metal particles 21 remain. The carbon nanotubes 22 are formed to have a length that protrudes upward from the via holes 17a and 17b by setting, for example, the conditions shown in the first embodiment.

Subsequently, as shown in FIG. 7D, the SOG film 23 is formed on the carbon nanotubes 22 and the cap insulating film 18 with the same method and conditions as in the first embodiment so as to cover the carbon nanotubes 22 with a thickness of, for example, 300 nm. Form.
Further, as shown in FIG. 7E, the SOG film 23 is etched by a plasma etching method using a fluorocarbon-based gas to expose the upper part of the carbon nanotubes 22.

In the etching of the SOG film 23, a fluorocarbon gas such as CF ₄ as a reaction gas is introduced into the etching chamber at a flow rate of 100 sccm to 200 sccm, and the pressure in the etching chamber is adjusted to 20 mTorr to 200 mTorr. In this case, high frequency power of 100 W to 500 W is applied to the electrodes of the etching chamber.

  Next, the carbon nanotubes 22 are etched by switching the reaction gas introduced into the etching chamber from the fluorocarbon system to the oxygen system. As a result, as shown in FIG. 7F, the carbon nanotubes 22 are adjusted to the same height as or lower than the via holes 17a and 17b, and used as the vias 22a and 22b.

In the etching, for example, O ₂ is introduced as a reaction gas at a flow rate ratio of about 200 sccm and CF ₄ at a flow rate ratio of 10 sccm to 50 sccm, and the exhaust amount is adjusted so that the pressure in the etching chamber is 20 mTorr to 200 mTorr. . In this case, high frequency power of 100 W to 500 W is applied to the electrodes of the etching chamber.

  Subsequently, the etching gas is switched from an oxygen system to a fluorocarbon system, and the SOG film 23 is selectively etched to expose the upper surface of the cap insulating film 18. As a result, the upper surface of the cap insulating film 18 is exposed in the same manner as shown in FIG. 2K of the first embodiment. The etching conditions are the same as the etching of the SOG film 23 shown in FIG. 7E, for example.

  Next, as in the first embodiment, the catalyst metal fine particles 21 on the cap insulating film 18 are removed. Thereafter, the third low-k insulating film 25, the hard mask layer 26, and the like are formed by the method described in the first embodiment. Further, as shown in FIG. 3, second layer wirings 30 a and 30 b connected to the vias 22 a and 22 b are formed in the third Low-k insulating film 25 by the same method as in the first embodiment.

As described above, according to the present embodiment, the catalytic metal particles 21 are etched in the via holes 17a and 17b in the cap insulating film 18 by etching the catalytic metal particles 21 using a fluorocarbon gas under a pressure of 200 mTorr or more. Leave selectively. Then, carbon nanotubes 22 are formed in the via holes 17 a and 17 b, and an SOG film 23 is formed on the carbon nanotubes 22. Next, the SOG films 23 and the carbon nanotubes 22 are alternately etched, and portions of the carbon nanotubes 22 that protrude from the via holes 17a and 17b are etched. As a result, the carbon nanotubes 22 left in the via holes 17a and 17b are applied as the vias 22a and 22b.

Accordingly, the CMP process for leaving the carbon nanotubes 22 in the via holes 17a and 17b is unnecessary, and the third Low-k insulating film 17 is not deteriorated due to the penetration of the abrasive. In addition, since the cap insulating film 18 is protected by the SOG film 23 during the etching for adjusting the length of the carbon nanotubes 22, damage to the cap insulating film 18 can be prevented.
In the present embodiment, an organic insulating film may be used instead of the SOG film 23 as shown in the second embodiment.

(Fourth embodiment)
8A to 8O are cross-sectional views illustrating manufacturing steps of the semiconductor device according to the fourth embodiment of the present invention. 8A to 8O show the structure from the top to the top of the first interlayer insulating film 10 shown in FIG.

  First, similarly to the first embodiment shown in FIG. 1, after forming the cover film 9 and the first interlayer insulating film 10 on the N-type MOS transistor formed on the silicon substrate 1, the source / source of the N-type MOS transistor is formed. Contact plugs 11 and 12 connected to the drain regions 7 and 8 are formed.

  Further, a first low-k insulating film 11 is formed on the first interlayer insulating film 10 and the contact plugs 11 and 12, and first-layer wirings 13a and 13b are formed therein. Thereafter, a first barrier insulating film 16 and a second Low-k insulating film 17 are formed on the first Low-k insulating film 11 and the first-layer wirings 13a and 13b. Note that the thickness of the second Low-k film 17 is, for example, about 250 nm.

Next, steps required until a structure shown in FIG. 8A is formed will be described.
First, first and second hard mask layers 41 and 42 are sequentially formed on the second low-k insulating film 17. A silicon oxide film is formed as the first hard mask layer 41 to a thickness of about 50 nm by plasma CVD, and a silicon nitride film is formed as the second hard mask layer 42 to a thickness of about 30 nm by plasma CVD. To do.

Subsequently, a first BARC film 40 is formed on the second hard mask layer 42. For example, an organic film is formed as the first BARC film 40. Further, a photoresist is applied on the first BARC film 40, and this is exposed, developed, and the like. Thus, a resist pattern 43 having a hole forming opening 43a is formed above a part of the first layer wiring 15b.
Further, the first BARC film 40 is etched using the resist pattern 43 as a mask, thereby exposing a part of the second hard mask layer 42 from the opening 43a.

Next, steps required until a structure shown in FIG. 8B is formed will be described.
First, using the resist pattern 43 and the first BARC film 40 as a mask, the first and second hard mask layers 41 and 42 are etched by the RIE method using a fluorine-based gas to form openings 42a.

Further, using the resist pattern 43 and the second hard mask layer 41 as a mask, the second low-k insulating film 17 is etched by plasma etching to form a via hole 17c.

As the etching conditions, for example, C ₄ F ₆ as a reactive gas is introduced into the etching chamber at a rate of 15 sccm to 30 sccm, O ₂ is 10 sccm, and Ar is 200 sccm, and the pressure in the etching chamber is set to 30 mTorr to 100 mTorr. Adjust the displacement so that In this case, a high frequency power of about 1000 W is applied to the electrodes of the etching chamber.
Thereafter, the resist pattern 43 and the first BARC film 40 are removed.

Next, a resin film 44, for example, a film of photoresist, polyimide, or the like is formed in the via hole 17c and on the second hard mask layer. The resin film 44 is formed to a thickness that completely fills the via hole 17c.
Thereafter, as shown in FIG. 8C, the resin film 44 is etched back by a plasma etching method using an oxygen-containing gas, for example, and removed from the second hard mask layer 42 and left in the via hole 17c.

  Next, as shown in FIG. 8D, a second BARC film 45 is formed on the resin film 44 and the second hard mask layer 42. Thereafter, a photoresist is applied onto the second BARC film 45, and this is exposed, developed, and the like, thereby forming a resist pattern 46 having a wiring-shaped opening 46a passing over the via hole 17c.

Next, steps required until a structure shown in FIG.
First, the second BARC film 45 is etched using the resist pattern 46 as a mask to form a wiring-shaped opening 45a under the opening 46a. Further, using the resist pattern 46 as a mask, the second hard mask layer 42 is etched by plasma etching, RIE, or the like through the openings 46a and 45a. As a result, a wiring-shaped opening 42 a is formed in the second hard mask layer 42.

Subsequently, as shown in FIG. 8F, the resist pattern 46 and the second BARC film 45 are removed and the resin film 44 in the via hole 17c is removed by a plasma etching method using an oxygen-containing gas, for example.
Further, as shown in FIG. 8G, the first barrier insulating film 16 made of SiCH is etched by the plasma etching method through the via hole 17c and the opening 42a of the second hard mask layer 42, whereby the first layer wiring 15b. To expose.

As the etching conditions, for example, CH ₂ F ₂ is introduced into the etching chamber at a flow rate ratio of about 30 sccm, O ₂ is about 10 sccm, N ₂ is about 50 sccm, and the pressure in the etching chamber is set to about 20 mTorr. To do. In this case, a high frequency power of about 300 W is applied to the electrodes of the etching chamber.
Under the etching conditions, the upper layer portion of the first hard mask layer 41 made of SiO ₂ is also etched.

  Next, as shown in FIG. 8H, a catalytic metal 46 is formed on the first-layer wiring 15b at the bottom of the via hole 17c and on the first and second hard mask layers 41,. The formation method and formation conditions of the catalyst metal fine particles 46 are set to be the same as the formation conditions of the catalyst metal particles 21 of the first embodiment.

Next, as shown in FIG. 8I, the silicon substrate 1 is placed in an etching chamber of a plasma etching apparatus, for example, a capacitively coupled plasma etching apparatus, and the catalytic metal 46 is formed from the upper surfaces of the first and second hard mask layers 41 and 42. Is selectively removed. This leaves the catalyst metal 46 at the bottom of the via hole 17c.

As the etching conditions, for example, CF ₄ is introduced into the etching chamber at a flow rate ratio of about 200 sccm and CO about 100 sccm to 400 sccm, and the pressure in the etching chamber is set to 200 mTorr or more, for example, 200 mTorr to 300 mTorr. In this case, high frequency power of 100 W to 400 W is applied to the electrodes of the etching chamber.

Next, as shown in FIG. 8J, carbon nanotubes 47 are formed by CVD on the first layer wirings 15a and 15b in which the catalyst metal 46 is left in the via hole 17c. For example, the carbon nanotube 47 is formed to have a length equal to the depth of the via hole 17c or a length protruding above the via hole 17c by setting the formation conditions shown in the third embodiment.
Note that the carbon nanotube 47 may be formed to have a length substantially equal to the depth of the via hole 17c, for example, by employing the method shown in FIGS. 7A to 7C of the third embodiment.

  Subsequently, as shown in FIG. 8K, the carbon nanotube 47 is etched by a plasma etching method using an oxygen-based gas, so that the upper end of the carbon nanotube 47 is positioned lower than the upper surface of the second Low-k insulating film 17. . As a result, the carbon nanotube 47 left in the via hole 17c is defined as a via 47a.

As the etching conditions, for example, O ₂ is introduced into the etching chamber at a flow rate ratio of about 200 sccm and CF ₄ is 10 to 50 sccm, and the pressure in the etching chamber is set to 20 to 200 mTorr. In this case, high-frequency power of 100 to 500 W is applied to the electrodes of the etching chamber.

Further, as shown in FIG. 8L, the first hard mask layer 41 is etched through the opening 42 a of the second hard mask layer 42. Thereby, an opening 41a for wiring is formed in the first hard mask layer 41. The silicon oxide film that is the second hard mask layer 41 is etched by a plasma etching method, an RIE method, or the like using, for example, a gas containing CF ₄ .
Here, the second hard mask layer 42 is removed by setting the etching selectivity of the silicon oxide film to the silicon nitride film to be small.

  Next, as shown in FIG. 8M, the second wiring groove 17d is formed by etching the upper portion of the second low-k insulating film 17 through the opening 41a of the first hard mask layer 41 by plasma etching. At the same time, the via hole 17c is made shallower. The depth of the second wiring groove 17d of the first hard mask layer 41 is set such that the bottom surface thereof substantially coincides with the upper end of the via 47a.

As the etching conditions, for example, C ₄ F ₆ as a reactive gas is introduced into the etching chamber at a rate of 15 sccm to 30 sccm, O ₂ is 10 sccm, and Ar is 200 sccm, and the pressure in the etching chamber is set to 30 mTorr to 100 mTorr. Adjust the displacement so that In this case, a high frequency power of about 1000 W is applied to the electrodes of the etching chamber.
According to this condition, the etching selectivity of the second low-k insulating film 17 with respect to the silicon oxide film that is the first hard mask layer 41 is increased.

Next, as shown in FIG. 8N, a barrier metal film 48a such as Ta and a Cu seed film (not shown) connected to the via 47a in the second wiring groove 17d are sequentially formed by sputtering. Thereafter, a copper film 48b is formed thereon by electrolytic plating using the barrier metal film 48a and the copper seed film as electrodes. Thereby, the Cu film 48b is embedded in the second wiring groove 17d.

  Thereafter, as shown in FIG. 8O, the Cu film 48b, the barrier metal film 48a, and the first hard mask layer 41 on the upper surface of the second Low-k insulating film 13 are removed by a CMP method. Thus, the Cu film 48b remaining in the second wiring trench 17d is used as the second-layer wiring 49.

  As described above, as shown in FIG. 9, the second layer wiring 49 is connected to one source / drain region 8 of the MOS transistor through the first layer wiring 15b and the via 47a. Thereafter, a second barrier insulating film 50 of SiCH is formed on the second-layer wiring 49 and the second low-k insulating film 17 to a thickness of, for example, 30 nm by plasma CVD.

After that, by repeatedly forming vias, wirings and the like connected to the second-layer wiring 49, a multilayer wiring is formed. As a method for forming these vias and wirings, the same method as the method for forming the vias 47a and the second-layer wirings 49 is employed.
As described above, according to the embodiment, after forming the via hole 17c in the second Low-k insulating film 17, the carbon nanotubes 47 are selectively formed in the via hole 17c by the same method as in the third embodiment. ing. Thereafter, the carbon nanotube 47 is selectively etched to adjust the length that can be used for the via 47a.

  As a result, CMP for leaving the carbon nanotubes 47 short in the via holes 17a and 17b is unnecessary, and the third Low-k insulating film 17 is not deteriorated due to the entry of the abrasive. In addition, since the second low-k insulating film 17 is protected by the first hard mask layer 41 during the etching for adjusting the length of the carbon nanotube 47, the second low-k insulating film 17 damage can be prevented.

Further, a via 47a of a carbon nanotube 47 shorter than the depth is formed in the via hole 17c of the second Low-k insulating film 17, and the upper portion of the second Low-k insulating film 17 is etched to form a via 47a. A second wiring groove 17d is formed to expose the.
By adopting such a dual damascene, a film forming process between the formation of the second layer wiring 49 after the formation of the via 47a becomes unnecessary, and the wiring formation throughput is improved.

(Fifth embodiment)
FIG. 10A is a sectional view showing a semiconductor device according to the fifth embodiment of the present invention, and shows a structure from the top to the upper side of the first interlayer insulating film 10 shown in FIG.

  10A, contact plugs 11 and 12 connected to source / drain regions 7 and 8 of an N-type MOS transistor are formed in a first interlayer insulating film 10 covering the silicon substrate 1 shown in FIG. Further, in the first low-k insulating film 13 formed on the first interlayer insulating film 10, first-layer wirings 15 a and 15 b partially connected to the contact plugs 11 and 12 are formed. ing.

  On the first Low-k insulating film 13 and the first layer wirings 15a and 15b, the first barrier insulating film 16, the second Low-k insulating film 17, and the first and second hard masks are provided. Layers 52 and 53 are formed. Further, vias 22 a and 22 b made of carbon nanotubes connected to the first-layer wirings 15 a and 15 b are formed in the films 16, 17, 52 and 53.

The first and second hard mask layers 52 and 53 protect the second low-k insulating film 17 from plasma when the carbon nanotubes are etched, like the cap layer 18 shown in the first embodiment. It has a function.

  A third Low-k insulating film 25 is formed on the vias 22 a and 22 b and the second hard mask layer 53. In the third Low-k insulating film 25, second-layer wirings 30a, 30b, 30c, 30d, and 30e are formed. Part of the second layer wirings 30a and 30b are connected to the vias 22a and 22b below the second layer wirings 30a and 30b, and the source / drain regions 7 and 8 of the N-type MOS transistor via the first layer wirings 15a and 15b. Is electrically connected.

  Among the plurality of films from the first interlayer insulating film 10 to the third Low-k insulating film 25, the outer peripheral region of the semiconductor device forming region 60 as shown in FIG. 10B surrounds the first to third semiconductor circuits. The moisture-resistant rings 50, 51 and 55 are formed. A second barrier insulating film 31 is formed on the third Low-k insulating film 25, the second-layer wirings 30a, 30b, 30c, 30d, 30e and the third moisture-resistant ring 55. Yes.

  Next, a method for forming the moisture-resistant rings 50, 51, and 55 will be described with reference to FIGS. 11A to 11N. 11A to 11N show the upper side from the upper part of the first interlayer insulating film 10, the left figure shows the transistor formation area A in the semiconductor device formation area, and the right figure shows the outer peripheral area of the semiconductor device formation area. B is shown.

The steps required until the structure shown in FIG. 11A is formed will be described.
First, the first ring-shaped groove 10c is formed in the outer peripheral region B of the semiconductor device formation region 60 in the first interlayer insulating film 10, and the Ti film, TiN film, and W film are sequentially embedded in the groove 10c. One moisture-resistant ring 50 is formed. The first moisture-resistant ring 50 is formed in the same process as the formation of the contact plugs 11 and 12 shown in the above embodiment.

  Subsequently, after the first low-k insulating film 11 is formed on the first moisture-resistant ring 50 and the first interlayer insulating film 10, the first low-k insulating film 11 is patterned to thereby form the outer peripheral region B. A second ring-shaped groove 13 c is formed on the first moisture-resistant ring 50. Furthermore, a second moisture-resistant ring 51 is formed by embedding the barrier metal film 14 a and the Cu film 14 b in the second ring-shaped groove 13 c and is connected to the first moisture-resistant ring 50. The second moisture-resistant ring 51 is formed in the same process as the first-layer wirings 15a and 15b in the transistor formation region A shown in the other embodiments.

  Further, as in the first embodiment, the first barrier insulating film 16, the second wiring 15 a, 15 b, the second moisture-resistant ring 51, and the first Low-k insulating film 11 are formed on the first barrier insulating film 16 and the second barrier insulating film 16. The low-k insulating film 17 is formed. For example, a SiCH film is formed as the first barrier insulating film 16 to a thickness of about 30 nm by plasma CVD, and a SiOC film is formed as the second Low-k insulating film 17 to a thickness of about 150 nm by plasma CVD. .

Further, first and second hard mask layers 52 and 53 are formed on the second Low-k insulating film 17. As the first hard mask layer 52, a SiCH film is formed to a thickness of about 10 nm by, for example, a plasma CVD method. Further, as the second hard mask layer 53, for example, a SiO ₂ film is formed to a thickness of about 30 nm by plasma CVD.

  Thereafter, the first BARC film 19 is formed on the second hard mask layer 53 in the same manner as shown in the first embodiment. Further, a photoresist is applied on the first BARC film 19, and this is exposed and developed.

Thus, similarly to the first embodiment, a resist pattern 20 having openings 20a and 20b with a diameter of about 50 nm for forming via holes is formed above the first-layer wirings 15a and 15b. At the same time, a ring-shaped opening 20 c is formed above the second moisture-resistant ring 51 in the outer peripheral region B of the resist pattern 20. Here, the width of the ring-shaped opening 20c is wider than the openings 20a and 20b for forming the via holes, and is formed, for example, at least five times the diameter thereof.

Subsequently, the first BARC film 19 is etched through the openings 20a, 20b, and 20c of the resist pattern 20.
Next, the silicon substrate 1 is put into a plasma etching apparatus, and as shown in FIG. 11B, through the openings 20a and 20b of the resist pattern 20 through the second hard mask layer 52 in the transistor formation region A to the first barrier insulating film 16. And via holes 17a and 17b are formed above the first layer wirings 15a and 15b. At the same time, a part of the first and second hard mask layers 52 and 53 in the outer peripheral region B is etched through the ring-shaped opening 20 c of the resist pattern 20 to form a recess 54. Note that an opening is formed in the second hard mask layer 53 through the recess 54.

In this way, the etching conditions are set as follows in order to make the etching depths different in the films under the via hole forming openings 20a and 20b and under the ring-shaped opening 20c.
This etching is performed under conditions that increase the deposition of the fluorocarbon polymer on the film. In this case, the fluorocarbon polymer is difficult to deposit under the openings 20a and 20b for forming via holes with small dimensions, and the etching rate thereunder is increased. At the same time, under the condition that the fluorocarbon polymer is easily deposited under the ring-shaped opening 20c having a large size, the etching under the condition is inhibited to lower the etching rate.

As the etching conditions, for example, when fluorocarbon, oxygen (O ₂ ), and an inert gas are introduced into the etching chamber and the flow ratio of fluorocarbon, for example, C ₄ F ₆ with respect to O ₂ is increased, the wide ring-shaped opening 20c is formed. The amount of fluorocarbon polymer deposited increases. Thereby, under the ring-shaped opening 20c, the etching rate is significantly reduced, or the etching can be substantially stopped. On the other hand, since the fluorocarbon polymer is difficult to deposit in the narrow openings 20a and 20b for forming the via hole, the etching rate can be increased. Incidentally, hydrofluorocarbon instead of fluorocarbon, for example, the _CH 2 _{F 2} may be used.

For example, the etching conditions for the SiO ₂ film that is the second hard mask layer 53 include C ₄ F ₆ at a flow rate of 20 sccm to 40 sccm, O ₂ at a flow rate of approximately 10 sccm, and Ar at a flow rate of approximately 200 sccm, or at such a flow rate ratio. A gas is introduced into the etching chamber. Further, the pressure in the etching chamber is set to about 30 mTorr to 100 mTorr, and the power applied to the electrodes of the etching chamber is set to about 1000 W. In this case, the flow rate of C ₄ F ₆ with respect to O ₂ is 2 to 4 times. Instead of C ₄ F ₆ , other fluorocarbon C ₄ F ₈ may be used.

Further, as etching conditions for the SiCH film constituting the first hard mask layer 52 and the first barrier film 16, for example, CH ₂ F ₂ is about 30 sccm, O ₂ is about 10 sccm, and N ₂ is about 50 sccm. Alternatively, it is introduced into the etching chamber at such a flow rate ratio. Further, the pressure in the etching chamber is set to about 20 mTorr, and the power applied to the electrodes of the etching chamber is about 300 W. In this case, the flow rate of CH ₂ F ₂ with respect to O ₂ is about three times.

Further, the etching conditions of the SiOC film that is the second Low-k insulating film 17 include, for example, a flow rate of 15 sccm to 30 sccm for C ₄ F ₆ , about 10 sccm for O ₂ , and about 200 sccm for Ar, or such a flow rate. Those gases are introduced into the etching chamber in proportions. Further, the pressure in the etching chamber is set to about 30 mTorr, and the power applied to the electrodes of the etching chamber is about 1000 W. In this case, the flow rate of C ₄ F ₆ with respect to O ₂ is 1.5 to 3 times.

According to the etching conditions as described above, the etch rate of the second hard mask layer 53 under the wide ring-shaped opening 20c and the films 52 and 17 thereunder is provided above the second moisture-resistant ring 51. A shallow and shallow recess 54 is formed. The flow rate of fluorocarbon and hydrofluorocarbon relative to O ₂ is 1.5 to 4 times.

Thereafter, the silicon substrate 1 is taken out from the plasma etching apparatus.
Next, with the resist pattern 20 and the first BARC film 19 removed, as shown in FIG. 11C, the first layer wiring 15a on the second hard mask layer 53 and in the via holes 17a and 17b. , 15b, catalyst metal fine particles 21 are formed respectively. The formation conditions of the catalyst metal particles 21 are set to be the same as those shown in the first embodiment, for example.

Next, as shown in FIG. 11D, carbon nanotubes 22 are formed on the surface on which the catalytic metal fine particles 21 are formed. The formation conditions of the carbon nanotubes 22 are set to be the same as those in the first embodiment, for example, and have a length that protrudes over the via holes 17a and 17b.
Further, as shown in FIG. 11E, an SOG film 23 is formed on the carbon nanotube 22. The formation conditions of the SOG film 23 are set to be the same as those in the first embodiment, for example, and the upper surface thereof is planarized.

  Thereafter, the silicon substrate 1 is put into a plasma etching apparatus. Then, as shown in FIG. 11F, the SOG film 23 is etched by plasma etching using the same fluorocarbon-based gas as shown in the first embodiment, thereby exposing the upper end of the carbon nanotubes 22.

In this state, a large number of carbon nanotubes 22 have deep recesses on the via holes 17a and 17b, so that the SOG film 23 remains thick in the recesses.
Next, the carbon nanotubes 22 are etched by switching the etching gas to an oxygen-based gas as in the first embodiment. Thereby, as shown in FIG. 11G, the side portion of the SOG film 23 is exposed.

  Further, the carbon nanotubes 22 are etched by switching the etching gas to an oxygen-based gas similar to that shown in the first embodiment. As a result, the upper end positions of the carbon nanotubes 22 formed in the via holes 17a and 17b are aligned with the upper end positions of the carbon nanotubes 22 in other regions. If the upper ends of the carbon nanotubes 22 are already aligned, the etching is omitted.

Furthermore, the etching gas is switched to a fluorocarbon-based gas to etch the SOG film 23, thereby exposing the upper ends of the carbon nanotubes 22 on the via holes 17a and 17b as shown in FIG. 11H.
Instead of the SOG film 23, an organic insulating film may be used as shown in the second embodiment.

Next, the etching gas is switched to the oxygen-based gas shown in the first embodiment, and the layer of the carbon nanotubes 22 whose upper end positions are aligned is etched, so that the second hard mask layer 53 is formed as shown in FIG. 11I. Expose the top surface. When the carbon nanotubes 22 are etched, the etching time is set so that the carbon nanotubes 22 formed on the bottom surface of the recess 54 above the second moisture-resistant ring 51 can be removed.

Thus, the carbon nanotubes 22 left in the via holes 17a and 17b after the etching are used as the vias 22a and 22b.
In order to embed the carbon nanotubes 22 in the via holes 17a and 17b, the methods shown in the second and third embodiments may be employed.
Subsequently, the catalyst metal particles 21 left on the bottom surfaces of the second hard mask layer 53 and the recesses 54 are removed. As the removal method, for example, the method shown in the first embodiment is adopted.

Next, as shown in FIG. 11J, on the second hard mask layer 53 and the vias 22a and 22b and on the bottom surface of the recess 54, the third Low-k insulating film 25 and the third hard mask layer 26 are formed. Are formed in order. An SiOC film is formed as the third Low-k insulating film 25 to a thickness of 150 nm by the CVD method. Further, a SiO ₂ film is formed as the third hard mask layer 26 to a thickness of 30 nm by the CVD method.

  Subsequently, as shown in FIG. 11K, a second BARC film 27 and a resist pattern 28 are formed on the third hard mask layer 26. Similar to the first embodiment, the resist pattern 28 has openings 28 a and 28 b for forming a wiring, and has an opening 28 c for forming a moisture-resistant ring above the second moisture-resistant ring 51. The planar shape of the opening 28c for forming the moisture-resistant ring preferably has a width that is the same as or wider than the recess 54 of the first and second hard mask layers 52 and 53.

Thereafter, the second BARC film 27 is etched using the resist pattern 28 as a mask, thereby exposing the third hard mask layer 26 from the openings 28a, 28b, 28c.
Further, the third hard mask layer 26 and the third low-k insulating film 25 are etched through the openings 28a, 28b, and 28c. Thus, as shown in FIG. 11L, the second wiring grooves 25 a and 25 b are formed, and the moisture-resistant ring groove 25 c is formed above the second moisture-resistant ring 51. FIG. 11L shows a state where the resist pattern 28 and the second BARC film 27 are removed.

Etching of the SiO ₂ film, which is the third hard mask layer 26, and the SiOC film, which is the third low-k insulating film 25, is performed by plasma etching using a gas containing C ₄ F ₆ , O ₂ , Ar, and RIE. This is done by dry etching such as the method. When the third Low-k film 25 is etched, the flow rate ratio of CF _{4 to} O ₂ is adjusted so that the etching rate of the SiO ₂ film is lowered.

Next, as shown in FIG. 11M, the first hard mask layer 52 and the second low− in the peripheral region B are masked using the SiO ₂ films constituting the second and third hard mask layers 26 and 53 as masks. The k insulating film 17 is etched to deepen the moisture-proof ring groove 25c.

Etching of the SiCH film that is the first hard mask layer 52 is performed by dry etching such as plasma etching or RIE using a gas containing CH ₂ F ₂ , O ₂ , and N ₂ . In this case, both by adjusting the flow ratio of _CH 2 _{F 2} with respect to _{O 2} to increase the etching rate, with the proviso that does not substantially etch the carbon nanotube 22 is a via 22a, 22b.

Etching of the second low-k insulating film 17 is performed by a plasma etching method, an RIE method, or the like using a gas containing C ₄ F ₆ , O ₂ , and Ar. In this case, both by adjusting the flow rate ratio of C ₄ F ₆ for O ₂ to increase the etching rate, with the proviso that does not substantially etch the carbon nanotube 22 is a via 22a, 22b.
Next, the first barrier insulating film 16 is etched using the second and third hard mask layers 26 and 53 as a mask, thereby deepening the moisture-resistant ring groove 25c and exposing the second moisture-resistant ring 51. .

Etching of the SiCH film as the first barrier insulating film 16 is performed by dry etching such as plasma etching or RIE using a gas containing CH ₂ F ₂ , O ₂ , and N ₂ . In this case, both by adjusting the flow ratio of _CH 2 _{F 2} with respect to _{O 2} to increase the etching rate, with the proviso that does not substantially etch the carbon nanotube 22 is a via 22a, 22b.
As a result, the moisture-resistant ring groove 25 c penetrates the second Low-k insulating film 17 and the first barrier insulating film 16 and reaches the second moisture-resistant ring 51.

  Next, as in the first embodiment, a barrier metal film 29a is formed on the inner surfaces of the second wiring grooves 25a and 25b and the moisture-resistant ring groove 26c, and a Cu film 29b is embedded therein. Subsequently, the Cu film 29b, the barrier metal film 29a, and the third hard mask layer 26 on the third Low-k insulating film 25 are removed by a CMP method.

  As a result, as shown in FIG. 11N, the Cu film 29b and the barrier metal film 29a remaining in the second wiring grooves 25a and 25b become the second layer wirings 30a, 30b, 30c, and 30d shown in FIG. 30e. Further, the Cu film 29 b and the barrier metal film 29 a remaining in the moisture-resistant ring groove 26 c become the third moisture-resistant ring 55 shown in FIG. 10 and are connected to the upper surface of the second moisture-resistant ring 51.

  Next, as shown in FIG. 10, the second barrier insulating film 31 is formed on the second layer wirings 30 a to 30 e and the third moisture-resistant ring 55. For example, a SiCH film is formed as the second barrier insulating film 31. Further, by laminating vias, wirings, and moisture resistant rings by the same method as described above, multilayer structured wiring and multilayer structured moisture resistant rings are formed.

  As described above, according to the present embodiment, the first layer wirings 15a and 15b and the second moisture-resistant ring 51 are formed in the first Low-k insulating film 13, and the third Low-k insulating film is formed. In the film 25, second-layer wirings 30a and 30b and a third moisture-resistant ring 55 are formed.

  The first-layer wirings 15 a and 15 b and the second-layer wirings 30 a and 30 b are connected to each other via vias 22 a and 22 b in the second Low-k insulating film 17. The third moisture-resistant ring 55 passes through the moisture-resistant ring groove 25c in the second Low-k insulating film 17 without passing through the carbon nanotubes 22 constituting the vias 22a and 22b. It is connected to the.

  10A and 10B, even if the semiconductor device is exposed to an external moisture-containing atmosphere, the first, second, and third moisture-resistant rings 50, 51, and 55 block moisture. In addition, it is possible to prevent damage due to water intrusion into the first, second, and third Low-k insulating films 11, 17, and 25 in the semiconductor formation region 60.

  On the other hand, when the second moisture-resistant ring 51 and the third moisture-resistant ring 55 are connected via the carbon nanotube, moisture enters the second Low-k insulating film 17 through a slight gap between the carbon nanotubes. There is a possibility of damaging the -k insulating film 17.

All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, such examples and It should be construed without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. Although embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the present invention.

Next, features of the embodiment will be described.
(Supplementary Note 1) A step of forming a first wiring above a semiconductor substrate, a step of forming a first insulating film above the first wiring, and patterning the first insulating film to reach the first wiring A step of forming a hole, a step of forming a carbon nanotube layer in the hole and on the top surface of the first insulating film, a step of forming a second insulating film on the carbon nanotube layer, and the second insulating film. Etching to expose the carbon nanotube layer and leaving the second insulating film in the recess of the carbon nanotube layer; and etching the carbon nanotube layer to align the top end of the carbon nanotube layer; Etching the second insulating film on the carbon nanotube layer; etching the carbon nanotube layer; And removing from the upper surface of the first insulating film and leaving it in the hole.
(Additional remark 2) The said 2nd insulating film is a coating type insulating film, The manufacturing method of the semiconductor device of Additional remark 1 characterized by the above-mentioned.
(Additional remark 3) The manufacturing method of the semiconductor device of Additional remark 2 characterized by etching the said coating type insulation film with the 1st gas containing fluorocarbon, and etching the said carbon nanotube with the 2nd gas containing oxygen.
(Supplementary note 4) The method of manufacturing a semiconductor device according to supplementary note 2, wherein the first gas and the second gas contain the fluorocarbon and the oxygen at different flow ratios.
(Supplementary Note 5) wherein the second etching atmosphere introducing gas, Appendix 3 or Appendix 4, characterized in that introducing CF ₄ at 5 flow rate% 20 flow rate% of the total flow rate of the fluorocarbon and the oxygen The manufacturing method of the semiconductor device as described in any one of.
(Supplementary Note 6) The on the first insulating film is SiCH, SiOC, forming a cap film made of any of SiO _2, Appendix 1 to characterized by having a step of forming the hole in the cap layer The method for manufacturing a semiconductor device according to any one of appendix 5.
(Appendix 7) A step of forming a first wiring above the semiconductor substrate, a step of forming a first insulating film above the first wiring, and etching the first insulating film to reach the first wiring A step of forming a hole; a step of forming a carbon nanotube in at least the hole; a step of forming a second insulating film covering the carbon nanotube above the first insulating film; and a gas containing oxygen. Etching the second insulating film and the carbon nanotube, exposing a top surface of the first insulating film, and leaving the carbon nanotube in the hole.
(Additional remark 8) The said 2nd insulating film is a coating-type resin film, The manufacturing method of the semiconductor device of Additional remark 7 characterized by the above-mentioned.
(Additional remark 9) The said carbon nanotube is formed also on the said 1st insulating film, The manufacturing method of the semiconductor device of Additional remark 7 or Additional remark 8 characterized by the above-mentioned.
(Supplementary note 10) The semiconductor device manufacturing method according to any one of supplementary notes 7 to 9, wherein the gas is added with fluorocarbon after the carbon nanotubes are exposed.
(Additional remark 11) The process of forming a 3rd insulating film on the said 1st insulating film and the said hole, The process of forming the groove | channel for wiring in the area | region including above the said hole among 3rd insulating films, The said hole A method for manufacturing a semiconductor device according to any one of appendix 1 to appendix 10, further comprising: forming a second interconnect connected to the carbon nanotube in the interconnect trench.
(Supplementary Note 12) A step of forming a first wiring above the semiconductor substrate, a step of forming a first insulating film above the first wiring, and etching the first insulating film to reach the first wiring A step of forming a hole; a step of forming a catalytic metal in the hole and on the upper surface of the first insulating film; and a gas containing fluorocarbon in an atmosphere at a pressure of 200 mTorr to 300 mTorr. A method for manufacturing a semiconductor device, comprising: a step of selectively etching the catalytic metal; and a step of selectively forming carbon nanotubes in the hole.
(Additional remark 13) The said catalyst metal has cobalt or nickel, The manufacturing method of the semiconductor device of Additional remark 12 characterized by the above-mentioned.
(Additional remark 14) The manufacturing method of the semiconductor device of Additional remark 12 or Additional remark 13 characterized by the above-mentioned gas containing carbon monoxide.
(Additional remark 15) The process of shortening the said carbon nanotube in the said hole by an etching, the process of etching the upper part of a said 1st insulating film, and forming the groove | channel for wiring in the area | region including above the said hole, The said carbon nanotube The method for manufacturing a semiconductor device according to any one of appendices 12 to 14, further comprising: forming a second interconnect connected to the interconnect trench in the interconnect trench.
(Supplementary Note 16) A step of forming a first wiring above the semiconductor substrate, a step of forming a first insulating film, a first hard mask layer, and a second hard mask layer above the first wiring, and the second A first opening having a first width is formed in a first region of the hard mask layer, and a second opening having a second width larger than the first width is formed in a second region. Etching the first hard mask layer, exposing the first insulating film from the first opening, and not exposing the first insulating film from the second opening, and etching the first hard film. Forming a hole exposing the first wiring under the first opening, forming a recess under the second opening, embedding carbon nanotubes in the hole, and the first hard mask layer , The second hard mask layer, the first insulating film and And forming a second insulating film on the carbon nanotube and etching to form a first groove in a wiring region including the carbon nanotube in the second insulating film, and in the second region, 1. A method for manufacturing a semiconductor device, comprising: forming a second groove penetrating an insulating film; and embedding a conductive material in the first groove and the second groove.
(Supplementary note 17) The method of manufacturing a semiconductor device according to supplementary note 16, wherein the first hard mask layer is a SiCH layer, and the second hard mask layer is a silicon oxide layer.
(Additional remark 18) The upper layer part of the said 2nd insulating film consists of the same material as a 2nd hard mask layer, The manufacturing method of the semiconductor device of Additional remark 17 characterized by the above-mentioned.
(Additional remark 19) The gas used for the etching of the first hard mask layer includes either hydrofluorocarbon or fluorocarbon gas and oxygen gas. 19. The method of manufacturing a semiconductor device according to any one of appendix 16 to appendix 18, wherein the method is 1.5 to 4 times. (Supplementary note 20) The method of manufacturing a semiconductor device according to any one of supplementary notes 16 to 19, wherein the conductive material includes copper.
(Supplementary note 21) The supplementary notes 16 to 20, wherein a second wiring is formed by the conductive material embedded in the first groove, and a moisture-resistant ring is formed by the conductive material embedded in the second groove. The manufacturing method of the semiconductor device as described in any one.
(Additional remark 22) The said carbon nanotube is formed by CVD method, The manufacturing method of the semiconductor device as described in any one of additional remark 1 thru | or appendix 21 characterized by the above-mentioned.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 7, 8 Source / drain area | region 11, 12 Contact plug 10 Interlayer insulating film 13, 17, 25 Low-k insulating film 15a, 15b 1st layer wiring 16 Barrier insulating film 18 Cap insulating film 19 1st BARC film 20 Resist pattern 21 Catalytic metal fine particles 22 Carbon nanotubes 22a and 22b Via 23 SOG film 26 Hard mask layer 27 Second BARC film 28 Resist patterns 30a to 30e Second-layer wiring 31 Barrier insulating film 32 Photoresist layer ( Resin layer)
41, 42 Hard mask layer 43 Resist pattern 44 Resin film 45 BARC film 46 Catalytic metal particle 47 Carbon nanotube 49 Second layer wiring 50, 51, 55 Moisture resistant ring

Claims (7)

Forming a first wiring above the semiconductor substrate;
Forming a first insulating film above the first wiring;
Patterning the first insulating film to form a hole reaching the first wiring;
Forming a carbon nanotube layer in the hole and on the upper surface of the first insulating film;
Forming a second insulating film on the carbon nanotube layer;
Exposing the carbon nanotube layer by etching the second insulating film, and leaving the second insulating film in a recess of the carbon nanotube layer;
Etching the carbon nanotube layer and aligning the position of the upper end of the carbon nanotube layer;
Etching the second insulating film on the carbon nanotube layer;
Etching the carbon nanotube layer and removing it from the top surface of the first insulating film and leaving it in the hole;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film is a coating type insulating film. Etching the coating insulating film with a first gas containing fluorocarbon,
The method of manufacturing a semiconductor device according to claim 2, wherein the carbon nanotube is etched with a second gas containing oxygen. Forming a first wiring above the semiconductor substrate;
Forming a first insulating film above the first wiring;
Etching the first insulating film to form a hole reaching the first wiring;
Forming a carbon nanotube in at least the hole;
Forming a second insulating film covering the carbon nanotubes above the first insulating film;
Etching the second insulating film and the carbon nanotube using a gas containing oxygen, exposing an upper surface of the first insulating film and leaving the carbon nanotube in the hole;
A method for manufacturing a semiconductor device, comprising:   5. The method of manufacturing a semiconductor device according to claim 4, wherein the second insulating film is a coating resin film. Forming a first wiring above the semiconductor substrate;
Forming a first insulating film above the first wiring;
Etching the first insulating film to form a hole reaching the first wiring;
Forming a catalyst metal in the hole and on the upper surface of the first insulating film;
Selectively etching the catalyst metal on the first insulating film in an atmosphere having a pressure of 200 mTorr to 300 mTorr using a gas containing fluorocarbon;
Selectively forming carbon nanotubes in the holes;
A method for manufacturing a semiconductor device comprising: Forming a first wiring above the semiconductor substrate;
Forming a first insulating film, a first hard mask layer, and a second hard mask layer above the first wiring;
Forming a first opening having a first width in a first region of the second hard mask layer;
Forming a second opening having a second width larger than the first width in the second region;
Etching the first hard mask layer, exposing the first insulating film from the first opening, and not exposing the first insulating film from the second opening;
Forming a hole exposing the first wiring under the first opening by etching and forming a recess under the second opening;
Embedding carbon nanotubes in the holes;
Forming a second insulating film on the first hard mask layer, the second hard mask layer, the first insulating film, and the carbon nanotube;
Forming a first groove in the wiring region including the carbon nanotubes in the second insulating film by etching, and forming a second groove penetrating the first insulating film in the second region;
Embedding a conductive material in the first groove and the second groove;
A method for manufacturing a semiconductor device, comprising:

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