JP2006049459A - Manufacturing method of carbon nanotube transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve manufacturing yield of a carbon nanotube transistor, with respect to a manufacturing method thereof. <P>SOLUTION: Carbon nanotubes 9 deposited on regions other than a source part 5, a drain 6 and a region between the source part 5 and the drain part 6 are removed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method of manufacturing a carbon nanotube transistor, and more particularly to a method of manufacturing a carbon nanotube transistor characterized by a process for improving the manufacturing yield of the carbon nanotube transistor.

  In recent years, research has been conducted on application to various electronic devices using the excellent electrical characteristics of carbon nanotubes. In particular, single-walled carbon nanotubes have a quantum effect due to their nanometer diameter. Because it appears, it is especially promising.

  Conventionally, the application to an electronic device has been mainly applied as an electrode material, but recently, an attempt has been made to construct a field effect transistor using a semiconductor characteristic having a carbon nanotube ( For example, see Non-Patent Document 1 or Non-Patent Document 2.)

  Such a carbon nanotube transistor CNT has been confirmed to have characteristics comparable to or higher than those of a single-crystal SiMOSFET. In particular, in p-channel CNT, very good carrier mobility and complementary conductance have been reported. Yes.

  However, since it is difficult to grow carbon nanotubes in a desired position, various methods have been proposed to make carbon nanotubes a practical device. For example, a self-assembled film is used (for example, Patent Document 1) or a method using a catalyst (for example, refer to Patent Document 2) has been proposed.

See FIG. 12 and FIG.
FIG. 12 is a conceptual perspective view of a conventional CNT, and FIG. 13 is a schematic cross-sectional view thereof.
For example, a pair of source / drain electrodes 43, 44 made of Mo is provided on a silicon substrate 41 via an SiO ₂ film 42, and an Fe-based catalyst 45 is formed on the surface of the source / drain electrodes 43, 44 by, for example, dipping. Then, carbon nanotubes 46 serving as channel regions are grown between the source / drain electrodes 43 and 44 from the catalyst 45 by a CVD method using methane or acetylene as a source gas.
Next, a gate insulating film 47 and a gate electrode 48 are formed on the carbon nanotube 46 by using a lift-off method, thereby completing the basic structure of the CNT.
http: // pcweb. mycom. co. jp / news / 2002/12/11/22. html http: // www. nec. co. jp / wcs / show / leaf / CID / onair / biztech / prom / 186232 JP 2003-017508 A JP 2004-067413 A

However, in reality, there is a problem that the growth of carbon nanotubes cannot be well controlled, and this situation will be described with reference to FIG.
See FIG.
FIG. 14 is a conceptual plan view when a plurality of CNTs are formed. Here, in order to form six CNTs, six pairs of source / drain electrodes are formed on a silicon substrate 41 via a SiO ₂ film. The case where 43 and 44 are provided is shown.

  In this state, when the carbon nanotube 46 is grown by the CVD method using methane or acetylene as a source gas, not only between the source / drain electrodes 43 and 44 constituting one CNT but also adjacent sources. There is a problem that the carbon nanotube 46 grows between the drain electrodes 43 and 44, and the function of each CNT is destroyed. Therefore, there is a problem that the production yield of CNT is very low.

  In addition, since the grown carbon nanotubes 46 are not necessarily carbon nanotubes (scnt) having semiconductor characteristics, but also carbon nanotubes (mcnt) having metal characteristics are mixed and grown, each CNT is surely operated as a transistor. However, there is a problem that the manufacturing yield is very low.

  Accordingly, an object of the present invention is to improve the manufacturing yield of carbon nanotube transistors (CNT).

FIG. 1 is a diagram illustrating the basic configuration of the present invention. Means for solving the problems in the present invention will be described with reference to FIG.
In order to solve the above-described problem, the present invention provides a method of manufacturing a carbon nanotube transistor on a source portion 5, a drain portion 6, and a region other than a region between the source portion 5 and the drain portion 6. The deposited carbon nanotubes 9 are removed.

Thus, the carbon nanotubes 9 deposited on the source portion 5, the drain portion 6, and the region other than the region between the source portion 5 and the drain portion 6, that is, the source portion 5 or the drain constituting another transistor. By removing the carbon nanotubes 9 connected to the part 6, each transistor can be operated reliably, so that the manufacturing yield can be improved.
The carbon nanotubes 9 in the present invention include not only carbon nanotubes with 100% C but also carbon nanotubes in which other elements are ion-implanted with H or the like.

  When such a process is actually performed, after providing the gate electrode 3 on the substrate 1 via the first insulating film 2, the second insulating film 4 is provided on the gate electrode 3, and then the first After providing the source / drain portions 5 and 6 on the second insulating film 4, the third insulating film 7 is provided, and then at least a part of the source / drain portions 5 and 6 of the third insulating film 7 and the source portion. After opening 8 is formed so that the region between 5 and drain portion 6 is exposed, carbon nanotube 9 is deposited on the entire surface, and then carbon nanotube 9 deposited in a region other than opening 8 is removed. It is desirable to make it.

  In this case, the substrate 1 may be any of a conductive substrate, a semiconductor substrate, and an insulating substrate, but a semiconductor substrate such as a silicon substrate is desirable from the viewpoint of ease of manufacturing, and also when the substrate is used as a gate electrode. A semiconductor substrate such as a silicon substrate is desirable.

In this case, the gate electrode 3 and the source / drain portions 5 and 6 are deposited with carbon nanotubes 9 such as Mo, Au, Pt, Ir, WN _x , RuO _x , IrO _x , CoSi ₂ , NiSi, or polycrystalline Si. A conductive material that can withstand a temperature of 700 to 900 ° C. and that can be easily formed or patterned is desirable.

The second insulating film 4 includes a gate insulating film made of any of SiO ₂ , Si ₃ N ₄ , SiON, Ta ₂ O ₅ , ZrO _x , HfO, or HfSiO, and a gate insulating film. And an etching stopper film having selective etching properties with respect to the gate insulating film, so that the second insulating film 4 can be excessively etched when the opening 8 is formed. Absent.

  In this case, it is desirable to remove the exposed portion of the etching stopper film in the opening 8 before the carbon nanotube 9 deposition step, so that the gate insulating film has a desired film thickness and a desired dielectric constant. It can be composed of a dielectric film.

  Further, it is desirable to attach a catalyst when depositing the carbon nanotubes 9 on at least a part of the source / drain portions 5 and 6 before the carbon nanotube 9 deposition step, thereby making the carbon nanotubes 9 highly reproducible. The source / drain portions 5 and 6 can be deposited while being aligned in a direction from one to the other.

  Further, when removing the carbon nanotubes 9 deposited in the region other than the opening 8, the opening 8 is filled with the buried film 10 made of either an inorganic insulating material or a resist, and then the buried film 10 is replaced with the third film. It is desirable to remove and planarize the insulating film 7 using a chemical mechanical polishing method, a reactive ion etching method, a wet etching method, or the like, and the removal process can be performed without a mask.

  Further, it is desirable that the distance between the source portion 5 and the drain portion 6 is 0.5 μm or more, and the length of the source / drain portions 5 and 6 is 100 μm or less. Can be obtained as a carbon nanotube 9 having semiconductor characteristics with high reproducibility.

  According to the present invention, carbon nanotubes to be grown can be made into carbon nanotubes having semiconductor characteristics, and carbon nanotubes grown at undesired positions can be removed to ensure transistor operation. The manufacturing yield of the transistor can be greatly improved.

  In the present invention, a gate electrode is provided on a substrate such as a semiconductor substrate via a first insulating film, and then a second insulating film including a gate insulating film and an etching stopper film is provided on the gate electrode, After providing the source / drain electrodes on the second insulating film, an interlayer insulating film is provided on the entire surface, and then an opening corresponding to the channel region forming region is formed in the interlayer insulating film, and then carbon nanotubes are deposited on the entire surface. Next, an embedded film made of an inorganic insulator or resist is deposited on the entire surface to fill the opening, and then planarized using a chemical mechanical polishing method, a reactive ion etching method, a wet etching method, or the like. By processing, the carbon nanotube deposited in the region other than the opening is removed.

Here, with reference to FIG. 2, the manufacturing process of the carbon nanotube transistor of Example 1 of this invention is demonstrated.
See Figure 2
First, a SiO ₂ film 12 having a thickness of, for example, 300 nm is formed on the silicon substrate 11 functioning as a gate, and then, using a lift-off method, the thickness is made of, for example, 50 nm of Mo. A pair of the source electrode 13 and the drain electrode 14 having a distance L between them is formed.
In addition, the extraction electrode 15 and the pad part 16 are formed simultaneously with the source electrode 13 and the drain electrode 14.

  Next, an Fe-based catalyst (not shown) is formed on at least the surfaces of the source electrode 13 and the drain electrode 14 by dipping, and then the carbon nanotubes 17 and 18 are formed on the entire surface by CVD using methane as a carbon supply source. Grow.

  Next, the exposed unnecessary carbon nanotubes 18 are removed by etching using a resist pattern (not shown) covering the source electrode 13, the drain electrode 14, and the region between them, thereby removing the main carbon nanotube 18. The basic structure of the carbon nanotube transistor (CNT) of Example 1 of the invention is completed.

  3 and FIG. 4 are IV characteristic diagrams of CNT. FIG. 3 shows the IV characteristics when −10 V is applied to the silicon substrate 11 serving as a gate electrode. FIG. The IV characteristics when 10 + V is applied to the silicon substrate 11 are shown.

3 and 4 that the drain current I _d can be controlled by the gate voltage, that is, the carbon nanotube 17 connecting the source electrode 13 and the drain electrode 14 has semiconductor characteristics.

See Figure 5
FIG. 5 is also an IV characteristic diagram of CNTE. When −10 V is applied to the silicon substrate 11 serving as the gate electrode and when +10 V is applied, the source electrode 13 and the drain electrode 14 are not changed. It can be seen that the connected carbon nanotubes 17 have metal characteristics and do not exhibit transistor characteristics.

表１は、成長したカーボンナノチューブを導電特性のソース・ドレイン間隔Ｌ及びソース・ドレイン長Ｗ依存性を示したものであり、ここでは、各ソース・ドレイン間隔Ｌに対して同じソース・ドレイン長Ｗの２つのＣＮＴを作成して図３乃至図５に示したＩ−Ｖ特性のゲート電圧依存性から導電特性を調べたものである。
表から明らかなように、ソース・ドレイン間隔Ｌが長くなるほど、また、ソース・ドレイン長Ｗが短くなるほど半導体特性を示すことが分かる。

Table 1 shows the dependence of the grown carbon nanotubes on the source / drain distance L and the source / drain length W of the conductive characteristics. Here, the same source / drain length W is used for each source / drain distance L. These two CNTs were prepared, and the conductive characteristics were examined from the gate voltage dependence of the IV characteristics shown in FIGS.
As is apparent from the table, the longer the source / drain distance L is, and the shorter the source / drain length W is, the more semiconductor characteristics are shown.

See FIG.
FIG. 6 is a graph of the results in Table 1. Here, two CNTs having the same L and D are plotted with a slight shift.
From FIG. 6, in order to realize the CNT transistor operation with good reproducibility by using the grown carbon nanotube as a carbon nanotube having semiconductor characteristics, the source / drain interval L including prediction is preferably 0.5 μm or more. Is preferably 1 μm or more, and when the source / drain distance L is short, the source / drain length W needs to be shorter.

  On the other hand, the source / drain length W is desirably 100 μm or less, preferably 50 μm or less. When the source / drain length W is long, the source / drain distance L needs to be longer.

  As described above, in Example 1, undesired carbon nanotubes grown in a region other than between the source and drain electrodes are removed, and therefore, the undesired carbon nanotubes are adjacent to the source electrode or drain electrode of another CNT. The transistor characteristics are not lost due to the connection.

  In addition, by setting the source / drain distance L and the source / drain length W to a predetermined relationship, the conductive characteristics of the carbon nanotubes grown between the source / drain electrodes can be reliably made semiconductor characteristics. Manufacturing yield is also improved.

Here, with reference to FIGS. 7 to 11, a manufacturing process of the carbon nanotube transistor according to the second embodiment of the present invention will be described.
See FIG.
First, a SiO ₂ film 22 having a thickness of, for example, 300 nm is formed on the silicon substrate 21, and then a gate electrode 23 made of Mo having a thickness of, for example, 50 nm is formed by using a lift-off method.

Next, after depositing a SiO ₂ film on the entire surface and then planarizing to form the buried layer 24, the gate insulating film has a thickness of, for example, a 3 nm ZrO _x film 25 and an etching stopper. For example, a 5 nm Si ₃ N ₄ film 26 is sequentially deposited.

See FIG.
Next, again using a lift-off method, a pair of source electrodes having a thickness of, for example, 50 nm of Mo, a length W of 200 μm or less, and a distance L between them of 0.5 μm or less, more preferably 2 μm or less. 27 and the drain electrode 28 are formed, and then a SiO ₂ film 29 having a thickness of 200 nm to 1 μm, for example, 500 nm is deposited on the entire surface.

See FIG.
Next, after forming an opening 30 so as to expose a part of the source electrode 27 and the drain electrode 28, the exposed Si ₃ N ₄ film 26 is selectively removed to expose the ZrO _x film 25, and then nitric acid The Fe-based catalyst film 31 is formed on the surfaces of the source electrode 27 and the drain electrode 28 by dipping in a solution containing iron.9 hydrate [Fe (NO ₃ ) ₃ .9H ₂ O].

See FIG.
Next, carbon nanotubes 32 and 33 are grown on the entire surface by, for example, a CVD method using methane as a carbon supply source, and then an SiO ₂ film 34 is again deposited on the entire surface to fill the opening 30.

See FIG.
Next, by using the CMP (chemical mechanical polishing) method, the SiO ₂ films 29 and 34 are removed until just before the source electrode 27 and the drain electrode 28 are exposed, so that the excess carbon nanotubes 33 grown in a region other than the opening 30 are obtained. Remove.

Next, an SiO ₂ film 35 serving as an interlayer insulating film is again deposited on the entire surface, contact holes reaching the source electrode 27 and the drain electrode 28 are formed, and the contact hole is filled with a plug 36 made of TiN barrier metal 37 and W38. Then, for example, a conductor layer made of TiN / W / TiN is deposited and then patterned to form the wiring 39, whereby the basic configuration of the carbon nanotube transistor of Example 2 is completed.

  In Example 2, since carbon nanotubes grown in an undesired region are removed as in Example 1, CNTs that are not affected by adjacent CNTs are not short-circuited with adjacent CNTs. Can be configured.

  Also in this case, since the relationship between the source / drain distance L and the source / drain length L is set to a relationship in which carbon nanotubes having semiconductor characteristics grow, the operation of the CNT can be ensured.

  Further, in the second embodiment, since individual gate electrodes are provided, the operation of each CNT can be performed independently.

As mentioned above, although each Example of this invention was described, this invention is not restricted to the structure and conditions described in each Example, A various change is possible.
For example, in each of the above embodiments, Mo is used as the source / drain electrode. However, the present invention is not limited to Mo, and can withstand a temperature of 700 to 900 ° C. that is the growth temperature of carbon nanotubes. A conductor that can be easily patterned is suitable. For example, Au, Pt, Ir, WN _x , RuO _x , IrO _x , CoSi ₂ , NiSi, or polycrystalline Si may be used.

  In the first embodiment, the actual device structure that constitutes the integrated circuit device using the substrate as the gate electrode is not realistic. A gate insulating film and a gate electrode may be provided thereover.

In the second embodiment, Mo is used as the gate electrode. However, the gate electrode is not limited to Mo, and includes Au, Pt, Ir, WN _x , RuO _x , IrO _x , CoSi ₂ , NiSi, or polycrystalline Si may be used.

In the second embodiment, ZrO _x is used as the gate insulating film. However, the gate insulating film is not limited to ZrO _x , and SiO ₂ , Si ₃ N ₄ , SiON, Ta ₂ O ₅ , HfO, or HfSiO or the like may be used, and a high dielectric constant such as Ta ₂ O ₅ , HfO, or HfSiO similar to ZrO _x is particularly desirable.

In the second embodiment, Si ₃ N ₄ is used as an etching stopper. However, the etching stopper is not limited to Si ₃ N ₄ and serves as an etching stopper for the gate insulating film according to the material of the gate insulating film. It is only necessary to use insulators having different etching rates to the extent that they can be obtained, and it is also desirable that the insulating films forming the openings have different etching rates.

  In Example 2 described above, the exposed portion of the etching stopper is removed before the growth of the carbon nanotubes, but the etching stopper may be left as it is.

  In the second embodiment, the etching stopper is provided on the gate insulating film. However, the etching stopper is not always necessary. The gate insulating film is provided independently and the source / drain electrodes are provided thereon. It is good.

  In the second embodiment, the buried layer is formed before the growth of the gate insulating film in order to form the source / drain electrodes with high accuracy. However, the buried layer is not always necessary. A gate insulating film may be directly deposited after forming the drain electrode.

  In the second embodiment, the planarization process is performed by the CMP method. However, the present invention is not limited to the CMP method, and a reactive ion etching method or a wet etching method may be used. is there.

  In each of the above embodiments, methane is used as a carbon supply source for growing carbon nanotubes, but is not limited to methane, and ethylene, acetylene, methanol, ethanol, or the like may be used. It is.

In each of the above embodiments, an Fe-based catalyst is used as a catalyst. However, the catalyst is not limited to Fe, and an iron group other than Fe, such as Co or Ni, may be used. When CoSi ₂ or NiSi is used as the source / drain electrodes, a catalyst is not always necessary.

  In each of the above embodiments, the catalyst is formed by the dipping method. However, the present invention is not limited to the dipping method, and Co, Fe, Ni, etc. may be deposited by an evaporation method or the like. In this case, the catalyst can be formed at an arbitrary position by using the lift-off method.

  In each of the above embodiments, the carbon nanotubes are grown by the CVD method. However, the carbon nanotube is not limited to the CVD method, and may be formed by a laser ablation method or an arc discharge method.

  In each of the above embodiments, only the carbon nanotube is referred to as a conductive property, but it may be a single wall carbon nanotube (scnt) or a multi-wall carbon nanotube (mcnt). The number of carbon nanotubes grown between the source and drain electrodes is arbitrary, and the drain current can be increased as the number increases.

  In each of the above embodiments, a silicon substrate is used as the substrate. However, the substrate is not limited to a silicon substrate. When the substrate has a gate electrode function as in the first embodiment, Mo or the like is used. The metal substrate may be used.

When the substrate does not have a gate electrode function as in the second embodiment, a metal substrate such as Mo or an insulating substrate such as quartz, sapphire, MgO, Al ₂ O ₃ , or glass may be used. It ’s good.

Here, the detailed configuration of the present invention will be described again with reference to FIG.
Again see Figure 1
(Additional remark 1) The carbon nanotube transistor deposited on the source part 5, the drain part 6, and the carbon nanotubes 9 deposited on the region other than the region between the source part 5 and the drain part 6 is removed. Method.
(Additional remark 2) The process of providing the 2nd insulating film 4 on the said gate electrode 3 after providing the gate electrode 3 through the 1st insulating film 2 on the board | substrate 1, and on the said 2nd insulating film 4 After the source / drain portions 5 and 6 are provided, the third insulating film 7 is provided, and then at least a part of the source / drain portions 5 and 6 of the third insulating film 7 and the source portion 5 and the drain portion. The step of forming the opening 8 so that the region between the openings 6 is exposed, and the step of depositing the carbon nanotubes 9 on the entire surface and then removing the carbon nanotubes 9 deposited in the regions other than the opening 8. A method for producing a carbon nanotube transistor, comprising:
(Supplementary Note 3) The gate electrode 3 and the source / drain portions 5 and 6 are made of Mo, Au, Pt, Ir, WN _x , RuO _x , IrO _x , CoSi ₂ , NiSi, or polycrystalline Si. The method for producing a carbon nanotube transistor according to supplementary note 2, wherein:
(Supplementary Note 4) The second insulating film _{4, SiO 2, Si 3 N 4} , SiON, Ta 2 O 5, ZrO X, HfO, or a gate insulating film made of any one of HfSiO, the gate insulating film 4. The method of manufacturing a carbon nanotube transistor according to appendix 2 or 3, further comprising an etching stopper film which is provided on the gate insulating film and has a selective etching property with respect to the gate insulating film.
(Additional remark 5) The manufacturing method of the carbon nanotube transistor of Additional remark 4 characterized by removing the exposed part in the said opening part 8 of the said etching stopper film | membrane before the deposition process of the said carbon nanotube 9. FIG.
(Additional remark 6) It has the process of making the catalyst at the time of depositing the said carbon nanotube 9 adhere to at least one part of the said source / drain parts 5 and 6 before the deposition process of the said carbon nanotube 9 characterized by the above-mentioned. The method for producing a carbon nanotube transistor according to any one of 1 to 5.
(Supplementary Note 7) In the step of removing the carbon nanotubes 9 deposited in the region other than the opening 8, the opening 8 is filled with an embedded film 10 made of either an inorganic insulating material or a resist, and then the embedded The method of manufacturing a carbon nanotube transistor according to appendix 2, wherein the film 10 is removed together with the third insulating film 7 and is planarized.
(Additional remark 8) The said planarization process consists of either a chemical mechanical polishing method, the reactive ion etching method, or the wet etching method, The manufacturing method of the carbon nanotube transistor of Additional remark 7 characterized by the above-mentioned.
(Additional remark 9) The space | interval of the area | region between the said source part 5 and the drain part 6 is 0.5 micrometer or more, and the length of the said source / drain parts 5 and 6 is 100 micrometers or less, It is characterized by the above-mentioned. The method for producing a carbon nanotube transistor according to any one of appendices 1 to 8.
(Supplementary note 10) A carbon nanotube transistor comprising the manufacturing method according to supplementary note 1.

  The utilization example of the present invention is not limited to the above-described simple CNT, but by utilizing the very excellent characteristics of p-channel CNT, p-channel CNT is formed on a silicon substrate on which an n-channel SiMOSFET is formed. It may be formed to constitute a composite high-speed CMOS.

It is explanatory drawing of the fundamental structure of this invention. It is explanatory drawing of the manufacturing process of the carbon nanotube transistor of Example 1 of this invention. It is an IV characteristic diagram of CNT at the time of applying -10V to a silicon substrate. It is an IV characteristic diagram of CNT at the time of applying + 10V to a silicon substrate. It is an IV characteristic view of CNT in case a carbon nanotube shows a metal characteristic. It is explanatory drawing of the source-drain space | interval L and source-drain length W dependence of the electrical conductivity of a carbon nanotube. It is explanatory drawing of the manufacturing process to the middle of the carbon nanotube transistor of Example 2 of this invention. It is explanatory drawing of the manufacturing process until the middle of FIG. 7 or subsequent of the carbon nanotube transistor of Example 2 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 8 of the carbon nanotube transistor of Example 2 of this invention. It is explanatory drawing of the manufacturing process until the middle of FIG. 9 or subsequent of the carbon nanotube transistor of Example 2 of this invention. It is explanatory drawing of the manufacturing process after FIG. 10 of the carbon nanotube transistor of Example 2 of this invention. It is a conceptual perspective view of the conventional CNT. It is a schematic sectional drawing of the conventional CNT. It is a conceptual top view in the case of comprising a plurality of CNTs.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 First insulating film 3 Gate electrode 4 Second insulating film 5 Source part 6 Drain part 7 Third insulating film 8 Opening part 9 Carbon nanotube 10 Embedded film 11 Silicon substrate 12 SiO ₂ film 13 Source electrode 14 Drain electrode 15 Lead electrode 16 Pad portion 17 Carbon nanotube 18 Carbon nanotube 21 Silicon substrate 22 SiO ₂ film 23 Gate electrode 24 Buried layer 25 ZrO _x film 26 Si ₃ N ₄ film 27 Source electrode 28 Drain electrode 29 SiO ₂ film 30 Opening Part 31 Fe-based catalyst film 32 Carbon nanotube 33 Carbon nanotube 34 SiO ₂ film 35 SiO ₂ film 36 Plug 37 TiN barrier metal 38 W
39 Wiring 41 Silicon substrate 42 SiO ₂ film 43 Source electrode 44 Drain electrode 45 Catalyst 46 Carbon nanotube 47 Gate insulating film 48 Gate electrode

Claims (5)

A method of manufacturing a carbon nanotube transistor, comprising removing carbon nanotubes deposited on a region other than a region between a source portion, a drain portion, and the source portion and the drain portion. A step of providing a gate electrode on the substrate via a first insulating film, a step of providing a second insulating film on the gate electrode, and a step of providing a source / drain portion on the second insulating film and a third step Forming an opening so as to expose at least a part of the source / drain portion of the third insulating film and a region between the source portion and the drain portion. And a step of removing the carbon nanotubes deposited in a region other than the opening after the carbon nanotubes are deposited. _3. The gate electrode and the source / drain portion are made of any one of Mo, Au, Pt, Ir, WN _x , RuO _x , IrO _x , CoSi ₂ , NiSi, or polycrystalline Si. The manufacturing method of the carbon nanotube transistor of description. The second insulating film is provided on the gate insulating film and a gate insulating film made of any of SiO ₂ , Si ₃ N ₄ , SiON, Ta ₂ O ₅ , ZrO _x , HfO, or HfSiO. 4. The method of manufacturing a carbon nanotube transistor according to claim 2, comprising an etching stopper film having selective etching property with respect to the gate insulating film. 5. The space between the source part and the drain part is 0.5 [mu] m or more, and the length of the source / drain part is 100 [mu] m or less. The manufacturing method of the carbon nanotube transistor of description.

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