JP2010183122A - Semiconductor device and production method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the productivity and the cost in production of semiconductor devices named a wafer-level CSP. <P>SOLUTION: A production process of semiconductor devices includes steps of forming interconnects 18 to electrically connect each of electrode pads 10a and external connection terminals on a wafer 10, having semiconductor elements formed thereon, connecting conductive balls formed in advance by another step thereon, and then covering the wafer with a resin 32 in a state that the upper portions of conductive support columns 30 are exposed. In the successive steps, a solder ball 34 as external connection terminal is disposed on the upper portion of the conductive support column. In the final step, the wafer is diced along the boundary lines of the semiconductor elements to form semiconductor devices. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a so-called wafer level CSP type semiconductor device in which a semiconductor chip can be packaged in a wafer state and a method for manufacturing the same.

  In the semiconductor device manufacturing industry, efforts are being made to further reduce the size of one packaged semiconductor device. The first effort to realize the miniaturization of the semiconductor device is to reduce the size of the semiconductor chip itself. By reducing the size of the semiconductor chip, the number of chips that can be obtained from one wafer is increased, the manufacturing cost is reduced, and the movement distance of electrons between each element can be shortened. improves. With the development of microfabrication technology, it has become possible to reduce the chip size of a semiconductor device having the same function. The current state-of-the-art design rule is 0.18 μm or less, and according to this, 20 million or more transistors can be formed on one semiconductor chip.

  In order to reduce the size of the semiconductor device, the next effort is to make the size of the package encapsulating the semiconductor chip as close as possible to the size of the built-in semiconductor chip. As a result of this effort, a semiconductor device of a type called a chip size package (CSP) or a chip scale package (Chip Scale Package) was born. In the chip size package, connection terminals (for example, solder balls, hereinafter referred to as external connection terminals) for a printed wiring board on which a semiconductor device is mounted are two-dimensionally arranged on the surface of the semiconductor chip, and the size of the package is thus reduced. Has succeeded in bringing the chip closer to the chip size. When the package size is reduced to be closer to the semiconductor chip size, the mounting area is reduced, and the wiring length connecting the electrode on the chip and the external connection terminal is shortened, thereby reducing the semiconductor chip itself. As with the above, the operation speed of the semiconductor device was improved.

  On the other hand, there is a problem that even if the package size is reduced, the manufacturing cost cannot be reduced much. This is because the process of the package is performed for each individual semiconductor chip cut out from the wafer. Therefore, even if the package size is reduced, the process man-hour is constant and the productivity is not changed.

  From such a background, a technique for packaging a semiconductor chip in a wafer state (hereinafter referred to as a wafer level CSP) has been proposed, and development for practical use is being promoted by each company. Wafer level CSP is a semiconductor manufacturing technology for packaging individual semiconductor chips before they are cut out from the wafer. In the wafer level CSP, since the package process can be integrated with the wafer process, there is an advantage that the package cost and, moreover, the manufacturing cost of the semiconductor device can be greatly reduced. For further details of the wafer level CSP, refer to “Nikkei Microdevices August 1998, pages 44-71” published by Nikkei BP.

  On the other hand, in the wafer level CSP, there is a problem of mounting reliability with respect to the printed wiring board as in the conventional CSP type semiconductor device. In a temperature cycle test for this type of semiconductor device, a crack may occur at the joint portion of the external connection terminal to the printed wiring board, resulting in an open defect. The main cause is due to stress based on the difference in coefficient of linear expansion between a semiconductor chip made of silicon and a printed wiring board made of FR4 or the like, and means for alleviating this must be taken in the design of a wafer level CSP.

  Therefore, as a suitable method for absorbing the difference in linear expansion coefficient between the semiconductor chip and the printed wiring board and relieving the stress caused thereby, a metal post is formed on the wiring pattern of the semiconductor chip main surface, There has been proposed a structure in which an external connection terminal such as a solder ball is joined to the support. In the semiconductor device, the main surface of the semiconductor chip and the periphery of the support are covered with resin. By interposing the post between the external connection terminal directly bonded to the printed wiring board and the semiconductor chip, it can be mitigated by deformation of the post portion when the stress is generated.

On the other hand, the semiconductor device provided with the metal support has the following problems.
(1) It takes time and cost to form the metal support on the main surface of the semiconductor chip. That is, the metal column is formed by laminating metal plating (for example, copper plating) on the wiring pattern. In order to relieve the stress, it is necessary to raise the support column to a height of 100 μm or more, and it takes 2 hours or more to form the support column by plating. In order to further improve the mounting reliability of the semiconductor device, it is necessary to further increase the supporting column (for example, 200 μm or more), but it is extremely difficult to realize it in terms of necessary time and cost.
(2) When metal posts are formed by plating, their shape, material, etc. cannot be freely selected, so the degree of freedom in designing the target package is limited.

  Accordingly, an object of the present invention is to improve the productivity of a semiconductor device called a wafer level CSP while ensuring its mounting reliability.

  In order to achieve the above object, a semiconductor device of the present invention is provided on a semiconductor chip having an electrode pad electrically connected to an electric circuit formed on a main surface of a semiconductor substrate, and the semiconductor chip. A substantially spherical conductive column electrically connected to the electrode pad; a resin formed on the semiconductor chip so that a top portion of the conductive column is exposed; and a top portion of the conductive column. And an external connection terminal.

  In a preferred embodiment, the electrode pad and the conductive column are electrically connected by wiring formed on the semiconductor chip. Further, the external connection terminal is preferably a solder ball, and more preferably, the conductive support is made of a substantially spherical copper ball and solder covering the surface of the copper ball. Furthermore, the height of the conductive support is preferably 200 μm or more.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: preparing a wafer on which a semiconductor element having an electric circuit and an electrode pad electrically connected to the electric circuit is formed; Forming a wiring for electrically connecting the external connection terminal and the electrode pad; connecting a pre-formed conductive column at a predetermined position of the wiring; and conducting the conductive material on the semiconductor element. Forming a resin so that the top of the conductive support is exposed; forming an external connection terminal on the top of the conductive support; and obtaining a semiconductor device in which the external connection terminal is formed by dicing the wafer. And have.

  Further, the step of forming the resin includes a step of supplying and curing a soft resin on the semiconductor chip, and a surface of the resin and an upper portion of the conductive column are ground to expose a top portion of the conductive column. It is preferable to include the process to make.

  In the present invention, since the support pillar for the external connection terminal can be formed by mounting and connecting the conductive support pillar at a predetermined position of the wiring, the object can be achieved in a very short time compared to the formation of the support pillar by the conventional plating method. Can be obtained. Thereby, the freedom degree of the design of a support | pillar can be raised and the support | pillar of a dimension, a shape, and a material required and sufficient for obtaining the mounting reliability of a package by it can be obtained.

  Further, the conductive support is preferably composed of a substantially spherical copper ball and a solder covering the surface of the copper ball, and the step of connecting the conductive support includes connecting the conductive support to the predetermined wiring line. It is preferable to include a step of placing the conductive strut on a position and a step of melting the solder on the surface of the conductive strut and connecting the conductive strut to a predetermined position of the wiring. Further, the step of forming the external connection terminal includes a step of placing a solder ball on the top of the conductive column, and a step of melting the solder ball and connecting the solder ball to the conductive column. It is preferable to include.

  As described above, according to the present invention, in a semiconductor device called a wafer level CSP, it is possible to improve the productivity and cost that have been problems in the conventional plating method while ensuring the mounting reliability.

  In addition, according to the manufacturing method of the present invention, a conductive support having a height of 200 μm or more can be easily obtained, so that it is easy to suppress the generation of stress due to the difference in linear expansion coefficient between members. The mounting reliability of this type of semiconductor device can be improved.

It is a figure which shows the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention. It is a figure which shows the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention. It is a figure which shows the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention. It is a figure which shows the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention. It is a schematic sectional drawing of the BGA type semiconductor device obtained by the manufacturing method which concerns on this invention. It is the figure which expanded the principal part of the semiconductor device of FIG. It is the figure which expanded the principal part of the LGA type semiconductor device obtained by the manufacturing method which concerns on this invention.

  Embodiments of the present invention will be described below with reference to the drawings. In the method of manufacturing a semiconductor device according to the present embodiment, a package process is performed in the state of a wafer on which semiconductor elements are formed, and a packaged semiconductor device is obtained when the wafer is finally diced. In the manufacturing method according to the present embodiment, necessary wiring is provided on the surface of a wafer on which a semiconductor element is formed, and conductive balls prepared in a separate process are connected on the surface, and the wafer surface is covered with a resin, and external connection is performed. It includes a step of transferring solder balls as terminals and dicing the wafer along the boundary line of the semiconductor element to obtain individual packages. These specific steps will be sequentially described with reference to FIGS. Those skilled in the art will appreciate that these figures are exaggerated for purposes of illustration. In the figure, only a partial cross section of the wafer (corresponding to two semiconductor devices) is shown, but the processing described below is performed over the entire area of the wafer according to each step shown in the figure. It will be understood that

  Prior to the illustrated steps, a normal wafer process is performed to form semiconductor elements arranged in a matrix on the surface of the silicon wafer. Here, one circuit pattern on the wafer formed corresponding to one semiconductor device is called a semiconductor element. A plurality of electrode pads drawn from each semiconductor element are exposed on the wafer surface, and each electrode pad and an external connection terminal are electrically connected in a later process.

  In the first step (A) according to the present embodiment shown in FIG. 1, a layer 12 of photosensitive polyimide resin is formed on the surface of the wafer 10 on which the semiconductor elements are formed in the wafer process. This layer 12 temporarily covers the electrode pad 10 a over the entire area of the wafer 10. This layer 12 covers the surface of the relatively fragile silicon wafer and mitigates the impact applied from the outside of the finished package to the wafer surface. Next, in step (B), a photomask is used to mask the region corresponding to the electrode pad 10a and the region along the boundary line of the semiconductor element, and after exposing the photosensitive polyimide resin, the polyimide resin on the region is exposed. Is removed by etching.

  Next, in order to form metal wiring on the wafer, the process (C) in FIG. 1 to the process (J) in FIG. 2 are performed. First, in step (C), titanium tungsten (TiW) is deposited on the wafer surface by ion sputtering, and then a barrier metal 14 such as chromium (Cr) or nickel (Ni) is formed thereon. Thereafter, in step (D), a resist 16 is formed by photolithography to form wiring, and in step (E), copper (Cu) is plated on the exposed barrier metal 14 to form wiring 18. To do.

  Then, in step (F) of FIG. 2, after titanium tungsten (TiW) is deposited again on the wafer surface by ion sputtering, gold (Au), palladium (Pd), and other precious metals 20 that are difficult to oxidize are interconnected. Evaporate on 18. Next, in step (G), the resist 16 is removed, and in step (H), a resist 22 is formed again by photolithography in order to perform metal etching thereon. Further, the barrier metal 14 other than the wiring portion is etched in the step (I), and the resist 22 is removed again in the step (J). Through the above steps, wiring 18 for connecting conductive balls and external connection terminals is formed on the wafer 10.

  Next, steps (K) to (N) of FIG. 3 are performed in order to form conductive columns on the wiring 18. In the manufacturing method of the present invention, in order to form the conductive support on the wiring 18, the conductive ball 28 prepared in another process is used. The conductive ball electrically connects the wiring 18 and a solder ball 34 which is an external connection terminal to be described later, and can be generated when the package is mounted on a printed circuit board (that is, a semiconductor chip) and a solder ball side. It functions to relieve stress due to the difference in coefficient of linear expansion with respect to (ie, the printed circuit board). The conductive balls are formed in a separate process, transferred onto the wafer, and connected to the wiring 18 to form conductive columns. In one embodiment, the conductive ball may be a spherical ball with copper as the core and the surface covered with solder.

  As will be described later, the conductive ball having such a structure improves the connection between the wiring and the external connection terminal by the outer solder, and prevents the shape from being deformed at the time of reflow by the central copper. For this purpose, if the connectivity with the wiring and the external connection terminal is maintained, the entire conductive ball may be formed of a highly conductive material such as copper. In this case, the conductive balls are connected on the wiring using solder paste. Further, if it is guaranteed that the shape is constant, that is, the shape does not change greatly after mounting, the whole may be formed of solder. Furthermore, the metal at the center of the conductive ball may be formed of a metal having a low diffusion coefficient for solder other than copper. In one embodiment, the thickness of the solder around the copper is approximately 20 μm.

  First, in step (K) of FIG. 3, prior to connecting the conductive balls, an opening 24a is formed in the position at the position. That is, a resist 24 is formed on the wafer so as to cover the wiring 18, and only the portion of the opening 24a is removed by photolithography. As a result, the wiring is exposed at the position of the opening 24a to which the conductive ball is connected. Next, in the step (L), the solder paste 26 is supplied to the opening 24a by screen printing. Subsequently, the conductive ball 28 prepared in advance is attracted by a handler (not shown) and transferred onto the opening 24a. Then, the solder on the ball surface and the solder paste 26 are melted and connected to the wiring 18 by collective reflow to obtain a substantially spherical conductive support. Those skilled in the art will understand that a method similar to the method of mounting solder balls as external connection terminals in a BGA (Ball grid array) can also be adopted here. A large number of conductive balls 28 are collectively sucked by a predetermined suction jig, the flux is transferred to the lower surface thereof, and then each conductive ball is transferred onto the opening 24a. In this state, the wafer 10 is passed through a reflow furnace, the solder on the surface of each conductive ball 28 and the solder paste 26 in the opening 24 a are melted, and the conductive ball 28 can be connected to the wiring 18. In one embodiment, 240 ° C. max. And a belt speed of 0.5 m / min. In this case, the time taken to implement the steps (L) to (M) was about 10 minutes. In the next step (N), the resist 24 covering the surface of the wafer 10 is removed, thereby forming the conductive columns 30 on the wiring.

  After the conductive balls 28 are connected, the package resin 32 is supplied onto the wafer 10 in the step (O) of FIG. 4 and is spread evenly over the entire surface. The height of the uniformly spread package resin 32 is such that it completely covers the conductive column 30 or leaves a small area on the upper side of the conductive column 30 as shown. In order to uniformly supply the package resin 32 onto the wafer, a spin coating method, a screen printing method, or another resin supply method can be employed. The liquid or gel resin 32 is cured by curing for a predetermined time. In carrying out the present invention, the package resin 32 is preferably a photosensitive polyimide resin. Next, in step (P), the entire surface of the package resin 32 is smoothed by grinding or polishing using a grinder or other grinding apparatus. At this time, the upper part of the conductive support column 30 is also ground together, whereby the conductive support column 30 is exposed and a smooth circular region 30a is formed here. In the case where a conductive ball 28 having a core made of copper and covered with solder is used, the inner copper is preferably exposed as a part of the region 30a by grinding or polishing the surface. In a preferred embodiment, the diameter of the conductive ball 28 used is, for example, 400 μm, and the remaining ball height after grinding is connected to the wiring and is 200 μm or more, preferably less than 300 μm. is there.

  Next, in order to connect the solder balls 34 as external connection terminals, the step (Q) of FIG. 4 is performed. Similar to the previous steps (K) to (M), after applying a resist on the surface of the ground wafer, the smooth area of the conductive support is removed by etching, and a solder paste is screened here. Fill by printing method. Next, the solder balls 34 produced in another process are transferred onto the smooth region 30a and fixed by batch reflow. The solder balls 34 are melted on the smooth region 30a by reflow, and are firmly bonded through a wide contact area of the region 30a. Subsequently, in step (R), the wafer 10 is diced using a dicing saw 36 to obtain a packaged semiconductor device 38.

  FIG. 5 shows an example of a semiconductor device obtained by the manufacturing method according to the present invention. Moreover, FIG. 6 is the figure which expanded the principal part. In these drawings, a large number of solder balls 34 are two-dimensionally arranged as external connection terminals on the mounting surface side (the upper side in the figure) of the semiconductor device 38. Each solder ball 34 is electrically connected to each electrode pad 10 a of the semiconductor device 38 by the conductive support 30 and the wiring 18 covered with the package resin 32.

  FIG. 6 shows a state of the semiconductor device 38 in which the photosensitive polyimide resin 12, the wiring 18, the conductive support 30 and the solder ball 34 are formed on the wafer 10. As shown in the above manufacturing process of the semiconductor device 38, the wiring 18 on the electrode pad 10a and the solder ball 34 are connected via the conductive support 30 obtained by connecting the conductive ball 28 manufactured in a separate process. Are electrically connected. Such a conductive ball has an advantage that its contact area can be made relatively large by using a substantially spherical member. It will be understood by those skilled in the art that the increased contact area between these members increases the connection reliability between the members and increases the conductivity.

  FIG. 7 is an enlarged view of a main part of another embodiment of a semiconductor device manufactured by the manufacturing method of the present invention. The illustrated semiconductor device 70 includes a package having an LGA (Land grid array) structure. That is, the semiconductor device 70 shown in the figure includes a land 71 formed of a solder paste as an external connection terminal to a printed circuit board. The land 71 is formed by applying a solder paste on the region 30a and reflowing it in a lump without transferring the solder ball in the step (Q) in the previous embodiment.

  The embodiments of the present invention have been described with reference to the drawings. It is obvious that the scope of application of the present invention is limited only in accordance with the description of the scope of claims, and is not limited by the matters shown in the above embodiments. In the mounting form described above, a substantially spherical conductive ball was used to form the conductive column. According to the object of the present invention, the shape may be a columnar shape, a conical shape, a prismatic shape, an elliptical shape or the like as long as it is manufactured in a separate process.

  The present invention relates to a so-called wafer level CSP type semiconductor device in which a semiconductor chip can be packaged in a wafer state and a method for manufacturing the same.

DESCRIPTION OF SYMBOLS 10 Wafer 10a Electrode pad 12 Photosensitive polyimide resin 14 Barrier metal 16 Resist 18 Wiring 20 Precious metal 22 Resist 24 Resist 24a Opening 26 Solder paste 28 Conductive ball 30 Conductive support | pillar 30a Solder ball connection area 32 Package resin 34 Solder ball 36 Dicing saw 38 Semiconductor device 70 Semiconductor device 71 Land

Claims (1)

A semiconductor chip having an electrode pad electrically connected to an electric circuit formed on the main surface of the semiconductor substrate;
A substantially spherical conductive support provided on the semiconductor chip and electrically connected to the electrode pad;
A resin formed on the semiconductor chip so as to expose the top of the conductive support;
An external connection terminal provided on the top of the conductive support;
A semiconductor device.

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