JP2010182331A - マルチプロセッサ・メモリ整合性の効率のよいエミュレーションのための方法 - Google Patents
マルチプロセッサ・メモリ整合性の効率のよいエミュレーションのための方法 Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1072—Decentralised address translation, e.g. in distributed shared memory systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/656—Address space sharing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/68—Details of translation look-aside buffer [TLB]
- G06F2212/682—Multiprocessor TLB consistency
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Abstract
【解決手段】 マルチプロセッサ・システムにおけるエミュレーションの方法(およびシステム)は、マルチプロセッサ・システムのホスト・マルチプロセッシング・システムが弱い整合性モデルをサポートし、マルチプロセッサ・システムのターゲット・マルチプロセッシング・システムが強い整合性モデルをサポートするエミュレーションを実行するステップを含む。
【選択図】 図8
Description
るが、これは単に、ステートメントS1がプログラム内に提示された命令シーケンス内の他のステートメントS2より先行する場合に、プロセッサはS2がその実行を開始する前にS1がその実行を完了したかのように動作しなければならないことを意味するだけである。これは、レジスタおよびメモリを含む、いずれかのリソースに対してS1が行った変更をS2が把握していなければならないことを暗示する。
ルゴリズムは、ターゲット・プロセッサ201、202としてのプロセッサ201、202上で実行しているものと見なさなければならない。
1.マッピングなし
2.排他読取り
3.排他書込み
4.共用読取り
5.共用書込み
始する前にすでにその人がそれを読み取ったことを確認するのは、何らかの「教師」(たとえば、このケースでは何らかのプログラム)の責任である。人々は読取りと書込みを続けるので、これはより混沌とした状況になる。多くの従来のプロセッサは現在、このような「弱い」整合性モデルを使用している。というのは、それによって、プロセッサは共用する場合よりかなり高速になるからである。したがって、パフォーマンスの観点から見ると、「弱い」整合性モデルは、共用があまり行われないときには、より優れたモデルになる。
第6031992号を参照)に記述されているように、まとめて変換すべき複数命令のグループについて検討し、変換したグループについて最適化を実行することにより、エミュレーション・パフォーマンスを改善することが可能な場合が多い。
202、430B プロセッサ2
1418 I/Oアダプタ
1422 ユーザ・インタフェース・アダプタ
1434 通信アダプタ
1436 ディスプレイ・アダプタ
1439 プリンタ
Claims (10)
- 複数命令のグループ実行の終了時に共用書込みをメモリにコミットする方法において、
変換の終了時に、あるブロックがアクセスした「共用書込み」位置への値をマルチプロセッサ・システムの他のどのプロセッサも変更していないことをチェックして保証するスタブ・コードを追加するステップを具備する方法。 - 他のプロセッサによるアクセスから共用メモリ位置をロックするステップと、
各ロード位置を再ロードし、対応するメモリ・オーダ・バッファ(MOB)項目内に記憶された値と比較するステップとをさらに具備し、
すべての再ロードが元のロードと同じであると判明した場合に、前記MOBからのすべてのストアがメモリ内のそれぞれの実際の位置に対して行われる、請求項1に記載の方法。 - ロード妥当性検査プロセス中に不一致が発生した場合に、すべてのレジスタをそれぞれの旧状態に復元し、ストア回復テーブル(SRT)内の操作をアンドゥすることによって非「共用書込み」位置に対して行った前記ストアを逆転することにより、前記グループの実行全体を取り消すステップをさらに具備する、請求項2に記載の方法。
- 前記システムを前に有効だった状態に戻した後、実行を再試行するステップをさらに具備する、請求項3に記載の方法。
- 共用メモリ位置へのアクセスをロックするステップと、
メモリ・オーダ・バッファ(MOB)内の第1の項目にポインタを設定し、前記MOBの終わりに達したかどうかを判定するステップと、
前記終わりに達していない場合に、前記MOB内のその項目が空であるかどうかを判定するステップと、
前記項目がロードではないと判定された場合に、前記MOBへのポインタを増分するステップとをさらに具備する、請求項1に記載の方法。 - 前記項目がロードであると判定された場合に、前記項目内のアドレスから前記項目を再ロードするステップと、
再ロードした値が前記項目内の値と一致するかどうかを判定するステップと、
前記値が一致した場合に、前記MOBへのポインタを増分するステップと、
前記値が一致しない場合に、前記ロックを解除し、前記状態を復元し、ストア回復テーブル(SRT)を使用して非共用書込みを復元することにより、前記グループの先頭まで回復を実行するステップとをさらに具備する、請求項5に記載の方法。 - 前記MOBの終わりに達している場合に、前記MOB内の前記第1の項目に前記ポインタを設定し、前記MOBの終わりに達したかどうかを判定するステップと、
前記終わりに達していない場合に、前記MOB内の前記項目が空であるかどうかを判定するステップと、
前記MOB内の前記項目がストアであるかどうかを判定するステップと、
前記項目がストアである場合に、前記値をメモリに書き込み、前記MOB内の前記ポインタを増分するステップとをさらに具備する、請求項6に記載の方法。 - 前記MOB内の前記項目がストアではない場合に、前記MOB内の前記ポインタが増分される、請求項7に記載の方法。
- 複数の命令を1つずつ処理するステップをさらに具備する、請求項1に記載の方法。
- メモリ・オーダ・バッファ(MOB)とストア回復テーブル(SRT)とを使用することにより、複数命令のグループ内の命令を処理するステップをさらに具備する、請求項1に記載の方法。
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US10/244,434 US9043194B2 (en) | 2002-09-17 | 2002-09-17 | Method and system for efficient emulation of multiprocessor memory consistency |
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JP2003302164A Expired - Fee Related JP3980538B2 (ja) | 2002-09-17 | 2003-08-26 | マルチプロセッシング・システムにおけるメモリ整合性を保証する方法、マルチプロセッサ・システムにおいて複数命令のグループ内の整合性を維持するためのコードを挿入する方法、複数命令のグループ実行の終了時に共用書込みをメモリにコミットする方法 |
JP2006281049A Expired - Fee Related JP4658894B2 (ja) | 2002-09-17 | 2006-10-16 | マルチプロセッサ・メモリ整合性の効率のよいエミュレーションのための方法 |
JP2010087222A Expired - Fee Related JP5116794B2 (ja) | 2002-09-17 | 2010-04-05 | マルチプロセッサ・メモリ整合性の効率のよいエミュレーションのための方法 |
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JP5116794B2 (ja) | 2013-01-09 |
JP2007042134A (ja) | 2007-02-15 |
JP3980538B2 (ja) | 2007-09-26 |
JP2004110811A (ja) | 2004-04-08 |
US20040078186A1 (en) | 2004-04-22 |
CN1492324A (zh) | 2004-04-28 |
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US9043194B2 (en) | 2015-05-26 |
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