JP4658894B2 - マルチプロセッサ・メモリ整合性の効率のよいエミュレーションのための方法 - Google Patents
マルチプロセッサ・メモリ整合性の効率のよいエミュレーションのための方法 Download PDFInfo
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- JP4658894B2 JP4658894B2 JP2006281049A JP2006281049A JP4658894B2 JP 4658894 B2 JP4658894 B2 JP 4658894B2 JP 2006281049 A JP2006281049 A JP 2006281049A JP 2006281049 A JP2006281049 A JP 2006281049A JP 4658894 B2 JP4658894 B2 JP 4658894B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1072—Decentralised address translation, e.g. in distributed shared memory systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/656—Address space sharing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/68—Details of translation look-aside buffer [TLB]
- G06F2212/682—Multiprocessor TLB consistency
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Description
1998年2月発表のStephenA. Herrodの「Using Complete MachineSimulation to Understand Computer System Behavior」というスタンフォード大学博士論文 1987年10月4〜8日にオーランドで開催されたObject Oriented Programming Systems Languages and ApplicationsConference (OOPSLA)の会議録ならびにSpecialIssue of Sigplan Notices, vol. 22, No. 12, Dec. 1987, vol. 22, No. 7, Jun. 24におけるCathy Mayによる「Mimic: A Fast System/370 Simulator」という論文 1996年12月発行のIEEEComputer, vol. 29, no. 12の66〜76ページに掲載されたSaritaAdve他の「Shared MemoryConsistency Models: A Tutorial」という論文 1979年9月発行のIEEETransactions on Computers, C-28, 9の690〜691ページに掲載されたL. Lamportの「How to Make aMultiprocessor Computer That Correctly Executes Multiprocess Programs」という論文
1.マッピングなし
2.排他読取り
3.排他書込み
4.共用読取り
5.共用書込み
202、430B プロセッサ2
1418 I/Oアダプタ
1422 ユーザ・インタフェース・アダプタ
1434 通信アダプタ
1436 ディスプレイ・アダプタ
1439 プリンタ
Claims (4)
- マルチプロセッシング・システムにおけるメモリ整合性を保証する方法において、
命令がロードまたはストアであるかどうかを判定するステップと、
前記命令がロードまたはストアであると判定された場合に、前記命令のアドレスを解明し、前記アドレスがローカル・ルックアサイド・バッファ(LLB)に記憶されているかどうかを判定するステップと、
前記アドレスが前記LLB内にある場合に、その位置が共用読取り状態になっているかどうかを判定するステップと、
前記位置が共用読取り状態になっていると判定された場合に、現行アクセスが書込みであるかどうかを判定するステップと、
前記現行アクセスが書込みではない場合に、前記命令のエミュレーションを実行するステップとを具備する方法。 - 前記アドレスが前記LLBに記憶されていない場合に、LLBミスに関する手順を開始し、前記方法が、
前記現行アクセスが書込みであると判定された場合に、前記位置を共用書込み状態に設定し、前記命令をエミュレートし、メモリ・バリア命令をそこに置くステップをさらに具備する、請求項1に記載の方法。 - 前記位置が共用読取り状態になっていないと判定された場合に、前記位置が共用書込み状態であるかどうかを判定するステップと、
前記位置が共用書込み状態であると判定された場合に、前記命令をエミュレートし、前記メモリ・バリア命令をそこに置くステップとをさらに具備する、請求項2に記載の方法。 - 前記位置が共用書込み状態であるかどうかまたは前記命令が共用書込みになるかどうかを判定するステップと、
共用書込み命令および共用書込みになりうる命令に関するメモリ・バリア命令を置くステップとをさらに具備する、請求項1に記載の方法。
Applications Claiming Priority (1)
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US10/244,434 US9043194B2 (en) | 2002-09-17 | 2002-09-17 | Method and system for efficient emulation of multiprocessor memory consistency |
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JP2003302164A Division JP3980538B2 (ja) | 2002-09-17 | 2003-08-26 | マルチプロセッシング・システムにおけるメモリ整合性を保証する方法、マルチプロセッサ・システムにおいて複数命令のグループ内の整合性を維持するためのコードを挿入する方法、複数命令のグループ実行の終了時に共用書込みをメモリにコミットする方法 |
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JP2010087222A Division JP5116794B2 (ja) | 2002-09-17 | 2010-04-05 | マルチプロセッサ・メモリ整合性の効率のよいエミュレーションのための方法 |
Publications (2)
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JP2007042134A JP2007042134A (ja) | 2007-02-15 |
JP4658894B2 true JP4658894B2 (ja) | 2011-03-23 |
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JP2003302164A Expired - Fee Related JP3980538B2 (ja) | 2002-09-17 | 2003-08-26 | マルチプロセッシング・システムにおけるメモリ整合性を保証する方法、マルチプロセッサ・システムにおいて複数命令のグループ内の整合性を維持するためのコードを挿入する方法、複数命令のグループ実行の終了時に共用書込みをメモリにコミットする方法 |
JP2006281049A Expired - Fee Related JP4658894B2 (ja) | 2002-09-17 | 2006-10-16 | マルチプロセッサ・メモリ整合性の効率のよいエミュレーションのための方法 |
JP2010087222A Expired - Fee Related JP5116794B2 (ja) | 2002-09-17 | 2010-04-05 | マルチプロセッサ・メモリ整合性の効率のよいエミュレーションのための方法 |
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JP2003302164A Expired - Fee Related JP3980538B2 (ja) | 2002-09-17 | 2003-08-26 | マルチプロセッシング・システムにおけるメモリ整合性を保証する方法、マルチプロセッサ・システムにおいて複数命令のグループ内の整合性を維持するためのコードを挿入する方法、複数命令のグループ実行の終了時に共用書込みをメモリにコミットする方法 |
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US (1) | US9043194B2 (ja) |
JP (3) | JP3980538B2 (ja) |
CN (1) | CN100495342C (ja) |
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JP5116794B2 (ja) | 2013-01-09 |
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