JP2010178461A - Semiconductor protection circuit - Google Patents
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Abstract
Description
本発明は、IGBTやMOSFETなどの電圧駆動型半導体素子の過渡動作時おいて、過電圧を抑制するための保護回路に関する。 The present invention relates to a protection circuit for suppressing overvoltage during transient operation of voltage-driven semiconductor elements such as IGBTs and MOSFETs.
現在、電圧駆動型半導体素子(以下、素子ともいう)であるIGBTやMOSFETは、多くの電力変換回路に適用されており、高性能化が図られている。しかし、スイッチング時の過渡動作が速く、ターンオフ動作時には電力変換回路に浮遊するインダクタンス分によって大きなサージ電圧が発生するため、これが定格電圧を超えると素子破壊を招く可能性が大きい。これを防止するためには、浮遊インダクタンスを極限まで低減するような配線構造にする必要があるが、電力変換回路の直流電圧変動などを考慮すると、配線構造のみの対策では不十分な場合が多い。そのため、素子を過電圧から保護する様々な方式が提案されている。以下に従来の技術例について説明する。 Currently, IGBTs and MOSFETs, which are voltage-driven semiconductor elements (hereinafter also referred to as elements), are applied to many power conversion circuits, and high performance is achieved. However, a transient operation at the time of switching is fast, and a large surge voltage is generated due to an inductance component floating in the power conversion circuit at the time of turn-off operation. Therefore, if this exceeds the rated voltage, there is a high possibility of causing element destruction. In order to prevent this, it is necessary to have a wiring structure that reduces the stray inductance to the limit. However, in consideration of fluctuations in the DC voltage of the power conversion circuit, measures with only the wiring structure are often insufficient. . Therefore, various methods for protecting the element from overvoltage have been proposed. A conventional technical example will be described below.
図5に、従来技術の基本回路構成例を示す。この図において、Q2はIGBT、D2はダイオード、ZDはツェナーダイオードやアバランシェダイオードなどの電圧クランプ素子である。このように、IGBTのコレクタ・ゲート間にD2とZDの直列回路(以下、クランプ回路)が接続された構成である。ZDのクランプ電圧値は、IGBTのコレクタ−エミッタ間電圧VCEにおける上限値に設定する。 FIG. 5 shows a basic circuit configuration example of the prior art. In this figure, Q 2 is an IGBT, D 2 is a diode, and ZD is a voltage clamp element such as a Zener diode or an avalanche diode. In this way, a series circuit of D 2 and ZD (hereinafter referred to as a clamp circuit) is connected between the collector and gate of the IGBT. Clamping voltage value ZD, the collector of IGBT - set to the upper limit value in the emitter voltage V CE.
図6に、各部波形例を示す。VGE2はIGBTのゲート・エミッタ間電圧、Iclamp2は電圧クランプ素子ZDやダイオードD2に流れる電流、VCE2はIGBTのコレクタ・エミッタ間電圧、IC2はIGBTのコレクタ電流の波形を示している。点線はクランプ回路が無い場合の波形、実線はクランプ回路がある場合の波形を表している。クランプ回路が無い場合、IGBTがターンオフを開始してVCE2が上昇し、電源電圧に達するとコレクタ電流IC2が減少し始める。この時の電流変化率と回路の浮遊インダクタンスにより、図5のようなサージ電圧が発生する。 FIG. 6 shows an example of the waveform of each part. V GE2 is the IGBT gate-emitter voltage, I clamp2 is the current flowing through the voltage clamp element ZD and diode D 2 , V CE2 is the IGBT collector-emitter voltage, and I C2 is the IGBT collector current waveform . The dotted line represents the waveform when there is no clamp circuit, and the solid line represents the waveform when there is a clamp circuit. When there is no clamp circuit, the IGBT starts to turn off and V CE2 rises. When the power supply voltage is reached, the collector current I C2 starts to decrease. A surge voltage as shown in FIG. 5 is generated by the current change rate and the floating inductance of the circuit.
次にクランプ回路が有る場合、VCEがクランプ電圧に達すると、クランプ回路のZDに電流が流れ、これがIGBTのゲートに流れ込む。この動作により、VGE2は上昇するため素子はオンする方向に動作することからVCE2が減少し始めるが、クランプ電圧を下回ろうとすると、Iclamp2が流れなくなり、再びIGBTがオフ動作になりVCE2が上昇する。この動作を高速で繰り返すことにより、図6に示すようにVCE2を一定値にクランプさせることができる。IC2の遮断が完了すると通常と同様、定常オフの状態になる。このような電圧クランプ素子を用いた方式は、例えば下記の特許文献1に開示されている。 Next, when there is a clamp circuit, when V CE reaches the clamp voltage, a current flows through ZD of the clamp circuit, which flows into the gate of the IGBT. By this operation, V GE2 rises, so the element operates in the direction to turn on, so V CE2 starts to decrease, but if it falls below the clamp voltage, I clamp2 does not flow, IGBT turns off again and V CE2 rises. By repeating this operation at high speed, VCE2 can be clamped to a constant value as shown in FIG. When I C2 is shut off, it is in a steady-off state as usual. A system using such a voltage clamp element is disclosed in, for example, Patent Document 1 below.
従来技術では電圧クランプ素子を用い、さらにこの電圧クランプ素子の電圧を適切に選定することで、任意の設定電圧に素子電圧をクランプさせることができ、あらゆる定格の電圧駆動型半導体素子を過電圧から保護できる。しかし、クランプ動作時において電圧クランプ素子には素子電圧と同様な電圧が印加され、かつ電流も流れる。そのため発生損失が大きく、高い頻度で動作する場合には許容できる特殊品を適用する必要があり、信頼性も低下する。
したがって、この発明の課題は、電圧クランプ素子を用いずに素子の過電圧保護を可能とすることにある。
In the prior art, a voltage clamp element is used, and by selecting the voltage of this voltage clamp element appropriately, the element voltage can be clamped to an arbitrary set voltage, and all rated voltage-driven semiconductor elements are protected from overvoltage. it can. However, during the clamping operation, a voltage similar to the element voltage is applied to the voltage clamping element, and a current also flows. Therefore, the generated loss is large, and when operating at a high frequency, it is necessary to apply an acceptable special product, and the reliability is also lowered.
Accordingly, an object of the present invention is to enable overvoltage protection of an element without using a voltage clamp element.
上述の課題を解決するために、第1の発明においては、電圧駆動型半導体素子のターンオフ時のサージによる過電圧を抑制する回路方式において、可飽和リアクトルと、コンデンサと、抵抗と、の直列回路を前記電圧駆動型半導体素子のコレクタ端子とゲート端子との間に接続する。 In order to solve the above-described problem, in the first invention, in a circuit system that suppresses overvoltage due to a surge at the time of turn-off of a voltage-driven semiconductor element, a series circuit of a saturable reactor, a capacitor, and a resistor is provided. The voltage driven semiconductor element is connected between a collector terminal and a gate terminal.
第2の発明においては、ダイオードを逆並列接続した電圧駆動型半導体素子のダイオード逆回復時のサージによる過電圧を抑制する回路方式において、可飽和リアクトルと、コンデンサと、抵抗と、の直列回路を前記電圧駆動型半導体素子のコレクタ端子とゲート端子との間に接続する。 According to a second aspect of the present invention, in a circuit system for suppressing overvoltage caused by a surge at the time of reverse diode recovery of a voltage-driven semiconductor element in which diodes are connected in antiparallel, a series circuit of a saturable reactor, a capacitor, and a resistor is provided. The voltage-driven semiconductor element is connected between the collector terminal and the gate terminal.
第3の発明においては、前記抵抗は、抵抗値を有する導電性部材で構成する。 In a third invention, the resistor is formed of a conductive member having a resistance value.
本発明では、電圧駆動型半導体素子のコレクタ端子とゲート端子との間に、可飽和リアクトルと、コンデンサと、抵抗との直列回路を接続して、過電圧を抑制するようにしている。その結果、電圧クランプ動作期間の短時間だけ、この回路に電流が流れるだけとなり、電圧駆動型半導体素子のクランプ期間中の損失が大幅に低減できる。また、高い頻度で動作する場合でも損失は小さく、特殊な部品を使用する必要もないため、信頼性が高くなる。 In the present invention, a series circuit of a saturable reactor, a capacitor, and a resistor is connected between the collector terminal and the gate terminal of the voltage-driven semiconductor element so as to suppress overvoltage. As a result, only a current flows through this circuit for a short time during the voltage clamping operation period, and the loss during the clamping period of the voltage-driven semiconductor element can be greatly reduced. Further, even when operating at a high frequency, the loss is small and it is not necessary to use special parts, so that the reliability is increased.
本発明の要点は、電圧駆動型半導体素子のターンオフ時のサージによる過電圧を抑制するために、コレクタ端子とゲート端子間に、可飽和リアクトルと、コンデンサと、抵抗と、の直列回路を接続する点である。 The main point of the present invention is that a series circuit of a saturable reactor, a capacitor, and a resistor is connected between a collector terminal and a gate terminal in order to suppress an overvoltage due to a surge at the time of turn-off of the voltage-driven semiconductor element. It is.
図1に、本発明の第1の実施例の回路構成例を示す。この構成において、L1は可飽和リアクトル、R1は抵抗、C1はコンデンサであり、これらの直列回路をIGBTQ1のコレクタ端子とゲート端子との間に接続している。可飽和リアクトルL1は、例えば図2に示すようなB−H特性(磁束密度−磁界の強さの特性)を持っており、磁界の強さを零から正方向に増加させると、期間aでは磁束密度も増加するが、期間bでは、増加率が大幅に減少し、やがて一定の磁束密度に飽和してしまう。 FIG. 1 shows an example of the circuit configuration of the first embodiment of the present invention. In this configuration, L 1 is a saturable reactor, R 1 is a resistor, C 1 is a capacitor, and these series circuits are connected between the collector terminal and the gate terminal of IGBTQ 1 . The saturable reactor L 1 has, for example, a BH characteristic (magnetic flux density-magnetic field strength characteristic) as shown in FIG. 2. When the magnetic field strength is increased from zero to the positive direction, the period a In this case, the magnetic flux density also increases, but in the period b, the increase rate is greatly reduced and eventually becomes saturated to a constant magnetic flux density.
この特性の傾きはL1の自己インダクタンスに比例しており、期間aではL1の自己インダクタンスを維持している傾向にあるが、期間bでは自己インダクタンス分が非常に小さくなる傾向にあることが判る。 The slope of this characteristic is proportional to the self-inductance of L 1, tend to maintain the self-inductance of the period in a L 1, be self-inductance in the period b is in the very low tendency I understand.
このような可飽和リアクトルをもつ図1の回路構成における各部の波形例を図3に示す。この図において、ターンオフを開始してゲート電圧VGE1が減少し、ゲートしきい値に達すると、VCE1が上昇し始める。すると、IGBTQ1のコレクタ・ゲート間にもVCE1と同様な電圧が印加されるため、Iclamp1電流が流れ始める。図2でも説明したように、B−H特性により期間aでは大きい自己インダクタンス分を有しIclamp1はゆっくりと増加するが、次第に期間bへ移って自己インダクタンス分が減少していくため、Iclamp1が急激に増加するようになる。 FIG. 3 shows a waveform example of each part in the circuit configuration of FIG. 1 having such a saturable reactor. In this figure, the turn-off starts, the gate voltage V GE1 decreases, and when the gate threshold value is reached, V CE1 starts to rise. Then, since the same voltage V CE1 is also applied between the collector and the gate of IGBTQ 1, I clamp1 current starts to flow. As described in FIG. 2, due to the BH characteristic, I clamp1 has a large self-inductance in period a and increases slowly, but gradually shifts to period b and the self-inductance decreases, so I clamp1 Suddenly increases.
この電流はIGBTQ1のゲート部へ流れ込むため、ゲート電圧VGE1は増加傾向となる。よって、IGBTQ1がオンする方向となりVCE1の電圧上昇が抑制される。ターンオフ波形において、電圧をクランプしたいタイミングでIclamp1に電流が流れるように可飽和リアクトルL1のインダクタンス値と飽和特性を設定することにより、所望の動作を得ることができる。 Since this current flows into the gate portion of IGBTQ 1 , the gate voltage V GE1 tends to increase. Therefore, the voltage rise of the V CE1 becomes direction IGBTQ 1 is turned on is prevented. In the turn-off waveform, by setting the saturation characteristic and the inductance value of the saturable reactor L 1 so that a current flows through the I CLAMP1 at the desired timing to clamp the voltage, it is possible to obtain a desired operation.
ここで、コンデンサC1は直流分がこの回路を通して流れることを防止するために接続している。設計方法として、例えばコンデンサC1のインピーダンスはL1のインピーダンスに比べて十分小さく設定することで、Iclamp1の時定数や電流値は可飽和リアクトルL1の値と抵抗R1の値で設定することができる。 Here, the capacitor C 1 is connected to prevent a DC component from flowing through this circuit. As a design method, for example, the impedance of the capacitor C 1 by setting sufficiently smaller than the impedance of L 1, constant or current values when the I CLAMP1 is set by the value of resistor R 1 and the value of the saturable reactor L 1 be able to.
図4に、本発明の第2の実施例の回路構成例を示す。第1の実施例との違いは、IGBTQ1と逆並列に還流用ダイオードが接続されている点であり、その他は第1の実施例と同じである。このような構成で、IGBTQ1のゲートにオン信号が入っている状態で、電流ID1がダイオードD1を流れているモードから、IGBTの信号をオフにして、外部条件でダイオードを逆回復させるモードにおいては、ダイオードD1の両端電圧、即ちIGBTQ1の両端電圧は第1の実施例と同じように、図3に示すような動作となる。 FIG. 4 shows a circuit configuration example of the second embodiment of the present invention. The difference from the first embodiment is that a free-wheeling diode is connected in antiparallel with IGBTQ 1 and the other points are the same as in the first embodiment. In such a configuration, the IGBT is turned off from the mode in which the current I D1 flows through the diode D 1 while the gate of the IGBT Q 1 is turned on, and the diode is reversely recovered under an external condition. in mode, the voltage across the diode D 1, i.e. the voltage across the IGBTQ 1, like the first embodiment, the operation shown in FIG.
即ち、ダイオードの両端電圧が上昇すると、この上昇に応じて、抵抗R1、可飽和リアクトルL1、コンデンサC1の直列回路を通して、電流Iclamp1がIGBTQ1のゲートに流れ込み、ゲート電圧VGE1を上昇させ、IGBTQ1をオンさせる方向となり、VCE1の電圧上昇が抑制される。 That is, when the voltage across the diode rises, the current I clamp1 flows into the gate of IGBTQ 1 through the series circuit of the resistor R 1 , the saturable reactor L 1 , and the capacitor C 1 according to this rise, and the gate voltage V GE1 is raised, becomes the direction to turn on the IGBTQ 1, voltage increase V CE1 is suppressed.
尚、上記実施例には抵抗として電気部品の例を示したが、電気部品に限られず、抵抗値を持った配線材料や導電材料を適用できる。また、可飽和リアクトルの巻線材料への抵抗値を持った導電性材料の適用、等価直列抵抗の大きなコンデンサ部品の適用も可能である。 In addition, although the example of the electrical component was shown as resistance in the said Example, it is not restricted to an electrical component, The wiring material and conductive material which have resistance value can be applied. In addition, it is possible to apply a conductive material having a resistance value to the winding material of the saturable reactor and a capacitor component having a large equivalent series resistance.
Q1、Q2・・・IGBT D1、D2・・ダイオード R1・・・抵抗
L1・・・可飽和リアクトル C1・・・コンデンサ
ZD・・・電圧クランプ素子
Q 1 , Q 2 ... IGBT D 1 , D 2 .. Diode R 1 ... Resistance
L 1 ... Saturable reactor C 1 ... Capacitor ZD ... Voltage clamp element
Claims (3)
The semiconductor protection circuit according to claim 1, wherein the resistor is formed of a conductive member having a resistance value.
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JP2014027789A (en) * | 2012-07-27 | 2014-02-06 | Hitachi Ltd | Power converter |
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JPH06311726A (en) * | 1993-01-14 | 1994-11-04 | Toshiba Corp | Snubber circuit, witching power source and saturable inductor used therefor |
JP2000245137A (en) * | 1999-02-18 | 2000-09-08 | Fuji Electric Co Ltd | Protective device for semiconductor device |
JP2001245466A (en) * | 2000-02-28 | 2001-09-07 | Hitachi Ltd | Electric power converter |
JP2006345666A (en) * | 2005-06-10 | 2006-12-21 | Fuji Electric Fa Components & Systems Co Ltd | Power converter |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH06311726A (en) * | 1993-01-14 | 1994-11-04 | Toshiba Corp | Snubber circuit, witching power source and saturable inductor used therefor |
JP2000245137A (en) * | 1999-02-18 | 2000-09-08 | Fuji Electric Co Ltd | Protective device for semiconductor device |
JP2001245466A (en) * | 2000-02-28 | 2001-09-07 | Hitachi Ltd | Electric power converter |
JP2006345666A (en) * | 2005-06-10 | 2006-12-21 | Fuji Electric Fa Components & Systems Co Ltd | Power converter |
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JP2014027789A (en) * | 2012-07-27 | 2014-02-06 | Hitachi Ltd | Power converter |
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