JP2010178253A - Pulse generator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pulse generator which is suited to efficient generation of a pulse signal having a satisfactory signal level. <P>SOLUTION: The pulse generator 100 includes a delay circuit 10, a buffer circuit 20, and a pulse generating circuit 30. The delay circuit 10 includes M (M is an integer of three or more) inverters I1 to IM connected in cascade. The buffer circuit 20 includes M buffers B1 to BM corresponding to respective delayed signals output from connection portions of the delay circuit 10, and uses the buffers B1 to BM to buffer the delayed signals from the delay circuit 10. The pulse generating circuit 30 includes an N (N is an integer of 1≤N<M) unit pulse generating circuits 31_1 to 31_N. In each unit pulse generating circuit, two or more unit pulse signals of a plurality of unit pulse signal constituting a single pulse signal are generated based on a plurality of delayed signals input via the buffer circuit 20. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a pulse generator suitable for generating a pulse signal having a desired signal level.

In recent years, wireless terminal devices such as mobile phones and wireless LANs have been remarkably spread, and the frequency band used has reached the gigahertz (GHz) band. Therefore, it is difficult to use a new frequency band for communication.
Under such circumstances, a communication method using an impulse-like pulse train having a very narrow pulse width (for example, a pulse train having a pulse width of about 1 [ns]) has been attracting attention as a new method of using frequency resources. As a communication method using such a pulse train, for example, an ultra wide band (UWB) communication method is known. The UWB communication method is described in detail in, for example, Patent Document 1.

In communication systems using these pulse trains, information transmission is performed by intermittent energy transmission / reception, unlike signal transmission using normal continuous waves.
UWB communication is suitable for mobile devices such as mobile phones because it consumes low power and the size of the transceiver can be reduced.
Further, as a conventional pulse generation circuit, for example, there is a pulse generator described in Patent Document 2.
Such a pulse generator is a circuit that generates a pulse signal while the input signal of the delay stage rises or falls.

Japanese National Patent Publication No. 10-508725 JP 2006-229677 A

However, the pulse generation circuit of Patent Document 2 generates a pulse signal that is output by short-circuiting (by wired-OR connection) the outputs of a plurality of unit pulse generation circuits that generate unit pulse signals. ing.
Therefore, as the number of unit pulse generation circuits that generate unit pulse signals increases, the number of circuit elements such as transistors connected to the output node of the unit pulse signal increases, and these become loads (mainly capacitors), There was a problem that the amplitude of the pulse signal was reduced.
Accordingly, the present invention has been made paying attention to such an unsolved problem of the conventional technology, and is suitable for generating a pulse signal having a desired signal level with relatively low power consumption. The object is to provide a generator.

[Mode 1] In order to achieve the above object, the pulse generator of mode 1 is a pulse generator that generates a pulse signal composed of a series of unit pulse signal sequences of a plurality of unit pulse signals,
A delay circuit having a configuration in which first to M-th (M is an integer of 3 or more) delay elements that output an input signal after delay are connected in cascade;
N unit pulse generation circuits (N is an integer of 1 ≦ N <M) for generating the plurality of unit pulse signals based on a delay signal output from the delay element,
The unit pulse generation circuit receives a plurality of delay signals corresponding to a plurality of different delay states in the M delay elements connected in cascade, and has a timing corresponding to each delay state of the input delay signals. And generating two or more unit pulse signals among the plurality of unit pulse signals.

With such a configuration, each unit pulse generation circuit has a unit pulse signal sequence according to delay signals having different delay states output from a plurality of different delay elements among the M delay elements constituting the delay circuit. Two or more unit pulse signals constituting the above are generated.
Here, when the number of unit pulse generation circuits is one (N = 1), this unit pulse generation circuit generates all the plurality of unit pulse signals constituting the unit pulse signal sequence. Two or more pulse generation circuits each generate and share two or more unit pulse signals among a plurality of unit pulse signals constituting a unit pulse signal sequence.

Accordingly, at least the number of unit pulse generation circuits can be halved as compared with the case where a plurality of unit pulse signals constituting the unit pulse signal sequence are generated by the same number of unit pulse generation circuits. .
As a result, when the signal output units of N (particularly, N = 2 or more) unit pulse generation circuits are all connected to a common signal output line by wired-OR, the number of circuits to be connected is reduced. Therefore, the degree of decrease in the amplitude level of the unit pulse signal, which decreases when the remaining unit pulse generation circuit becomes a capacitive load, can be reduced with respect to the unit pulse generation circuit that generates the unit pulse signal. . When N = 1, it is possible to prevent the amplitude level from being lowered due to wired-OR connection.

Here, the “unit pulse generation circuit” is a logic circuit that receives a delayed input signal (delayed signal) and generates an output signal (unit pulse signal) that becomes a high level or a low level by a predetermined logical operation. Consists of
The “unit pulse signal” corresponds to a minimum unit pulse signal forming a unit pulse signal train such as a single cycle monocycle pulse signal.

[Mode 2] Furthermore, the pulse generator of mode 2 is the pulse generator of mode 1, wherein the N unit pulse generation circuits are configured to generate the plurality of unit pulse signals in response to rising and falling of the input signal. Is generated.
With such a configuration, each unit pulse generation circuit generates a unit pulse signal in accordance with both the rising and falling timings of the input signal. In comparison, the input signal can be at a low frequency.
As a result, an increase in power consumption due to higher frequency input signals can be suppressed.

[Mode 3] Further, the pulse generator of mode 3 is the pulse generator of mode 1 or 2, wherein the unit pulse generation circuit performs a logical operation based on the plurality of delay signals to generate the unit pulse signal. A timing signal generator that generates a plurality of logic signals for determining the unit pulse, and a unit pulse signal generator that generates a unit pulse signal by performing a logic operation based on the plurality of logic signals.
With such a configuration, it is possible to control the generation timing of the unit pulse signal and the generation of the unit pulse signal by a logical operation using the delay signal from the delay circuit as an input. A relatively simple configuration can be obtained.

For example, it can be constituted by a logic circuit such as an existing OR circuit or an EXOR circuit, or a logic circuit in which a relatively small number of transistors are combined.
Here, the logic signal is a signal corresponding to “true (1)” and “false (0)” in the logical operation. If the logic signal is positive logic, the high-level signal is “true (1)”, If the low level signal is “false (0)”, and if it is negative logic, the high level signal is “true (0)” and the low level signal is “false (1)”. .

[Mode 4] Furthermore, the pulse generator of mode 4 is the pulse generator of mode 3, wherein the timing signal generation unit includes the delays of two or more different delay elements among the first to Mth delay elements. Two or more logic operation element units that generate the logic signal based on the signal and output the generated logic signal are included.
With such a configuration, the unit pulse signal generation unit generates a unit pulse signal by performing a logical operation on two or more logic signals at timings corresponding to the delay state of the delay signal output from the timing signal generation unit. be able to.

[Mode 5] Furthermore, the pulse generator of mode 5 is the pulse generator of mode 4, wherein the timing signal generator includes the first to fourth logic operation elements.
The unit pulse signal generator is
A P-channel type first field effect transistor having a gate terminal electrically connected to the output portion of the logic signal of the first logic operation element portion and a source terminal connected to a power supply node on a high potential side;
A P-channel type first terminal in which a gate terminal is electrically connected to an output part of the logic signal of the second logic operation element part, and a source terminal is electrically connected to a drain terminal of the first field effect transistor. Two field effect transistors;
An N-channel type first transistor having a gate terminal electrically connected to the output part of the logic signal of the third logic operation element part and a drain terminal electrically connected to the drain terminal of the second field effect transistor. 3 field effect transistors,
The gate terminal is electrically connected to the output part of the logic signal of the fourth logic operation element part, the drain terminal is electrically connected to the source terminal of the third field effect transistor, and the source terminal is low potential An N-channel fourth field effect transistor electrically connected to the power supply node on the side;
And a signal output unit electrically connected to the drain terminal of the second field effect transistor and the drain terminal of the third field effect transistor.

That is, the unit pulse signal generation unit is configured to input the logic signals generated by the first to fourth logic operation element units to the unit pulse signal generation unit including the four field effect transistors. Can generate a unit pulse signal by performing a logical operation on a set of four logic signals input at a timing corresponding to the delay state of the delay signal.
As a result, in the unit pulse generation circuit, two or more unit pulse signals in the plurality of unit pulse signals constituting the pulse signal can be generated.

[Mode 6] Furthermore, the pulse generator of mode 6 is the pulse generator of any one of modes 1 to 5, wherein the delay element is an inverter circuit.
With such a configuration, an input signal can be transmitted from the delay element at the start of the M delay elements connected in cascade to the delay element at the end while being delayed and inverted by each delay circuit. .
Therefore, in the delay circuit, both a signal obtained by delaying the input signal and a signal obtained by inverting and delaying the input signal can be generated. Therefore, the unit pulse generation circuit can easily generate a unit pulse signal having a pulse width corresponding to the delay amount between the delay signals.

[Mode 7] Furthermore, the pulse generator of mode 7 is the pulse generator of any one of modes 1 to 6, based on the delay signal output from the M delay elements connected in cascade in the delay circuit. There are provided N (N is an integer of 1 ≦ N <M) N-phase unit pulse generation circuits that generate unit pulse signals that are 180 ° out of phase with the pulse signals generated by the unit pulse generation circuit.
With such a configuration, it is possible to generate two types of pulse signals that are in a relationship of balanced signals by using the delay signal output from the common delay circuit.

It is a block diagram which shows schematic structure of the pulse generator 100 which concerns on this invention. 2 is a diagram illustrating a circuit configuration example of a delay circuit 10 and a buffer circuit 20. FIG. 2 is a block diagram showing a detailed configuration of a pulse generation circuit 30. FIG. (A) is a block diagram showing a configuration of the unit pulse generation circuit 31, and (b) is a diagram showing a circuit configuration example of a timing signal generation unit 32 (described later). (A) is a figure which shows the terminal structural example of the unit pulse signal generation part 33, (b) is a figure which shows the specific circuit structural example of the unit pulse signal generation part 33, (c) is It is a figure which shows the truth table of the unit pulse signal generation part 33 of the structure of (b). (A) is a block diagram showing a configuration of a unit pulse generation circuit 31 for explaining a signal input / output state, and (b) is a diagram showing a signal transition state of each input / output terminal group. 3 is a timing chart of input / output signals of a unit pulse generation circuit 31. It is a figure which shows the circuit structural example of the pulse generator 100 which is provided with two unit pulse generation circuits, and generates the pulse signal which consists of a unit pulse signal sequence with which four unit pulse signals continued. It is a figure which shows the circuit structure of the pulse generator 100 of the modification 1. It is a figure which shows the circuit structure of the pulse generator 100 of the modification 2. 11 is a timing chart of input / output signals of a unit pulse generation circuit 31_1 shown in FIG. It is a figure which shows the 1st circuit structure of the pulse generator 100 of the modification 3. It is a figure which shows the 2nd circuit structure of the pulse generator 100 of the modification 3. (A)-(c) is a figure which shows the 1st-3rd structural example of the delay circuit 10. FIG. It is a figure which shows the circuit structural example of the inverter I1 which can control delay time.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 to 8 are diagrams showing an embodiment of a pulse generator according to the present invention.
First, a schematic configuration of a pulse generator according to the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing a schematic configuration of a pulse generator 100 according to the present invention.
As shown in FIG. 1, the pulse generator 100 includes a delay circuit 10, a buffer circuit 20, and a pulse generator circuit 30.
The delay circuit 10 is configured by cascading M (M is an integer of 3 or more) inverter elements (delay elements), and has a function of sequentially delaying an input signal by an inverter element (hereinafter simply referred to as an inverter). In addition, a delay signal is output from each connection unit to the buffer circuit 20.

The buffer circuit 20 is a circuit composed of M buffer elements (hereinafter simply referred to as “buffers”) respectively corresponding to the delay signals output from the respective connections of the delay circuit 10, and each inverter of the delay circuit 10. It has a function to make the load between them constant.
The pulse generation circuit 30 generates a pulse signal composed of a pulse signal sequence in which a plurality of unit pulse signals are continuous, based on a plurality of delay signals from the delay circuit 10 input via each buffer of the buffer circuit 20. It has a function.

Next, detailed circuit configurations of the delay circuit 10 and the buffer circuit 20 will be described with reference to FIG.
Here, FIG. 2 is a diagram illustrating a circuit configuration example of the delay circuit 10 and the buffer circuit 20.
As shown in FIG. 2, the delay circuit 10 has a configuration in which M inverters I1 to IM are cascade-connected in the order of I1 to IM with the inverter I1 as a starting end and the inverter IM as a terminating end. Then, in accordance with the input of the start signal D0, D0 is inverted and delayed and transmitted, and the delay signals XD1, D2, XD3,. , XDM is output.

With the above configuration, the signal input to the beginning is transmitted through each circuit while being delayed and inverted by each inverter. When there are an odd number of inverters, the signal is delayed from the terminal by M inverter circuits and the input signal is inverted. Is output.
For example, when a high level signal is viewed as positive logic and a low level signal is viewed as negative logic, and the signal input to the input terminal of the inverter I1 is positive logic, the negative logic is output from the output terminal of the inverter IM. When the input signal is negative logic, positive logic is output from the output terminal of the inverter IM.
If the number of inverters is an even number, a signal having the same logic as the signal input at the start end is output from the end.

  On the other hand, as shown in FIG. 2, the buffer circuit 20 is configured to include M buffers B <b> 1 to BM respectively corresponding to the respective connection portions of the delay circuit 10. The buffers B1 to BM buffer the delayed signals XD1, D2, XD3... XD (M-2), D (M-1), and XDM according to the inputs of the delayed signals XD1 ′, D2 ′. , XD3 ′... XD (M−2) ′, D (M−1) ′, and XDM ′ are output.

Next, a detailed configuration of the pulse generation circuit 30 will be described with reference to FIG.
Here, FIG. 3 is a block diagram showing a detailed configuration of the pulse generation circuit 30.
As shown in FIG. 3, the pulse generation circuit 30 includes unit pulse generation circuits 31_1 to 31_N and a potential adjustment circuit 40. In FIG. 3, for convenience of explanation, two unit pulse generation circuits are shown, but there may be only one configuration.

Each of the unit pulse generation circuits 31_1 to 31_N receives a plurality of delay signals output from each connection portion of the delay circuit 10 through the buffer circuit 20, and corresponds to each delay state of the plurality of delay signals. At the timing, a plurality of unit pulse signals having a pulse width corresponding to the delay time of each delay signal are sequentially generated. A specific circuit configuration will be described later.
Hereinafter, the unit pulse generation circuits 31_1 to 31_N are simply referred to as the unit pulse generation circuit 31 when they are described in common.
The potential adjustment circuit 40 has a function of setting an output potential during a period in which no pulse signal is generated. A specific circuit configuration will be described later.

Next, the configuration of the unit pulse generation circuit 31 will be described with reference to FIG.
4A is a block diagram illustrating a configuration of the unit pulse generation circuit 31, and FIG. 4B is a diagram illustrating a circuit configuration example of a timing signal generation unit 32 (described later).
As shown in FIG. 4, the unit pulse generation circuit 31 receives six different delay signals a to f out of the delay signals XD1 ′ to XDM ′ output via the buffer circuit 20, and receives the input delay signals. A timing signal generation unit 32 that performs logic operations based on a to f and outputs signals (hereinafter referred to as logic signals) A to D of the logic operation results, performs logic operations based on the logic signals A to D, and delays And a unit pulse signal generation unit 33 that generates two unit pulse signals at a timing corresponding to the specific combination of the logic signals A to D that change according to the delay states of the signals a to f.

As shown in FIG. 4B, the timing signal generator 32 is configured to include exclusive OR negation circuits XNOR1 and XNOR2 and exclusive OR circuits XOR1 and XOR2.
The output terminal of the buffer that outputs the delay signal c is electrically connected to one of the two input terminals of XNOR1, and the output terminal of the buffer that outputs the delay signal e is electrically connected to the other input terminal. The output terminal of XNOR1 is electrically connected to the signal input terminal Ain of the unit pulse signal generator 33. When the delay signals c and e are input to the input terminals, the logic signal A corresponding to the negation of the exclusive OR of the delay signals c and e is output.

  Furthermore, the output terminal of the buffer that outputs the delay signal a is electrically connected to one of the two input terminals of XNOR2, and the output terminal of the buffer that outputs the delay signal e is electrically connected to the other input terminal. The output terminal of XNOR2 is electrically connected to the signal input terminal Din of the unit pulse signal generation unit 33. When the delay signals a and e are input to the input terminals, a logic signal D corresponding to the negation of the exclusive OR of the delay signals a and e is output.

  Furthermore, one of the two input terminals of XOR1 is electrically connected to the output terminal of the buffer that outputs the delayed signal b, and the other output terminal is electrically connected to the output terminal of the buffer that outputs the delayed signal f. The output terminal of XOR1 is electrically connected to the signal input terminal Bin of the unit pulse signal generation unit 33. When the delay signals b and f are input to the input terminals, the logic signal B corresponding to the exclusive OR of the delay signals b and f is output.

  Furthermore, the output terminal of the buffer that outputs the delay signal b is electrically connected to one of the two input terminals of the XOR2, and the output terminal of the buffer that outputs the delay signal d is electrically connected to the other input terminal. The output terminal of XOR2 is electrically connected to the signal input terminal Cin of the unit pulse signal generation unit 33. When the delay signals b and d are input to the input terminal, the logic signal C corresponding to the exclusive OR of the delay signals b and d is output.

The unit pulse signal generation unit 33 includes input terminals Ain, Bin, Cin, and Din corresponding to the logic signals A, B, C, and D, respectively, and an output terminal OUT, and the logic signal A to input to each input terminal. It has a function of outputting a signal corresponding to a calculation result obtained by logically calculating D.
The unit pulse signal generation unit 33 has several output states according to the contents of the logic signals A to D. When the unit pulse signal generation unit 33 is in a state of outputting a low level or high level signal, the output signal is a unit pulse. It becomes a signal, and the rest is in a high impedance state.

Next, based on FIG. 5, the detailed structure of the unit pulse signal generation part 33 is demonstrated.
Here, FIG. 5A is a diagram illustrating a terminal configuration example of the unit pulse signal generation unit 33, and FIG. 5B is a diagram illustrating a specific circuit configuration example of the unit pulse signal generation unit 33. (C) is a figure which shows the truth table of the unit pulse signal generation part 33 of the structure of (b).
As shown in FIG. 5A, the unit pulse signal generation unit 33 has the same configuration as the unit pulse signal generation unit 33 in FIG.
As shown in FIG. 5B, the unit pulse signal generation unit 33 of the present embodiment is configured such that the source terminal of PTr1 which is a P-channel field effect transistor is electrically connected to the power supply node of voltage V2, and the drain The terminal is electrically connected to the source terminal of PTr2, which is a P-channel field effect transistor.

Furthermore, the drain terminal of PTr2 is electrically connected to the drain terminal of NTr1, which is an N-channel field effect transistor, and the source terminal of NTr1 is electrically connected to the drain terminal of NTr2, which is an N-channel field effect transistor. The source terminal of NTr2 is electrically connected to the GND node.
Further, an input terminal Ain is formed at the gate terminal of PTr1, an input terminal Bin is formed at the gate terminal of PTr2, an input terminal Cin is formed at the gate terminal of NTr1, and an input terminal Din is formed at the gate terminal of NTr2.
Further, a signal output terminal OUT is formed at a connection portion between the drain terminal of PTr2 and the drain terminal of NTr1.

With the above configuration, when logic signals A to D are input to the input terminals Ain, Bin, Cin, and Din, signals corresponding to the logical operation results shown in the truth table of FIG. In FIG. 5C, L represents a low level, H represents a high level, Z represents a high impedance, and x represents a prohibited setting.
That is, the timing signal generator 32 controls the contents of the logic signals A to D based on the delay signals a to f so that the output of the pulse signal generator 33 changes to L or H at the generation timing of the pulse signal. In other periods, high impedance is set. However, it is necessary to control the logic signals A to D so as not to be in a prohibited setting state.

Hereinafter, the relationship between the signal input / output state of the timing signal generation unit 32 and the signal output state of the pulse signal generation unit 33 will be described more specifically based on FIG. 6.
Here, FIG. 6A is a block diagram showing the configuration of the unit pulse generation circuit 31 for explaining the input / output states of the signals, and FIG. 6B shows the transition states of the signals of the respective input / output terminal groups. FIG.
As shown in FIG. 6A, the unit pulse generation circuit 31 includes a terminal group A and a terminal group B that input a delay signal, and a terminal group X that outputs a logic signal generated based on the input delay signal. A unit pulse signal generation unit that generates a unit pulse signal by performing a logical operation based on a logic signal input via the terminal group X and the timing signal generation unit 32 provided, and outputs the generated unit pulse signal from the output terminal OUT Part 33.

In the present embodiment, the delay signals input to the terminal group A and the terminal group B of the timing signal generation unit 32 have a steady state of A1 and A2, and the logical signals output to the terminal group X include X1 and X2. There is a steady state.
Specifically, the delay signals a to f and the logic signals A to D in the configuration shown in FIGS. 4 and 5 will be described as examples. The steady state shown in the following equations (1) to (6) is obtained. Become.
A1: (a, b, c) = (Low, High, Low) (1)
A2: (a, b, c) = (High, Low, High) (2)
B1: (a, b, c) = (Low, High, Low) (3)
B2: (a, b, c) = (High, Low, High) (4)
X1: (A, B, C, D) = (Low, High, High, Low) (5)
X2: (A, B, C, D) = (High, Low, Low, High) (6)

As shown in FIG. 6B, when the delayed signal of the terminal group A transitions from the steady state A1 to the steady state A2 through the transient state, the delayed signal of the terminal group B maintains the steady state B1, and the terminal group The logic signal of X transitions from the steady state X1 to the steady state X2 through the transient state. On the other hand, the output of the output terminal OUT becomes high impedance in the steady state A1, and the unit pulse signal is output from the output terminal OUT when the signals of the terminal group A and the terminal group X are in the transient state.
Subsequently, the output of the output terminal OUT becomes high impedance in the steady state A2, B1, and X2, the steady state B1 transits to the steady state B2 through the transient state, and the steady state X2 transits to the steady state X1 through the transient state. Then, a unit pulse signal is output from the output terminal OUT in the transient state. Further, the steady state A2 is maintained.

Subsequently, the output of the output terminal OUT becomes high impedance in the steady state A2, B2, and X1, the steady state A2 transits to the steady state A1 through the transient state, and the steady state X1 transits to the steady state X2 through the transient state. Then, a unit pulse signal is output from the output terminal OUT in the transient state. Further, the steady state B2 is maintained.
Thereafter, the above series of flows is repeated.
In consideration of the above, by setting each terminal group and delay signal, a pulse signal generation circuit that generates a desired number of unit pulse signals at a desired timing can be configured.

Next, based on FIG. 7, a unit pulse configured to include a timing signal generating unit 32 having the circuit configuration of FIG. 4B and a unit pulse signal generating unit 33 having the circuit configuration of FIG. The operation of the generation circuit 31 will be described.
Here, FIG. 7 is a timing chart of the input / output signals of the unit pulse generation circuit 31.
Hereinafter, the delay signals a to f will be described as outputs XD1 ′, D2 ′, XD3 ′, XD5 ′, D6 ′, and XD7 ′ from the delay circuit 10 and the buffer circuit 20 shown in the upper diagram of FIG.
As shown in FIG. 7, when the activation start signal D0 input to the inverter I1 of the delay circuit 10 changes from the low level to the high level, XD1 ′, D2 ′, XD3 ′, XD5 ′, D6 ′ is triggered by this. , XD7 ′ change in this order.

  First, when XD1 ′ changes from the high level to the low level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din are “L”, “H”, and “H”. , “L” to “L”, “H”, “H”, “H”. When the logic signals A to D corresponding to “L”, “H”, “H”, and “H” are input to the unit pulse signal generation unit 33, as shown in FIG. As a part, a low level signal is output from the output terminal OUT.

Subsequently, when D2 ′ changes from the low level to the high level, the logic signals A, B, C, D input to the input terminals Ain, Bin, Cin, Din are “L”, “H”, “H”. , “H” to “L”, “L”, “L”, “H”. When the logic signals A to D corresponding to “L”, “L”, “L”, and “H” are input to the unit pulse signal generation unit 33, as shown in FIG. As a part, a high level signal is output from the output terminal OUT.
Subsequently, when XD3 ′ changes from the high level to the low level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din are “L”, “L”, and “L”. , “H” to “H”, “L”, “L”, “H”. When the logic signals A to D corresponding to “H”, “L”, “L”, and “H” are input to the unit pulse signal generation unit 33, the output of the output terminal OUT is high as shown in FIG. Impedance.

  Subsequently, when D4 ′ changes from the low level to the high level and XD5 ′ changes from the high level to the low level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din. Changes from “H”, “L”, “L”, “H” to “H”, “L”, “H”, “H”. When the logic signals A to D corresponding to “H”, “L”, “H”, and “H” are input to the unit pulse signal generation unit 33, as shown in FIG. As a part, a low level signal is output from the output terminal OUT.

  Subsequently, when D6 ′ changes from the low level to the high level, the logic signals A, B, C, D input to the input terminals Ain, Bin, Cin, Din are “H”, “L”, “H”. , “H” to “L”, “L”, “H”, “L”. When the logic signals A to D corresponding to “L”, “L”, “H”, “L” are input to the unit pulse signal generation unit 33, as shown in FIG. As a part, a high level signal is output from the output terminal OUT.

Subsequently, when XD7 ′ changes from the high level to the low level, the logic signals A, B, C, D input to the input terminals Ain, Bin, Cin, Din are “L”, “L”, “H”. , “L” to “L”, “H”, “H”, “L”. When the logic signals A to D corresponding to “L”, “H”, “H”, and “L” are input to the unit pulse signal generation unit 33, the output from the output terminal OUT is as shown in FIG. High impedance.
Thereafter, the delay signals a to f are constant at a high level or a low level, and the output of the output terminal OUT becomes a high impedance while the activation start signal D0 is at a high level.
That is, the unit pulse signal is output twice consecutively from the unit pulse generation circuit 31 in response to the rise of the start signal D0.

Subsequently, when the activation start signal D0 changes from the high level to the low level, XD1 ′, D2 ′, XD3 ′, XD5 ′, D6 ′, and XD7 ′ change again in this order.
As in the case where the start signal D0 changes from the low level to the high level, first, when XD1 ′ changes from the low level to the high level, the signals are input to the input terminals Ain, Bin, Cin, Din. The logic signals A, B, C, D to be changed from “L”, “H”, “H”, “L” to “L”, “H”, “H”, “H”. When the logic signals A to D corresponding to “L”, “H”, “H”, and “H” are input to the unit pulse signal generation unit 33, as shown in FIG. As a part, a low level signal is output from the output terminal OUT.

Thereafter, similarly to the case where the activation start signal D0 changes from the low level to the high level, the logic signals A to D change according to the change of the delay signal, and the unit pulse signal is generated.
That is, the unit pulse signal is output from the unit pulse generation circuit 31 twice in succession in response to the fall of the start signal D0.
As described above, the unit pulse generation circuit 31 including the timing signal generation unit 32 having the circuit configuration of FIG. 4B and the unit pulse signal generation unit 33 having the circuit configuration of FIG. A unit pulse signal is generated twice in succession at the rise and fall of D0.

Next, a specific circuit configuration example of the pulse generator 100 will be described with reference to FIG.
Here, FIG. 8 is a diagram showing a circuit configuration example of a pulse generation device 100 that includes two unit pulse generation circuits and generates a pulse signal composed of a unit pulse signal sequence in which four unit pulse signals are continuous. In FIG. 8, there is a part in which connection is omitted in order to avoid making the drawing difficult to see, but in actuality, it is electrically connected to a buffer that outputs a corresponding delay signal.
As shown in FIG. 8, the pulse generator 100 includes a delay circuit 10 including inverters I1 to I9, a buffer circuit 20 including buffers B1 to B9, and unit pulse generators 31_1 to 31_2. And a potential adjusting circuit 40 including NTr3 and NTr4 which are N-channel field effect transistors.

The delay circuit 10 is configured by cascading an output terminal of a younger inverter and an input terminal of an inverter of the next number in descending order, starting from the inverter I1 and ending with the inverter I9.
With this configuration, the signal input to the start end is transmitted through each circuit while being delayed and inverted by each inverter, and since there are an odd number of inverters, the signal is delayed by nine inverters from the end and the input signal is inverted. Is output.
The buffer circuit 20 is configured to include buffers B1 to B9 in which input terminals are electrically connected to the output terminals of the inverters I1 to I9 by the same numbers as these.

With this configuration, the delay signals XD1, D2, XD3, D4, XD5, D6, XD7, D8, and XD9 that are input to the input terminals of the buffers B1 to B9 have the same load level, so that the amplitude level of each delay signal Further, the time width becomes uniform, and delayed signals XD1 ′, D2 ′, XD3 ′, D4 ′, XD5 ′, D6 ′, XD7 ′, D8 ′, and XD9 ′ are output from the output terminals of the buffers B1 to B9.
The unit pulse generation circuit 31_1 includes a timing signal generation unit 32_1 and a unit pulse signal generation unit 33_1.
One input terminal of the two input terminals of the XNOR1 of the timing signal generation unit 32_1 is electrically connected to the output terminal of the buffer B2, the other input terminal is electrically connected to the output terminal of the buffer B6, and the output terminal is The unit pulse signal generator 33_1 is electrically connected to the gate terminal (input terminal Ain) of PTr1.

One input terminal of the two input terminals of the XOR1 of the timing signal generation unit 32_1 is electrically connected to the output terminal of the buffer B2, the other input terminal is electrically connected to the output terminal of the buffer B7, and the output terminal is The unit pulse signal generator 33_1 is electrically connected to the gate terminal (input terminal Bin) of PTr2.
One input terminal of the two input terminals of the XOR2 of the timing signal generation unit 32_1 is electrically connected to the output terminal of the buffer B2, the other input terminal is electrically connected to the output terminal of the buffer B5, and the output terminal is The unit pulse signal generator 33_1 is electrically connected to the gate terminal (input terminal Cin) of NTr1.

One input terminal of the two input terminals of the XNOR2 of the timing signal generator 32_1 is electrically connected to the output terminal of the buffer B1, the other input terminal is electrically connected to the output terminal of the buffer B6, and the output terminal is The unit pulse signal generator 33_1 is electrically connected to the gate terminal (input terminal Din) of NTr2.
The unit pulse generation circuit 31_2 includes a timing signal generation unit 32_2 and a unit pulse signal generation unit 33_2.
One input terminal of the two input terminals of the XNOR1 of the timing signal generator 32_2 is electrically connected to the output terminal of the buffer B5, the other input terminal is electrically connected to the output terminal of the buffer B8, and the output terminal is The unit pulse signal generator 33_2 is electrically connected to the gate terminal (input terminal Ain) of PTr1.

One input terminal of the two input terminals of the XOR1 of the timing signal generator 32_2 is electrically connected to the output terminal of the buffer B4, the other input terminal is electrically connected to the output terminal of the buffer B9, and the output terminal is The unit pulse signal generator 33_2 is electrically connected to the gate terminal (input terminal Bin) of PTr2.
One input terminal of the two input terminals of the XOR2 of the timing signal generation unit 32_2 is electrically connected to the output terminal of the buffer B4, the other input terminal is electrically connected to the output terminal of the buffer B7, and the output terminal is The unit pulse signal generator 33_2 is electrically connected to the gate terminal (input terminal Cin) of NTr1.

One input terminal of the two input terminals of the XNOR2 of the timing signal generator 32_2 is electrically connected to the output terminal of the buffer B3, the other input terminal is electrically connected to the output terminal of the buffer B6, and the output terminal is The unit pulse signal generator 33_2 is electrically connected to the gate terminal (input terminal Din) of NTr2.
In the potential adjustment circuit 40, the drain terminal of NTr3 is electrically connected to the output terminals of the unit pulse signal generators 33_1 and 33_2, the source terminal is electrically connected to the drain terminal of NTr4, and the source terminal of NTr4 is potential V1. It is electrically connected to the power supply node (GND potential in this embodiment).
Furthermore, the gate terminal of NTr3 is electrically connected to the output terminal of buffer B9, and the gate terminal of NTr4 is electrically connected to the output terminal of buffer B1.
Further, an output terminal Pout for a pulse signal is formed at the drain terminal of NTr3.

Next, a specific operation of the pulse generator 100 having the circuit configuration shown in FIG. 8 will be described.
First, when the start signal D0 input to the inverter I1 of the delay circuit 10 changes from the low level to the high level, the XD1 ′ changes from the high level to the low level. First, a unit pulse signal is generated. The logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit 33_1 are changed from “L”, “H”, “H”, and “L” to “L” and “H”. , “H”, “H”. When logic signals A to D corresponding to “L”, “H”, “H”, and “H” are input to the unit pulse signal generation unit 33_1, the first unit pulse signal of the unit pulse signal generation unit 33_1 is input. As a part, a low level signal is output from the output terminal OUT.

Subsequently, when D2 ′ changes from the low level to the high level, the logic signals A, B, C, D input to the input terminals Ain, Bin, Cin, Din are “L”, “H”, “H”. , “H” to “L”, “L”, “L”, “H”. When logic signals A to D corresponding to “L”, “L”, “L”, and “H” are input to the unit pulse signal generation unit 33_1, the first unit pulse signal of the unit pulse signal generation unit 33_1 is input. As a part, a high level signal is output from its output terminal OUT.
The logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_2 in the unit pulse signal generation period of the first unit pulse generation circuit 31_1 are as follows. Since “H”, “L”, “L”, and “H” remain unchanged, the output becomes high impedance.

Subsequently, when XD3 ′ changes from the high level to the low level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_2 become “L”. ”,“ H ”,“ H ”,“ L ”to“ L ”,“ H ”,“ H ”,“ H ”. When logic signals A to D corresponding to “L”, “H”, “H”, and “H” are input to the unit pulse signal generation unit 33_2, the first unit pulse signal of the unit pulse signal generation unit 33_2 is output. As a part, a low level signal is output from the output terminal OUT.
On the other hand, when XD3 ′ changes from the high level to the low level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_1 are “H”. ”,“ L ”,“ L ”,“ H ”, but the output is high impedance.

Subsequently, when D4 ′ changes from the low level to the high level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_2 become “L”. ”,“ H ”,“ H ”,“ H ”to“ L ”,“ L ”,“ L ”,“ H ”. When logic signals A to D corresponding to “L”, “L”, “L”, and “H” are input to the unit pulse signal generation unit 33_2, the first unit pulse signal of the unit pulse signal generation unit 33_2 is output. As a part, a high level signal is output from its output terminal OUT.
The logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generator 33_1 during the first unit pulse signal generation period of the unit pulse generator 31_2 are as follows. Since “H”, “L”, “L”, and “H” remain unchanged, the output is high impedance.

Subsequently, when XD5 ′ changes from the high level to the low level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_2 become “L”. ”,“ L ”,“ L ”,“ H ”to“ H ”,“ L ”,“ L ”,“ H ”. When the logic signals A to D corresponding to “H”, “L”, “L”, and “H” are input to the unit pulse signal generation unit 33_2, the output becomes high impedance.
Further, when XD5 ′ changes from the high level to the low level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_1 are “H”. ”,“ L ”,“ L ”,“ H ”to“ H ”,“ L ”,“ H ”,“ H ”. When logic signals A to D corresponding to “H”, “L”, “H”, and “H” are input to the unit pulse signal generation unit 33_1, the second unit pulse signal of the unit pulse signal generation unit 33_1 is input. As a part, a low level signal is output from the output terminal OUT.

Subsequently, as D6 ′ changes from the low level to the high level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_1 are “H”. ”,“ L ”,“ H ”,“ H ”to“ L ”,“ L ”,“ H ”,“ L ”. When logic signals A to D corresponding to “L”, “L”, “H”, and “L” are input to the unit pulse signal generation unit 33_1, the second unit pulse signal of the unit pulse signal generation unit 33_1 is input. As a part, a high level signal is output from its output terminal OUT.
The logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generator 33_2 in the second unit pulse signal generation period of the unit pulse generator 31_1 are as follows. Since “H”, “L”, “L”, and “H” remain unchanged, the output becomes high impedance.

Subsequently, when XD7 ′ changes from the high level to the low level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_1 become “L”. ”,“ L ”,“ H ”,“ L ”to“ L ”,“ H ”,“ H ”,“ L ”. When the logic signals A to D corresponding to “L”, “H”, “H”, and “L” are input to the unit pulse signal generation unit 33_1, the output becomes high impedance.
On the other hand, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_2 change to “H” when XD7 ′ changes from the high level to the low level. ”,“ L ”,“ L ”,“ H ”to“ H ”,“ L ”,“ H ”,“ H ”. When logic signals A to D corresponding to “H”, “L”, “H”, “H” are input to the unit pulse signal generation unit 33_2, the second unit pulse signal of the unit pulse signal generation unit 33_2 is output. As a part, a low level signal is output from the output terminal OUT.

Subsequently, when D8 ′ changes from the low level to the high level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_2 become “H”. ”,“ L ”,“ H ”,“ H ”to“ L ”,“ L ”,“ H ”,“ L ”. When logic signals A to D corresponding to “L”, “L”, “H”, and “L” are input to the unit pulse signal generation unit 33_2, the second unit pulse signal of the unit pulse signal generation unit 33_2 is output. As a part, a high level signal is output from its output terminal OUT.
The logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_2 in the generation period of the second unit pulse signal of the unit pulse generation circuit 31_2 are as follows. Since “L”, “H”, “H”, and “L” remain unchanged, the output is high impedance.

Subsequently, when XD9 ′ changes from the high level to the low level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_2 become “L”. ”,“ L ”,“ H ”,“ L ”to“ L ”,“ H ”,“ H ”,“ L ”. When the logic signals A to D corresponding to “L”, “H”, “H”, and “L” are input to the unit pulse signal generation unit 33_2, the output becomes high impedance.
In this state, when the activation start signal D0 changes from the high level to the low level, the logic signals A to D change as in the series of processes, and the unit pulse signal generation unit 33_1 → unit pulse signal generation unit 33_2 → unit. Each unit pulse signal is generated twice in the order of pulse signal generator 33_1 → unit pulse signal generator 33_2.

On the other hand, when XD1 ′ is “H” and XD9 ′ is “H”, the potential adjustment circuit 40 turns on NTr3 and NTr4 and drops the output potential to “V1”, that is, the GND potential. However, when the activation start signal D0 rises, XD1 ′ becomes “L”. Therefore, during the generation period of the pulse signal, NTr3 is turned off and the output terminal Pout is not dropped to the GND potential.
Similarly, when the start start signal D0 changes from the high level to the low level from the above state, since XD9 ′ is “L”, NTr3 is turned on in the generation period of the next pulse signal. However, NTr4 is turned off, and the output terminal Pout is not dropped to the GND potential.
Therefore, as shown in FIG. 8, a pulse signal having a configuration in which four unit pulse signals are continuous is generated once in response to the rising edge of the start signal D0 and once in response to the falling edge.

  As described above, in the pulse generator 100 according to the present embodiment, in the unit pulse generator circuit 31, the delay state of these delay signals is changed based on a plurality of types of delay signals from a plurality of cascade-connected inverters constituting the delay circuit 10. It is possible to generate a logic signal that changes in response, and to generate two or more unit pulse signals among a plurality of unit pulse signals constituting one pulse signal based on the logic signal.

This makes it possible to at least halve the number of unit pulse generation circuits compared to the case where a plurality of unit pulse signals constituting one pulse signal are generated by the same number of unit pulse generation circuits. it can.
In addition, since the number of circuits can be reduced, the number of circuits connected to a common signal output line by wired-OR can be reduced. It is possible to reduce the degree of decrease in the amplitude level of the unit pulse signal, which decreases when the unit pulse generation circuit of FIG.

[Modification 1]
Next, a first modification of the embodiment of the present invention will be described with reference to the drawings. FIG. 9 is a diagram showing a first modification of the embodiment of the pulse generator according to the present invention.
In the above embodiment, as shown in FIG. 8, the two output terminals of the unit pulse generation circuits 31_1 and 31_2 are wired-OR connected, and each unit pulse generation circuit generates two unit pulses each when generating one pulse signal. The configuration is such that the signals are alternately generated one by one in turn. However, the present invention is not limited to this configuration, and the number of unit pulse generation circuits may be three or more, or each unit pulse generation circuit may have one pulse signal. The number of unit pulses generated with respect to the above may be three or more.

Hereinafter, as a first modification of the above-described embodiment, as illustrated in FIG. 9, the configuration of the pulse generator 100 is the same as that of the pulse generator 100 of FIG. In addition, an example in which buffers B10 to B13 are added to the buffer circuit 20, a unit pulse generation circuit 31_3 is added, and three unit pulse generation circuits are provided will be described.
Note that the same components as those in the above embodiment are denoted by the same reference numerals, description thereof will be omitted as appropriate, and different portions will be described in detail.
First, the circuit configuration of the pulse generator 100 according to the first modification will be described with reference to FIG.
Here, FIG. 9 is a diagram showing a circuit configuration of the pulse generator 100 of the first modification. In FIG. 9, there is a part in which connection is omitted in order to avoid making the drawing difficult to see, but in actuality, it is electrically connected to a buffer that outputs a corresponding delay signal.

As shown in FIG. 9, the pulse generator 100 of the first modification includes a delay circuit 10 including inverters I1 to I13, a buffer circuit 20 including buffers B1 to B13, and unit pulse generation. The circuit includes a circuit 31_1 to 31_3 and a potential adjustment circuit 40 including NTr3 to NTr5 and PTr3.
The delay circuit 10 is configured by cascading a lower output terminal and an input terminal of the next number in descending order of numbers, with the inverter I1 as the start and the inverter I13 as the end.
The buffer circuit 20 is configured to include buffers B1 to B13 in which input terminals are electrically connected to the output terminals of the inverters I1 to I13 by the same numbers as these.
The unit pulse generation circuit 31_3 includes a timing signal generation unit 32_3 and a unit pulse signal generation unit 33_3.

One input terminal of the two input terminals of the XNOR1 of the timing signal generator 32_1 is electrically connected to the output terminal of the buffer B3, the other input terminal is electrically connected to the output terminal of the buffer B8, and the output terminal is The unit pulse signal generator 33_1 is electrically connected to the input terminal Ain.
One input terminal of the two input terminals of the XOR1 of the timing signal generation unit 32_1 is electrically connected to the output terminal of the buffer B2, the other input terminal is electrically connected to the output terminal of the buffer B9, and the output terminal is The unit pulse signal generator 33_1 is electrically connected to the input terminal Bin.

One input terminal of the two input terminals of the XOR2 of the timing signal generation unit 32_1 is electrically connected to the output terminal of the buffer B2, the other input terminal is electrically connected to the output terminal of the buffer B7, and the output terminal is The unit pulse signal generator 33_1 is electrically connected to the input terminal Cin.
One input terminal of the two input terminals of the XNOR2 of the timing signal generator 32_1 is electrically connected to the output terminal of the buffer B1, the other input terminal is electrically connected to the output terminal of the buffer B8, and the output terminal is The unit pulse signal generator 33_1 is electrically connected to the input terminal Din.

One input terminal of the two input terminals of the XNOR1 of the timing signal generator 32_2 is electrically connected to the output terminal of the buffer B5, the other input terminal is electrically connected to the output terminal of the buffer B10, and the output terminal is The unit pulse signal generator 33_2 is electrically connected to the input terminal Ain.
One input terminal of the two input terminals of the XOR1 of the timing signal generator 32_2 is electrically connected to the output terminal of the buffer B4, the other input terminal is electrically connected to the output terminal of the buffer B11, and the output terminal is The unit pulse signal generator 33_2 is electrically connected to the input terminal Bin.

One input terminal of the two input terminals of the XOR2 of the timing signal generator 32_2 is electrically connected to the output terminal of the buffer B4, the other input terminal is electrically connected to the output terminal of the buffer B9, and the output terminal is The unit pulse signal generator 33_2 is electrically connected to the input terminal Cin.
One input terminal of two input terminals of XNOR2 of the timing signal generation unit 32_2 is electrically connected to the output terminal of the buffer B3, the other input terminal is electrically connected to the output terminal of the buffer B10, and the output terminal is The unit pulse signal generator 33_2 is electrically connected to the input terminal Din.

One input terminal of two input terminals of XNOR1 of the timing signal generation unit 32_3 is electrically connected to the output terminal of the buffer B7, the other input terminal is electrically connected to the output terminal of the buffer B12, and the output terminal is The unit pulse signal generator 33_3 is electrically connected to the input terminal Ain.
One input terminal of the two input terminals of the XOR1 of the timing signal generator 32_3 is electrically connected to the output terminal of the buffer B6, the other input terminal is electrically connected to the output terminal of the buffer B13, and the output terminal is The unit pulse signal generator 33_3 is electrically connected to the input terminal Bin.

One input terminal of the two input terminals of the XOR2 of the timing signal generator 32_3 is electrically connected to the output terminal of the buffer B6, the other input terminal is electrically connected to the output terminal of the buffer B11, and the output terminal is The unit pulse signal generator 33_3 is electrically connected to the input terminal Cin.
One input terminal of the two input terminals of XNOR2 of the timing signal generator 32_3 is electrically connected to the output terminal of the buffer B5, the other input terminal is electrically connected to the output terminal of the buffer B12, and the output terminal is The unit pulse signal generator 33_3 is electrically connected to the input terminal Din.
The potential adjustment circuit 40 includes NTr3 to NTr5, which are N channel type MOS transistors, and PTr3, which is a P channel type MOS transistor.

Specifically, the drain terminal of NTr3 is electrically connected to the output terminal OUT and output terminal Pout of the unit pulse generation circuits 31_1 to 31_3, the source terminal is electrically connected to the drain terminal of NTr4, and the source terminal of NTr4 is It is electrically connected to the GND node.
Further, the gate terminal of NTr3 is electrically connected to the output terminal of the buffer B13 of the buffer circuit 20, and the gate terminal of NTr4 is electrically connected to the output terminal of the buffer B1 of the buffer circuit 20.
Furthermore, the source terminal of PTr3 is electrically connected to the power supply node of voltage V2, the drain terminal is electrically connected to the drain terminal of NTr5, and the source terminal of NTr5 is electrically connected to the GND node.

Furthermore, the source terminal of NTr3, the gate terminals of NTr5 and PTr3, and the drain terminals of NTr5 and PTr3 are electrically connected.
With the above configuration, NTr3 and NTr4 are turned on when both signals input to the gate terminals are at a high level, connect the output terminal Pout to the GND level, and are turned off at other times. As a result, the output potential during a period in which no pulse signal is generated can be set. In the present embodiment, the GND level (ground potential) that is the most stable potential is set, but other potentials may be set as long as the potential is lower than V2.
The transistors PTr3 and NTr5 form a push-pull circuit, and output an output signal corresponding to the level of the input signal (unit pulse signal).
Other configurations are the same as those of the pulse generator 100 shown in FIG. 8 of the above embodiment.

Next, a specific operation of the pulse generator 100 having the circuit configuration shown in FIG. 9 will be described.
Since the operation is the same as that of the pulse generator 100 shown in FIG. 8 in the above embodiment until the change of D4 ′, the operation after the change of XD5 ′ will be described below.
When XD5 ′ changes from the high level to the low level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_3 are “L”, It changes from “H”, “H”, “L” to “L”, “H”, “H”, “H”. When logic signals A to D corresponding to “L”, “H”, “H”, and “H” are input to the unit pulse signal generation unit 33_3, the first unit pulse signal of the unit pulse signal generation unit 33_3 As a part, a low level signal is output from the output terminal OUT.

  Further, when XD5 ′ changes from the high level to the low level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_2 are “L”. ”,“ L ”,“ L ”,“ H ”to“ H ”,“ L ”,“ L ”,“ H ”. When the logic signals A to D corresponding to “H”, “L”, “L”, and “H” are input to the unit pulse signal generation unit 33_1, the output becomes high impedance.

  Subsequently, as D6 ′ changes from the low level to the high level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_3 become “L ”,“ H ”,“ H ”,“ H ”to“ L ”,“ L ”,“ L ”,“ H ”. When logic signals A to D corresponding to “L”, “L”, “L”, “H” are input to the unit pulse signal generation unit 33_3, the first unit pulse signal of the unit pulse signal generation unit 33_3 As a part, a high level signal is output from its output terminal OUT.

Note that the output of the unit pulse signal generators 32_1 to 32_2 becomes high impedance during the first unit pulse signal generation period of the unit pulse generation circuit 31_3.
Subsequently, when XD7 ′ changes from the high level to the low level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_3 become “L”. ”,“ L ”,“ L ”,“ H ”to“ H ”,“ L ”,“ L ”,“ H ”. When the logic signals A to D corresponding to “H”, “L”, “L”, and “H” are input to the unit pulse signal generation unit 33_3, the output becomes high impedance.

  On the other hand, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_1 change to “H” when XD7 ′ changes from the high level to the low level. ”,“ L ”,“ L ”,“ H ”to“ H ”,“ L ”,“ H ”,“ H ”. When logic signals A to D corresponding to “H”, “L”, “H”, and “H” are input to the unit pulse signal generation unit 33_1, the second unit pulse signal of the unit pulse signal generation unit 33_1 is input. As a part, a low level signal is output from the output terminal OUT.

Subsequently, when D8 ′ changes from the low level to the high level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_1 become “H”. ”,“ L ”,“ H ”,“ H ”to“ L ”,“ L ”,“ H ”,“ L ”. When logic signals A to D corresponding to “L”, “L”, “H”, and “L” are input to the unit pulse signal generation unit 33_1, the second unit pulse signal of the unit pulse signal generation unit 33_1 is input. As a part, a high level signal is output from its output terminal OUT.
Note that the output of the unit pulse signal generators 33_2 to 32_3 becomes high impedance during the second unit pulse signal generation period of the unit pulse generation circuit 31_1.

  Subsequently, when XD9 ′ changes from the high level to the low level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_2 are changed to “H”. ”,“ L ”,“ L ”,“ H ”to“ H ”,“ L ”,“ H ”,“ H ”. When logic signals A to D corresponding to “L”, “H”, “H”, and “L” are input to the unit pulse signal generation unit 33_2, the second unit pulse signal of the unit pulse signal generation unit 33_2 is output. As a part, a low level signal is output from the output terminal OUT.

Subsequently, as D10 ′ changes from the low level to the high level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_2 become “H”. ”,“ L ”,“ H ”,“ H ”to“ L ”,“ L ”,“ H ”,“ L ”. When logic signals A to D corresponding to “L”, “L”, “H”, and “L” are input to the unit pulse signal generation unit 33_2, the second unit pulse signal of the unit pulse signal generation unit 33_3 is output. As a part, a high level signal is output from its output terminal OUT.
Note that the output of the unit pulse signal generators 33_1 and 33_3 becomes high impedance during the second unit pulse signal generation period of the unit pulse generation circuit 31_2.

  Subsequently, when XD11 ′ changes from the high level to the low level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_2 become “L”. ”,“ L ”,“ H ”,“ L ”to“ L ”,“ H ”,“ H ”,“ L ”. When the logic signals A to D corresponding to “L”, “H”, “H”, and “L” are input to the unit pulse signal generation unit 33_2, the output becomes high impedance.

  On the other hand, when XD11 ′ changes from the high level to the low level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_3 become “H”. ”,“ L ”,“ L ”,“ H ”to“ H ”,“ L ”,“ H ”,“ H ”. When logic signals A to D corresponding to “H”, “L”, “H”, and “H” are input to the unit pulse signal generation unit 33_3, the second unit pulse signal of the unit pulse signal generation unit 33_3 As a part, a low level signal is output from the output terminal OUT.

  Subsequently, as D12 ′ changes from the low level to the high level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_3 are changed to “H”. ”,“ L ”,“ H ”,“ H ”to“ L ”,“ L ”,“ H ”,“ L ”. When logic signals A to D corresponding to “L”, “L”, “H”, and “L” are input to the unit pulse signal generation unit 33_3, the second unit pulse signal of the unit pulse signal generation unit 33_3 As a part, a high level signal is output from its output terminal OUT.

Note that the output of the unit pulse signal generators 33_1 to 32_2 becomes high impedance during the second unit pulse signal generation period of the unit pulse generation circuit 31_3.
Subsequently, when XD13 ′ changes from the high level to the low level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_3 become “L”. ”,“ L ”,“ H ”,“ L ”to“ L ”,“ H ”,“ H ”,“ L ”. When the logic signals A to D corresponding to “L”, “H”, “H”, and “L” are input to the unit pulse signal generation unit 33_3, the output becomes high impedance.

  In this state, when the activation start signal D0 changes from the high level to the low level, the logic signals A to D change as in the series of processes, and the unit pulse signal generation unit 33_1 → unit pulse signal generation unit 33_2 → unit. Each unit pulse signal is generated twice in the order of pulse signal generation unit 33_3 → unit pulse signal generation unit 33_1 → unit pulse signal generation unit 33_2 → unit pulse signal generation unit 33_3.

On the other hand, when XD1 ′ is “H” and XD13 ′ is “H”, the potential adjustment circuit 40 turns on NTr3 and NTr4 and drops the output potential to the GND potential. However, when the activation start signal D0 rises, XD1 ′ becomes “L”. Therefore, during the generation period of the pulse signal, NTr3 is turned off and the output terminal Pout is not dropped to the GND potential.
Similarly, when the start start signal D0 changes from the high level to the low level from the above state, since XD13 ′ is “L”, NTr3 is turned on in the generation period of the next pulse signal. However, NTr4 is turned off, and the output terminal Pout is not dropped to the GND potential.

Therefore, as shown in FIG. 9, a pulse signal having a structure in which six unit pulse signals are continuous is generated once in response to the rising edge of the start signal D0 and once in response to the falling edge.
As described above, in the pulse generator 100 according to the first modification, in the unit pulse generation circuits 31_1 to 31_3, each of these delays is based on a plurality of types of delay signals from a plurality of cascaded inverters constituting the delay circuit 10. It is possible to generate a logic signal that changes according to the delay state of the signal, and generate two unit pulse signals each of six unit pulse signals that constitute one pulse signal based on the logic signal. .

As a result, the number of unit pulse generation circuits can be halved compared to the case where six unit pulse signals constituting one pulse signal are generated by the same number of unit pulse generation circuits. .
In addition, since the number of circuits can be reduced, the number of circuits connected to a common signal output line by wired-OR can be reduced. It is possible to reduce the degree of decrease in the amplitude level of the unit pulse signal, which decreases when the unit pulse generation circuit of FIG.

[Modification 2]
Next, a second modification of the embodiment of the present invention will be described with reference to the drawings. FIGS. 10-11 is a figure which shows the modification 2 of embodiment of the pulse generator which concerns on this invention.
In the above embodiment and the first modification, a plurality of unit pulse signals constituting one pulse signal are generated and shared by a plurality of unit pulse generation circuits. However, in this modification, one unit pulse is generated. The difference is that the circuit generates all of a plurality of unit pulse signals constituting one pulse signal.

Hereinafter, as a second modification of the above-described embodiment, as illustrated in FIG. 10, the configuration of the pulse generator 100 is configured such that one unit pulse generation circuit 31 generates a pulse signal composed of four unit pulse signals. This will be described as an example.
Note that the same components as those in the above embodiment are denoted by the same reference numerals, description thereof will be omitted as appropriate, and different portions will be described in detail.
First, the circuit configuration of the pulse generator 100 of the second modification will be described with reference to FIG.
Here, FIG. 10 is a diagram illustrating a circuit configuration of the pulse generator 100 according to the second modification. In FIG. 10, the connection between the output terminal of the buffer and the signal input terminal of the timing signal generator 32_1 is omitted in order to avoid making the drawing difficult to see, but these input terminals are actually corresponding delays. It is electrically connected to an output terminal of a buffer that outputs a signal.

As shown in FIG. 10, a pulse generator 100 according to the second modification includes a delay circuit 10 including inverters I1 to I9, a buffer circuit 20 including buffers B1 to B9, and unit pulse generation. Circuit 31_1. In addition, in the pulse generator 100 of FIG. 10, the potential adjustment circuit 40 is omitted.
The unit pulse generation circuit 31_1 includes a timing signal generation unit 32_1 and a unit pulse signal generation unit 33_1.

The timing signal generator 32_1 of the second modification has a configuration different from that of the above-described embodiment and the first modification in order to correspond to the generation of four unit pulse signals.
Specifically, the timing signal generation unit 32_1 of the second modification includes exclusive OR circuits XOR1 to XOR6 and exclusive OR negation circuits XNOR1 to XNOR6.
The output terminal of XNOR1 is electrically connected to one of the input terminals of XOR5, the output terminal of XNOR2 is electrically connected to the other of the input terminals of XOR5, and the output terminal of XOR5 is the unit pulse signal generator 33_1. Is electrically connected to the gate terminal of PTr1.

The output terminal of XOR1 is electrically connected to one of the input terminals of XNOR5, the output terminal of XOR2 is electrically connected to the other of the input terminals of XNOR5, and the output terminal of XNOR5 is the unit pulse signal generator 33_1. Is electrically connected to the gate terminal of PTr2.
The output terminal of XOR3 is electrically connected to one of the input terminals of XNOR6, the output terminal of XOR4 is electrically connected to the other of the input terminals of XNOR6, and the output terminal of XNOR6 is the unit pulse signal generator 33_1. This is electrically connected to the gate terminal of NTr1.

The output terminal of XNOR3 is electrically connected to one of the input terminals of XOR6, the output terminal of XNOR4 is electrically connected to the other of the input terminals of XOR6, and the output terminal of XOR6 is the unit pulse signal generator 33_1. This is electrically connected to the gate terminal of NTr2.
One of the input terminals of XNOR1 is electrically connected to the output terminal of buffer B3, and the other is electrically connected to the output terminal of buffer B4. One of the input terminals of XNOR2 is the output terminal of buffer B7 and the other is the output terminal of buffer B8. Are electrically connected to each other.

One of the input terminals of XOR1 is electrically connected to the output terminal of buffer B2, and the other is electrically connected to the output terminal of buffer B5. One of the input terminals of XOR2 is the output terminal of buffer B6, and the other is the output terminal of buffer B9. Are electrically connected to each other.
One of the input terminals of XOR3 is electrically connected to the output terminal of buffer B2, and the other is electrically connected to the output terminal of buffer B3. One of the input terminals of XOR4 is the output terminal of buffer B6, and the other is the output terminal of buffer B7. Are electrically connected to each other.
One of the input terminals of XNOR3 is electrically connected to the output terminal of buffer B3, and the other is electrically connected to the output terminal of buffer B4. One of the input terminals of XNOR4 is the output terminal of buffer B5 and the other is the output terminal of buffer B8. Are electrically connected to each other.

Next, a specific operation of the pulse generator 100 having the circuit configuration shown in FIG. 10 will be described with reference to FIG.
Here, FIG. 11 is a timing chart of input / output signals of the unit pulse generation circuit 31_1 shown in FIG.
First, as shown in FIG. 11, when the start signal D0 input to the inverter I1 of the delay circuit 10 changes from low level to high level, XD1 ′ changes from high level to low level. First, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generator 33_1 are changed from “L”, “H”, “H”, and “L” to “ It changes to “L”, “H”, “H”, “H”. When logic signals A to D corresponding to “L”, “H”, “H”, and “H” are input to the unit pulse signal generation unit 33_1, the first unit pulse signal of the unit pulse signal generation unit 33_1 is input. As a part, a low level signal is output from the output terminal OUT.

  Subsequently, as D2 ′ changes from the low level to the high level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din become “L”, “H”, “ Changes from “H”, “H” to “L”, “L”, “L”, “H”. When logic signals A to D corresponding to “L”, “L”, “L”, and “H” are input to the unit pulse signal generation unit 33_1, the first unit pulse signal of the unit pulse signal generation unit 33_1 is input. As a part, a high level signal is output from its output terminal OUT.

  Subsequently, when XD3 ′ changes from the high level to the low level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_1 become “L”. ”,“ L ”,“ L ”,“ H ”to“ H ”,“ L ”,“ H ”,“ H ”. When logic signals A to D corresponding to “H”, “L”, “H”, and “H” are input to the unit pulse signal generation unit 33_1, the second unit pulse signal of the unit pulse signal generation unit 33_1 is input. As a part, a low level signal is output from the output terminal OUT.

  Subsequently, when D4 ′ changes from the low level to the high level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_1 become “H”. ”,“ L ”,“ H ”,“ H ”to“ L ”,“ L ”,“ H ”,“ L ”. When logic signals A to D corresponding to “L”, “L”, “H”, and “L” are input to the unit pulse signal generation unit 33_1, the second unit pulse signal of the unit pulse signal generation unit 33_1 is input. As a part, a high level signal is output from its output terminal OUT.

  Subsequently, when XD5 ′ changes from the high level to the low level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_1 become “L ”,“ L ”,“ H ”,“ L ”to“ L ”,“ H ”,“ H ”,“ H ”. When logic signals A to D corresponding to “L”, “H”, “H”, “H” are input to the unit pulse signal generation unit 33_1, the unit pulse signal of the third unit pulse signal of the unit pulse signal generation unit 33_1 is input. As a part, a low level signal is output from the output terminal OUT.

  Subsequently, as D6 ′ changes from the low level to the high level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_1 are “L”. ”,“ H ”,“ H ”,“ H ”to“ L ”,“ L ”,“ L ”,“ H ”. When logic signals A to D corresponding to “L”, “L”, “L”, and “H” are input to the unit pulse signal generation unit 33_1, the unit pulse signal of the third unit pulse signal of the unit pulse signal generation unit 33_1 is input. As a part, a high level signal is output from its output terminal OUT.

  Subsequently, when XD7 ′ changes from the high level to the low level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_1 become “L”. ”,“ L ”,“ L ”,“ H ”to“ H ”,“ L ”,“ H ”,“ H ”. When logic signals A to D corresponding to “H”, “L”, “H”, and “H” are input to the unit pulse signal generation unit 33_1, the unit pulse signal of the fourth unit pulse signal of the unit pulse signal generation unit 33_1 is input. As a part, a low level signal is output from the output terminal OUT.

  Subsequently, when D8 ′ changes from the low level to the high level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_1 become “H”. ”,“ L ”,“ H ”,“ H ”to“ L ”,“ L ”,“ H ”,“ L ”. When logic signals A to D corresponding to “L”, “L”, “H”, and “L” are input to the unit pulse signal generation unit 33_1, the fourth unit pulse signal of the unit pulse signal generation unit 33_2 is output. As a part, a high level signal is output from its output terminal OUT.

  Subsequently, when XD9 ′ changes from the high level to the low level, the logic signals A, B, C, and D input to the input terminals Ain, Bin, Cin, and Din of the unit pulse signal generation unit 33_1 become “H”. ”,“ L ”,“ H ”,“ H ”to“ L ”,“ H ”,“ H ”,“ L ”. When the logic signals A to D corresponding to “L”, “H”, “H”, and “L” are input to the unit pulse signal generation unit 33_1, the output becomes high impedance.

In this state, when the activation start signal D0 changes from the high level to the low level, the logic signals A to D change as in the series of processes, and the unit pulse signal generator 33_1 continuously outputs the unit pulse signals. Occurs 4 times.
As described above, in the pulse generation device 100 of the second modification, the unit pulse generation circuit 31_1 changes the delay state of these delay signals based on a plurality of types of delay signals from a plurality of cascaded inverters constituting the delay circuit 10. It is possible to generate a logic signal that changes in response, and to generate all four unit pulse signals constituting one pulse signal based on the logic signal.

As a result, the number of unit pulse generation circuits can be reduced to ¼ compared to the case where four unit pulse signals constituting one pulse signal are generated by the same number of unit pulse generation circuits. .
Further, since the number of circuits can be one, the unit pulse generation circuit that generates the unit pulse signal is compared with the configuration in which a plurality of unit pulse generation circuits are connected to a common signal output line by wired OR. On the other hand, since the remaining unit pulse generation circuit does not become a capacitive load, it is possible to generate a pulse signal having a good amplitude level.

[Modification 3]
Next, Modification 3 of the embodiment of the present invention will be described with reference to the drawings. 12-13 is a figure which shows the modification 3 of embodiment of the pulse generator which concerns on this invention.
The third modification is provided with a negative-phase unit pulse generation circuit that generates a unit pulse signal having a phase opposite to that of the unit pulse generation circuit 31 in addition to the unit pulse generation circuit 31. Different from each of the above modifications.
Hereinafter, as a third modification of the above-described embodiment, as illustrated in FIGS. 12 and 13, the configuration of the pulse generator 100 includes three unit pulse generation circuits 31 </ b> _ <b> 1 to 31 </ b> _ <b> 3 and three antiphase unit pulse generation circuits 34 </ b> _ <b> 1. ˜34_3 and a configuration that generates a pulse signal composed of four unit pulse signals and an anti-phase pulse signal having a phase difference of 180 ° from the pulse signal will be described as an example.

Note that the same components as those in the above embodiment are denoted by the same reference numerals, description thereof will be omitted as appropriate, and different portions will be described in detail.
First, the first circuit configuration of the pulse generator 100 of the third modification will be described with reference to FIG.
Here, FIG. 12 is a diagram showing a first circuit configuration of the pulse generator 100 of the third modification. In FIG. 12, in order to avoid making the drawing difficult to see, some of the connections between the buffer output terminals and the signal input terminals of the timing signal generators 32_1 to 32_3 and 35_1 to 35_3 are omitted. The input terminal is actually electrically connected to the output terminal of the buffer that outputs the corresponding delay signal.

As shown in FIG. 12, the pulse generator 100 according to the third modification includes a delay circuit 10 including inverters I1 to I13, a buffer circuit 20 including buffers B1 to B13, and a unit pulse. The generation circuits 31_1 to 31_3, the negative phase unit pulse generation circuits 34_1 to 34_3, and the potential adjustment circuits 40_P and 40_N including the NTr3 to NTr4 are configured.
The delay circuit 10 is configured by cascading a lower output terminal and an input terminal of the next number in descending order of numbers, with the inverter I1 as the start and the inverter I13 as the end.
The buffer circuit 20 is configured to include buffers B1 to B11 in which the input terminals are electrically connected to the output terminals of the inverters I1 to I11 with the same numbers.
The configuration and connection configuration of the unit pulse generation circuits 31_1 to 31_3 are the same as those of the first modification.

The negative phase unit pulse generation circuit 34_1 includes a timing signal generation unit 35_1 and a unit pulse signal generation unit 33_1.
In the timing signal generation unit 35_1, one input terminal of two input terminals is electrically connected to the output terminal of the buffer B4, the other input terminal is electrically connected to the output terminal of the buffer B7, and the output terminal is a unit. The exclusive OR circuit XOR1 electrically connected to the input terminal Ain of the pulse signal generator 33_1 is configured.
Furthermore, one input terminal of the two input terminals is electrically connected to the output terminal of the buffer B3, the other input terminal is electrically connected to the output terminal of the buffer B8, and the output terminal is the unit pulse signal generator 33_1. And an exclusive OR circuit XNOR1 electrically connected to the input terminal Bin.

Furthermore, one input terminal of the two input terminals is electrically connected to the output terminal of the buffer B3, the other input terminal is electrically connected to the output terminal of the buffer B6, and the output terminal is the unit pulse signal generator 33_1. The exclusive OR circuit XNOR2 is electrically connected to the input terminal Cin.
Furthermore, one input terminal of the two input terminals is electrically connected to the output terminal of the buffer B2, the other input terminal is electrically connected to the output terminal of the buffer B7, and the output terminal is the unit pulse signal generator 33_1. And an exclusive OR circuit XOR2 electrically connected to the input terminal Din.
The negative phase unit pulse generation circuit 34_2 includes a timing signal generation unit 35_2 and a unit pulse signal generation unit 33_2.

In the timing signal generator 35_2, one input terminal of two input terminals is electrically connected to the output terminal of the buffer B6, the other input terminal is electrically connected to the output terminal of the buffer B9, and the output terminal is a unit. The exclusive OR circuit XOR1 electrically connected to the input terminal Ain of the pulse signal generator 33_2 is included.
Furthermore, one input terminal of the two input terminals is electrically connected to the output terminal of the buffer B5, the other input terminal is electrically connected to the output terminal of the buffer B10, and the output terminal is the unit pulse signal generator 33_2. And an exclusive OR circuit XNOR1 electrically connected to the input terminal Bin.

Furthermore, one input terminal of the two input terminals is electrically connected to the output terminal of the buffer B5, the other input terminal is electrically connected to the output terminal of the buffer B8, and the output terminal is the unit pulse signal generator 33_2. The exclusive OR circuit XNOR2 is electrically connected to the input terminal Cin.
Furthermore, one input terminal of the two input terminals is electrically connected to the output terminal of the buffer B4, the other input terminal is electrically connected to the output terminal of the buffer B9, and the output terminal is the unit pulse signal generator 33_2. And an exclusive OR circuit XOR2 electrically connected to the input terminal Din.

The negative phase unit pulse generation circuit 34_3 includes a timing signal generation unit 35_3 and a unit pulse signal generation unit 33_3.
In the timing signal generator 35_3, one input terminal of two input terminals is electrically connected to the output terminal of the buffer B8, the other input terminal is electrically connected to the output terminal of the buffer B11, and the output terminal is a unit. The exclusive OR circuit XOR1 electrically connected to the input terminal Ain of the pulse signal generator 33_3 is included.
Furthermore, one input terminal of the two input terminals is electrically connected to the output terminal of the buffer B7, the other input terminal is electrically connected to the output terminal of the buffer B12, and the output terminal is the unit pulse signal generator 33_3. And an exclusive OR circuit XNOR1 electrically connected to the input terminal Cin.

Furthermore, one input terminal of the two input terminals is electrically connected to the output terminal of the buffer B7, the other input terminal is electrically connected to the output terminal of the buffer B10, and the output terminal is the unit pulse signal generator 33_3. The exclusive OR circuit XNOR2 is electrically connected to the input terminal Cin.
Furthermore, one input terminal of the two input terminals is electrically connected to the output terminal of the buffer B7, the other input terminal is electrically connected to the output terminal of the buffer B11, and the output terminal is the unit pulse signal generator 33_3. And an exclusive OR circuit XOR2 electrically connected to the input terminal Din.

In the potential adjustment circuit 40_P, the drain terminal of NTr3 is electrically connected to the output terminals of the unit pulse signal generators 33_1 to 33_3, the source terminal of NTr3 is electrically connected to the drain terminal of NTr4, and the source terminal of NTr4 is It is electrically connected to a power supply node at the GND potential.
Furthermore, the gate terminal of NTr3 is electrically connected to the output terminal of buffer B11, and the gate terminal of NTr4 is electrically connected to the output terminal of buffer B1.
Further, a pulse signal output terminal Pout_P is formed at the drain terminal of NTr3.

In the potential adjustment circuit 40_N, the drain terminal of NTr3 is electrically connected to the output terminals of the negative-phase unit pulse signal generators 34_1 to 34_3, the source terminal of NTr3 is electrically connected to the drain terminal of NTr4, and the source of NTr4 The terminal is electrically connected to the power supply node at the GND potential.
Furthermore, the gate terminal of NTr3 is electrically connected to the output terminal of buffer B15, and the gate terminal of NTr4 is electrically connected to the output terminal of buffer B1.
Further, a pulse signal output terminal Pout_N is formed at the drain terminal of NTr3.

With the above configuration, in the unit pulse generation circuits 31_1 to 31_3, the first pulse signal having a configuration in which six unit pulse signals are continuous can be generated twice in response to the rise and fall of the activation start signal D0.
Further, in the negative-phase unit pulse generation circuits 34_1 to 34_3, six unit pulse signals are continuously generated in accordance with the rise and fall of the start start signal D0 at the same generation timing as the unit pulse generation circuits 31_1 to 31_3. A second pulse signal having a phase opposite to that of the first pulse signal can be generated twice.

Next, a second circuit configuration of the pulse generator 100 of the third modification will be described with reference to FIG.
Here, FIG. 13 is a diagram illustrating a second circuit configuration of the pulse generator 100 of the third modification. In FIG. 13, in order to avoid making the drawing difficult to see, some connections between the output terminals of the buffer and the signal input terminals of the timing signal generators 32_1 to 32_3 and 35_1 to 35_3 are omitted. The input terminal is actually electrically connected to the output terminal of the buffer that outputs the corresponding delay signal.

13 is replaced with the configuration of the delay circuit 10 and the buffer circuit 20 in the pulse generation device 100 shown in FIG. , And these input signals are reversed from the input signals of the unit pulse generation circuits 31_1 to 31_3, thereby forming a negative phase unit pulse generation circuit.
Hereinafter, configurations of the delay circuit 10 and the buffer circuit 20 will be described.
As shown in FIG. 13, the delay circuit 10 includes a first delay stage 10a, a second delay stage 10b, and an edge enhancement circuit 10c.

The first delay stage 10a is configured by cascading inverters I1 to I15, starting with the inverter I1 and ending with the inverter I15.
The second delay stage 10b is configured by cascading inverters I1 ′ to I15 ′ starting from the inverter I1 ′ and ending with the inverter I15 ′.
The edge emphasis circuit 10c includes a pair of cross-coupled inverters for each of the inverters I1 to I15 and the inverters I1 ′ to I15 ′ having the same number, and includes a first delay stage 10a and a second delay stage 10a. The delay stage 10b is cross-coupled to make the edge sharp.
The buffer circuit 20 includes a first buffer stage 20a and a second buffer stage 20b.

The first buffer stage 20a includes buffers B1 to B15 whose input terminals are electrically connected with the same numbers as the output terminals of the inverters I1 to I15 of the first delay stage 10a.
The second buffer stage 20b includes buffers B1 ′ to B15 ′ whose input terminals are electrically connected with the same numbers as the output terminals of the inverters I1 ′ to I15 ′ of the second delay stage 10a.
The configuration and connection configuration of the unit pulse generation circuits 31_1 to 31_3 are the same as those of the first modification.
On the other hand, the configuration of the unit pulse generation circuits 31_4 to 31_6 is the same as that of the unit pulse generation circuits 31_1 to 31_3.

Next, the connection configuration of the unit pulse generation circuits 31_4 to 31_6 will be described.
In the timing signal generation unit 35_4, one input terminal of two input terminals is electrically connected to the output terminal of the buffer B4, the other input terminal is electrically connected to the output terminal of the buffer B9, and the output terminal is a unit. The exclusive OR circuit XOR1 electrically connected to the input terminal Ain of the pulse signal generator 33_4 is included.
Furthermore, one input terminal of the two input terminals is electrically connected to the output terminal of the buffer B3, the other input terminal is electrically connected to the output terminal of the buffer B9, and the output terminal is the unit pulse signal generator 33_4. And an exclusive OR circuit XNOR1 electrically connected to the input terminal Bin.

Furthermore, one input terminal of the two input terminals is electrically connected to the output terminal of the buffer B3, the other input terminal is electrically connected to the output terminal of the buffer B8, and the output terminal is the unit pulse signal generation unit 33_4. The exclusive OR circuit XNOR2 is electrically connected to the input terminal Cin.
Furthermore, one input terminal of the two input terminals is electrically connected to the output terminal of the buffer B2, the other input terminal is electrically connected to the output terminal of the buffer B9, and the output terminal is a unit pulse signal generator 33_4. And an exclusive OR circuit XOR2 electrically connected to the input terminal Din.

In the timing signal generator 35_5, one input terminal of two input terminals is electrically connected to the output terminal of the buffer B6, the other input terminal is electrically connected to the output terminal of the buffer B11, and the output terminal is a unit. The exclusive OR circuit XOR1 electrically connected to the input terminal Ain of the pulse signal generator 33_5 is included.
Furthermore, one input terminal of the two input terminals is electrically connected to the output terminal of the buffer B5, the other input terminal is electrically connected to the output terminal of the buffer B12, and the output terminal is the unit pulse signal generator 33_5. And an exclusive OR circuit XNOR1 electrically connected to the input terminal Bin.

Furthermore, one input terminal of the two input terminals is electrically connected to the output terminal of the buffer B5, the other input terminal is electrically connected to the output terminal of the buffer B10, and the output terminal is the unit pulse signal generator 33_5. The exclusive OR circuit XNOR2 is electrically connected to the input terminal Cin.
Furthermore, one input terminal of the two input terminals is electrically connected to the output terminal of the buffer B4, the other input terminal is electrically connected to the output terminal of the buffer B11, and the output terminal is the unit pulse signal generator 33_5. And an exclusive OR circuit XOR2 electrically connected to the input terminal Din.

In the timing signal generator 35_6, one input terminal of two input terminals is electrically connected to the output terminal of the buffer B8, the other input terminal is electrically connected to the output terminal of the buffer B13, and the output terminal is a unit. The exclusive OR circuit XOR1 electrically connected to the input terminal Ain of the pulse signal generator 33_6 is included.
Furthermore, one input terminal of the two input terminals is electrically connected to the output terminal of the buffer B7, the other input terminal is electrically connected to the output terminal of the buffer B11, and the output terminal is the unit pulse signal generator 33_6. And an exclusive OR circuit XNOR1 electrically connected to the input terminal Bin.

Furthermore, one input terminal of the two input terminals is electrically connected to the output terminal of the buffer B7, the other input terminal is electrically connected to the output terminal of the buffer B12, and the output terminal is the unit pulse signal generator 33_6. The exclusive OR circuit XNOR2 is electrically connected to the input terminal Cin.
Furthermore, one input terminal of the two input terminals is electrically connected to the output terminal of the buffer B6, the other input terminal is electrically connected to the output terminal of the buffer B13, and the output terminal is the unit pulse signal generator 33_6. And an exclusive OR circuit XOR2 electrically connected to the input terminal Din.
The potential adjustment circuit 40_P has a configuration similar to that of FIG.

In the potential adjustment circuit 40_N, the drain terminal of NTr3 is electrically connected to the output terminals of the unit pulse signal generation units 34_4 to 34_6, the source terminal of NTr3 is electrically connected to the drain terminal of NTr4, and the source terminal of NTr4 is It is electrically connected to a power supply node at the GND potential.
Furthermore, the gate terminal of NTr3 is electrically connected to the output terminal of buffer B15, and the gate terminal of NTr4 is electrically connected to the output terminal of buffer B2.
Further, a pulse signal output terminal Pout_N is formed at the drain terminal of NTr3.

With the above configuration, in the unit pulse generation circuits 31_1 to 31_3, the first pulse having a configuration in which six unit pulse signals are continuous based on the delay signal having a sharp edge according to the rise and fall of the activation start signal D0. The signal can be generated twice.
Further, in the unit pulse generation circuits 31_4 to 31_6, at the same generation timing as the unit pulse generation circuits 31_1 to 31_3, a delay signal having a sharp edge according to the rise and fall of XD0 obtained by inverting the start start signal D0. Based on this, it is possible to generate a second pulse signal having a phase opposite to that of the first pulse signal in which six unit pulse signals are continuous, twice.

As described above, according to the pulse generation device 100 of the third modification, in the unit pulse generation circuits 31_1 to 31_3, each is based on a plurality of types of delay signals from a plurality of cascaded inverters constituting the delay circuit 10. A logic signal that changes according to the delay state of these delay signals is generated, and based on the logic signal, two unit pulse signals are generated from each of the six unit pulse signals that constitute one first pulse signal. It is possible.
Further, in the unit pulse generation circuits 34_1 to 34_3 or 31_4 to 31_6, each is based on a plurality of types of delay signals from a plurality of cascaded inverters constituting the delay circuit 10, and according to the delay state of these delay signals. A logic signal that changes is generated, and two unit pulse signals of each of six unit pulse signals constituting one second pulse signal (opposite phase from the first pulse signal) are generated based on the logic signal. Can occur.

Thereby, based on the delay signal of the common delay circuit 10, it is possible to generate the first pulse signal and the second pulse signal having a balanced signal relationship.
Furthermore, the number of unit pulse generation circuits can be halved compared to the case where six unit pulse signals constituting one pulse signal are generated by the same number of unit pulse generation circuits.
In addition, since the number of circuits can be reduced, the number of circuits connected to a common signal output line by wired-OR can be reduced. It is possible to reduce the degree of decrease in the amplitude level of the unit pulse signal, which decreases when the unit pulse generation circuit of FIG.

[Modification 4]
Next, Modification 4 of the embodiment of the present invention will be described with reference to the drawings. 14-15 is a figure which shows the modification 4 of embodiment of the pulse generator which concerns on this invention.
In the fourth modification, the delay circuit 10 of the pulse generator 100 is configured not only as a delay stage using an inverter but also as a DLL and PLL, and a PLL including the delay stage is prepared separately, and is the same as this delay stage. The point that the delay circuit is configured by the delay stage is different from the above-described embodiment and each modification.
In the following, the same components as those in the above embodiment are given the same reference numerals, description thereof will be omitted as appropriate, and different portions will be described in detail.

First, a first configuration example of the delay circuit 10 of the present modification will be described based on FIG.
Here, FIGS. 14A to 14C are diagrams illustrating first to third configuration examples of the delay circuit 10.
As shown in FIG. 14A, the first configuration example of the delay circuit 10 includes a delay stage 10a having a configuration in which M inverters I1 to IM are cascade-connected, a PFD (Frequency Phase Detector), and a CP (Charge- a delay amount control signal generation unit 10b configured to include a pump (charge pump) and an LPF (Low-Pass Filter).
That is, the delay circuit 10 of the first configuration example forms a DLL (Delay Locked Loop) from the delay stage 10a and the delay amount control signal generation unit 10b.

In the present modification, the inverters I1 to IM configuring the delay stage 10a have a configuration capable of controlling the delay time using a delay amount control signal (control voltage).
Hereinafter, based on FIG. 15, the structure of the inverter I1 of this modification 4 is demonstrated.
Here, FIG. 15 is a diagram illustrating a circuit configuration example of the inverter I1 capable of controlling the delay time. The inverters I2 to IM have the same configuration as I1.
As shown in FIG. 15, the inverter I1 of Modification 4 includes P-channel field effect transistors PTr4 and PTr5 and N-channel field effect transistors NTr6 and NTr7.

The source terminal of PTr4 is electrically connected to the power supply node of voltage V _DD , the drain terminal of PTr4 is electrically connected to the source terminal of PTr5, and the drain terminal of PTr5 is electrically connected to the drain terminal of NTr6. The source terminal of NTr6 is electrically connected to the drain terminal of NTr7, and the source terminal of NTr7 is electrically connected to the GND node.
Further, an output terminal is formed at a connection portion between the drain terminal of PTr5 and the drain terminal of NTr6.
With the above configuration, by controlling the voltages of the gate terminal G1 of PTr4 and the gate terminal G2 of NTr7, the power supply current flowing into the inverter can be controlled, and thereby the delay time can be controlled.

Returning to FIG. 14A, the delay amount control signal generation unit 10b in the PFD uses the phase of the start signal D0 or XD0 input from the external clock signal generator and the inverter IM at the end of the delay stage 10a. A signal having a positive / negative output proportional to the phase difference from the phase of the input delay signal (hereinafter referred to as a phase difference output signal) is generated and output to the CP.
Specifically, the PFD includes two JK flip-flops, and a phase difference output signal having two types of outputs in the positive direction and the negative direction depending on which rising edge of the start signal or the delay signal is input first. Is generated. Thereby, the phase difference from “−360 °” to “+ 360 °” can be detected.

Next, in the CP, the delay amount control signal generation unit 10b outputs, to the LPF, a signal that changes positively and negatively according to the phase difference output signal input from the PFD.
Specifically, the CP includes an N-channel MOS transistor (hereinafter referred to as NTr) and a P-channel MOS transistor (hereinafter referred to as PTr), although not shown, and the drain of the PTr is on the high potential side. The power supply node is connected, the source of NTr is connected to the power supply node on the low potential side, and the source of PTr and the drain of NTr are connected. And an output is taken out from this connection part.

Next, the delay amount control signal generation unit 10b converts the signal from CP into a control voltage (delay amount control signal) in the LPF, and this signal is applied to the gate terminals of PTr4 and NTr7 of each inverter of the delay stage 10a. Supply.
Specifically, the PWM square wave output from the CP is converted into a signal having a shape close to a direct current, and this is output as a delay amount control signal. Therefore, the control voltage increases as the duty ratio increases.
With the above configuration, since the start signal and the delay signal of the delay stage 10a can be synchronized, the delay amount of the inverters I1 to IM of the delay stage 10a can be kept constant with high accuracy.

Next, a second configuration example of the delay circuit 10 of the present modification will be described based on FIG.
As shown in FIG. 14B, the second configuration example of the delay circuit 10 includes a delay stage 10a, a delay amount control signal generation unit 10b, and a frequency divider 10c having a prescaler and a frequency divider circuit. Consists of including.
The delay stage 10a is composed of an inverter capable of controlling the delay time, as in FIG. 14 (a).
That is, the delay circuit 10 of the second configuration example forms a PLL (Phase Locked Loop) from the delay stage 10a, the delay amount control signal generation unit 10b, and the frequency divider 10c.

The delay amount control signal generator 10b generates the delay amount control signal shown in FIG. 14 (a) only by changing one of the input signals from the delay signal from the delay stage 10a to the divided signal from the frequency divider 10c. It becomes the structure similar to the part 10b.
The frequency divider 10c divides the delay signal input from the delay stage 10a by the total frequency dividing number of the prescaler and the frequency dividing circuit, and outputs the result to the delay amount control signal generation unit 10b.
With the above configuration, since the start signal and the delay signal of the delay stage 10a can be synchronized, the delay amount of the inverters I1 to IM of the delay stage 10a can be kept constant with high accuracy.

Next, a third configuration example of the delay circuit 10 of the present modification will be described based on FIG.
As shown in FIG. 14C, the third configuration example of the delay circuit 10 includes a delay amount control unit including a delay stage 10a, a delay amount control signal generation unit 10b, and a frequency divider 10c. The delay amount control signal generated by the delay amount control unit 50 is supplied to the delay circuit 10 having the same configuration as the delay stage 10a.
The configuration of the delay amount control unit 50 is the same as the configuration of the delay circuit of FIG.
Therefore, the delay amount control signal in a synchronized state can be supplied from the delay amount control unit 50 to each inverter of the delay circuit 10 to control the delay time of each inverter of the delay circuit 10.

With the above configuration, since the start signal and the delay signal of the delay circuit 10 can be synchronized, the delay amount of the inverters I1 to IM of the delay circuit 10 can be kept constant with high accuracy.
Furthermore, since it is not necessary to always supply the start signal to the delay circuit 10, generation of the pulse signal can be stopped.
In the fourth modification, the delay circuit 10 corresponds to the delay circuit described in the first or seventh aspect.
In the above embodiment and each of the above modifications, the transistors constituting each circuit are N-channel type MOS transistors or P-channel type MOS transistors. Any element may be used as long as it has performance applicable to the above.

The above-described embodiment and each of the above-described modified examples are preferable specific examples of the present invention, and various technically preferable limitations are given. However, the scope of the present invention is particularly described in the above description. Unless otherwise stated, the present invention is not limited to these forms. In the drawings used in the above description, for convenience of illustration, the vertical and horizontal scales of members or parts are schematic views different from actual ones.
The present invention is not limited to the above-described embodiment and each of the above-described modifications, and includes modifications and improvements as long as the object of the present invention can be achieved.

DESCRIPTION OF SYMBOLS 100 ... Pulse generator, 10 ... Delay circuit, 20 ... Buffer circuit, 30 ... Pulse generator, 31 ... Unit pulse generator, 32 ... Timing signal generator, 33, 35 ... Unit pulse signal generator, 34 ... Reverse phase Unit pulse generation circuit, 40 ... potential adjustment circuit

Claims (7)

A pulse generator for generating a pulse signal composed of a series of unit pulse signal sequences of a plurality of unit pulse signals,
A delay circuit having a configuration in which first to M-th (M is an integer of 3 or more) delay elements that output an input signal after delay are connected in cascade;
N unit pulse generation circuits (N is an integer of 1 ≦ N <M) for generating the plurality of unit pulse signals based on a delay signal output from the delay element,
The unit pulse generation circuit receives a plurality of delay signals corresponding to a plurality of different delay states in the M delay elements connected in cascade, and has a timing corresponding to each delay state of the input delay signals. A pulse generator for generating two or more unit pulse signals among the plurality of unit pulse signals.   2. The pulse generator according to claim 1, wherein the N unit pulse generation circuits generate the plurality of unit pulse signals in response to rising and falling of the input signal.   The unit pulse generation circuit performs a logical operation based on the plurality of delay signals to generate a plurality of logic signals for determining the generation timing of the unit pulse signal, and a logic based on the plurality of logic signals. The pulse generator according to claim 1, further comprising: a unit pulse signal generation unit that performs an operation to generate the unit pulse signal.   The timing signal generation unit generates a logic signal based on the delay signals of two or more different delay elements among the first to Mth delay elements, and outputs a generated logic signal. The pulse generator according to claim 3, comprising two or more. The timing signal generation unit includes first to fourth logic operation element units,
The unit pulse signal generator is
A P-channel type first field effect transistor having a gate terminal electrically connected to the output portion of the logic signal of the first logic operation element portion and a source terminal connected to a power supply node on a high potential side;
A P-channel type first terminal in which a gate terminal is electrically connected to an output part of the logic signal of the second logic operation element part, and a source terminal is electrically connected to a drain terminal of the first field effect transistor. Two field effect transistors;
An N-channel type first transistor having a gate terminal electrically connected to the output part of the logic signal of the third logic operation element part and a drain terminal electrically connected to the drain terminal of the second field effect transistor. 3 field effect transistors,
The gate terminal is electrically connected to the output part of the logic signal of the fourth logic operation element part, the drain terminal is electrically connected to the source terminal of the third field effect transistor, and the source terminal is low potential An N-channel fourth field effect transistor electrically connected to the power supply node on the side;
5. The pulse according to claim 4, further comprising: a signal output unit electrically connected to a drain terminal of the second field effect transistor and a drain terminal of the third field effect transistor. Generator.   The pulse generation device according to claim 1, wherein the delay element is an inverter circuit.   Based on the delay signals output from the M delay elements connected in cascade of the delay circuit, N pulse generators that generate unit pulse signals of opposite phases that are 180 ° out of phase with the pulse signals generated by the unit pulse generation circuit (N 7. The pulse generator according to claim 1, further comprising a negative-phase unit pulse generation circuit of 1 ≦ N <M).

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