JP2010178199A - Serial communication system and communication method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the processing efficiency of an arithmetic processing unit in a node that performs half duplex communication. <P>SOLUTION: This serial communication system includes a node 2 for performing serial communication with another node through a communication bus 10. The node 2 includes an arithmetic processing unit 14 for generating transmission data to the another node, a transmission buffer 32 for storing the transmission data 200, and a transmission control circuit 31 for transmitting, when performing half duplex communication, the transmission data 200 to the another node after keeping the transmission data 200 stored by the transmission buffer 32 waiting for a predetermined period. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a serial communication system and a communication method, and more particularly to a serial communication system having a plurality of nodes performing half-duplex communication and a communication method.

  There is a half-duplex communication method as asynchronous serial communication. In the half-duplex communication method, since transmission and reception are performed simultaneously on one transmission path, data from other nodes cannot be received while the node is transmitting. Further, transmission cannot be performed while the node is receiving. Therefore, when transmitted by a plurality of nodes, contention occurs on the communication path (communication bus) and correct data cannot be transmitted. Therefore, when each node transmits in the half-duplex communication method, it is necessary to perform transmission when the reception operation is not performed. When receiving, it is necessary to transmit after confirming the end of reception. For this reason, it is common to use a reception completion interrupt or a status flag indicating reception in order to indicate that reception has ended.

  On the other hand, each node generally generates a baud rate based on its operation clock. An error occurs between the baud rates of the nodes due to the difference in the frequency of the operation clock and the accuracy of the operation clock generation unit. For this reason, in a system that performs asynchronous serial communication, an allowable baud rate error range is set for each node (unit). For this reason, the timing at which data bits are received differs depending on each node, and the timing at which the last bit of data is received may have a difference of nearly 1 bit between the nodes under worst conditions.

  For example, when data is transmitted from the node A and the node B whose baud rate error is on the side with a fast allowable range receives the data reception completion interrupt and transmits data, the baud rate error is on the slow side of the allowable range. A node C may receive the data transmitted from the node B before receiving the data from the node A, resulting in a reception error.

  With reference to FIG. 1, details of the operation when a reception error occurs in another node when switching from reception to transmission of data as described above will be described. Here, it is assumed that the sampling signal of the node A is a standard, the sampling timing of the node B is the minimum value in the allowable error, and the sampling timing of the node C is the maximum value in the allowable error.

  When data is transmitted to the data communication bus and node B detects a stop bit at time T1, a reception interrupt signal is output at node B (the reception interrupt transitions to a high level). At time T2, at node B, transmission data is written to the transmission buffer in response to the reception interrupt signal, and then transmitted to the data communication bus.

  The stop bit on the data communication bus is changed by the data (start bit) sent from the node B. As a result, the bit length Tst of the stop bit may be shorter than 1 bit. If the difference between the sampling timing of the node B and the sampling timing of the node C is, for example, 1 bit, the start bit is transmitted on the data communication bus before the node C receives the stop bit. In this case, since node C samples the data of the start bit at the timing (time T3) when detecting the stop bit, a frame reception error occurs, and an error of the entire system is induced.

  That is, if the timing (time T3) for detecting the stop bit in node C is delayed from time T2 when data is transmitted from node B, node C causes a reception error. In order to prevent such an error from occurring, it is necessary to perform control so that the bit length Tst of the stop bit on the communication bus becomes a predetermined length (for example, a length corresponding to 1 bit) when switching from reception to transmission. There is.

  In order to avoid the above problem, a method of delaying the transmission of data from the node B by delaying the reception completion interrupt process is known. For example, there is a method of measuring reception delay processing by software processing or rising of a status flag being received, and measuring a time for delaying data transmission using a software counter based on the reception interrupt processing. However, with this method, when the system frequency depends or when the driver software cannot be shared (shared) for each node, the processing load on the CPU increases and the processing efficiency deteriorates. On the other hand, when the driver software is shared by taking a sufficient time by the software counter, the communication bus efficiency is deteriorated because the idle time of the communication bus increases.

  In order to avoid such a deterioration in efficiency, a technique for delaying a reception interrupt by mode setting is described in Japanese Patent Laid-Open No. 2001-237811 (see Patent Document 1). FIG. 2 is a diagram illustrating a configuration of the serial communication device described in Patent Document 1. In FIG. With reference to FIG. 2, the node 10 described in Patent Document 1 includes a reception control circuit 51, a delay shift register 52, a selector 53, an interrupt control circuit 54, and a CPU 55. The reception control circuit 51 detects a stop bit and sets a reception end flag. The delay shift register 52 delays the reception end flag and sets it in the selector 53. The selector 53 selects one of the reception end flag from the reception control circuit 51 and the reception end flag from the delay shift register 52 according to the mode signal, and sets it in the interrupt control circuit 54. The interrupt control circuit 54 outputs an interrupt request signal to the CPU 55 according to the set reception end flag. The CPU 55 outputs transmission data in response to the interrupt request signal.

  In the half duplex mode, the selector 53 sets the delayed reception end flag in the interrupt control circuit 54. As a result, the output of data from the CPU 55 is delayed, and the data is sent on the communication bus at the time when the bit length of the stop bit exceeds 1 bit. As a result, it can be avoided that the bit length of the stop bit on the communication bus is shortened by the transmission data.

JP 2001-237811 A

  As described above, in the serial communication device described in Patent Literature 1, since the reception completion interrupt is delayed by the mode setting, the reception interrupt is always delayed when the mode is set, and the reception processing time of the CPU is delayed. Therefore, efficiency will deteriorate.

  Referring to FIG. 3, in the serial communication device described in Patent Document 1, a reception completion interrupt is detected during a period from detection (sampling) of a stop bit on the communication bus at time T1 until the next sampling (time T3). The signal issuance is delayed. Therefore, during the period TB from the time T2 when the reception data after the detection of the stop bit is determined to the time T4 after the reception interrupt signal is issued, the CPU 55 cannot execute the preparation and output processing of the transmission data. For example, when one frame of received data is composed of data (8 bits), start bit (1 bit), and stop bit (1 bit), 10% of the time for one frame is prepared for transmission data and It cannot be used for transmission.

  Further, the CPU does not always perform processing according to the interrupt signal as soon as the interrupt signal is input. Although depending on the priority order of interrupt signals, when a plurality of interrupt processes are performed in the CPU, transmission data preparation and output (writing to the transmission data shift register) may take 1 bit or more. In this case, there is no point in delaying the interrupt signal, and the data on the communication bus has a stop bit length of 1 bit or more, so the communication bus efficiency is also deteriorated. Furthermore, in recent years, various peripheral devices have been added, and interrupt processing has also been diversified. For this reason, it is necessary to reduce the processing efficiency of the CPU and the time taken from the reception to the transmission of data even a little.

  [Means for Solving the Problems] will be described below by using the numbers and symbols used in [Mode for Carrying Out the Invention] in parentheses. The numbers and symbols are added to clarify the correspondence between the description of [Claims] and the description of [Mode for Carrying Out the Invention]. [Claims] It should not be used for the interpretation of the technical scope of the invention described in.

  The serial communication system according to the present invention includes a node (2) that performs serial communication with another node via a communication bus (10). The node (2) includes a processing unit (14) that generates transmission data to other nodes, a transmission buffer (32) that holds transmission data (200), and a transmission buffer ( A transmission control circuit (31) for transmitting transmission data (200) held by 32) to another node after waiting for a predetermined period.

  The communication method according to the present invention is performed in a node that performs serial communication with another node via a communication bus (10). The communication method according to the present invention includes a step in which an arithmetic processing unit (14) generates transmission data (200) to another node, a transmission buffer (32) holds transmission data (200), When duplex communication is performed, the transmission data (200) to be held is waited for a predetermined period and then transmitted to another node.

  As described above, according to the present invention, the transmission timing to another node can be changed without waiting for the data output process in the arithmetic processing unit (14).

  Therefore, according to the present invention, it is possible to improve the processing efficiency of the CPU related to data transmission in a serial communication system that performs half-duplex communication.

  In addition, the bit length between the frames of the reception data and the transmission data can be secured so as not to prevent the data reception at other nodes, and a communication error can be avoided.

FIG. 1 is a timing chart showing problems of a general serial communication system. FIG. 2 is a diagram showing a configuration of a serial communication device according to the prior art. FIG. 3 is a timing chart showing problems of the serial communication device shown in FIG. FIG. 4 is a diagram showing a configuration of a serial communication system according to the present invention. FIG. 5 is a diagram showing a configuration of an embodiment of a serial communication device (node) according to the present invention. FIG. 6 is a timing chart showing an example of operation in the first embodiment of the serial communication system according to the present invention. FIG. 7 is a timing chart showing another example of the operation in the first embodiment of the serial communication system according to the present invention. FIG. 8 is a timing chart showing an operation in the second embodiment of the serial communication system according to the present invention.

  Embodiments of a serial communication system according to the present invention will be described below in detail with reference to the accompanying drawings. In general, a communication system that employs asynchronous serial communication can support both a full-duplex communication method and a half-duplex method. In this case, either one is selected and used according to product specifications or user needs. Therefore, in this embodiment, an asynchronous serial communication system capable of switching between a half-duplex communication method and a full-duplex communication method will be described. The present invention is preferably used for a microcomputer in which a plurality of nodes each having an arithmetic processing unit are connected by serial communication.

1. First Embodiment (Configuration)
The configuration of the serial communication system according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a block diagram showing the configuration of the serial communication system according to the present invention. 4, the serial communication system includes a plurality of serial communication devices (nodes) 1, 2, 3,... Connected via a communication bus 10 (data bus). Each of the plurality of nodes 1, 2, 3,... Includes a reception terminal 11 and a transmission terminal 12 connected to the communication bus 10. The reception terminal 11 and the transmission terminal 12 of each of the nodes 1, 2, 3,... Are connected to a common transmission line in the half duplex communication system. In the full-duplex communication system, the reception terminal 11 of the own node and the transmission terminal 12 of another node, and the transmission terminal 12 of the own node and the reception terminal 11 of another node are connected to each other.

  FIG. 5 is a diagram showing a configuration in the embodiment of the serial communication device (node) 2 according to the present invention. The configuration of the node 2 will be described with reference to FIG. Since the configuration of the nodes 1 and 3 is the same as that of the node 2, the description thereof is omitted. Referring to FIG. 5, node 2 includes a processing unit (CPU) 14, an interrupt control circuit U 1, a receiving unit U 2, a transmitting unit U 3, and a baud rate generator 34, each of which is connected via a communication bus 13. To do.

  The receiving unit U2 operates in accordance with the baud rate generated by the baud rate generator 34, and inputs data 100 input from the receiving terminal 11 to the CPU 14 via the communication bus 13. Specifically, the reception unit U2 includes a reception control circuit 21, a reception shift register 22, a reception buffer 23, and a reception sampling circuit 24.

  Data 100 input from the reception terminal 11 is taken into the reception shift register 22 in accordance with the reception sampling signal 101 output from the reception sampling circuit 24. The reception sampling circuit 24 generates the reception sampling signal 101 at a timing corresponding to the baud rate from the baud rate generator 34. The baud rate generator 34 generates a baud rate with a period corresponding to a clock signal (not shown). The clock signal is generated unique to a node, for example. Therefore, the baud rate of each of the nodes 1, 2, 3,... Therefore, in the serial communication system according to the present invention, the allowable baud rate error range is set for each node as in the conventional case.

  The reception control circuit 21 detects the data format of the data fetched by the reception shift register 22. The data frame received at the receiving terminal 11 includes a start bit, a data bit, and a stop bit. When detecting the stop bit, the reception control circuit 21 notifies the interrupt control circuit U1 and the transmission unit U3 (standby control circuit (Wait Time control circuit) 40), and controls the reception shift register 22 to receive the data frame as a reception buffer 23. To be transferred.

  When the reception control circuit 21 detects the stop bit, it outputs a reception completion notification signal 102 to the interrupt control circuit U1 and the transmission unit U3 (standby control circuit 40). Alternatively, the reception control circuit 21 may set a reception completion flag indicating completion of reception when detecting the stop bit. In this case, the interrupt control circuit U1 and the transmission unit U3 (standby control circuit 40) can confirm the reception completion by the reception completion flag. The data frame written in the reception buffer 23 is output to the CPU 14 via the communication bus 13.

  The interrupt control circuit U1 sets a reception interrupt to the CPU 14 in response to the notification of completion of data frame reception. The CPU 14 executes an interrupt process corresponding to the reception interrupt. For example, the CPU 14 generates and outputs a data frame (transmission data) to be transmitted to another node in response to reception as interrupt processing.

  The transmission unit U3 transmits the data frame output from the CPU 13 via the transmission terminal 12 at a timing corresponding to the baud rate. Specifically, the transmission unit U3 includes a transmission control circuit 31, a transmission shift register 32, a transmission timing generation circuit 33, a standby control circuit 40, and an address detection circuit (address check) 41.

  The transmission shift register 32 is assigned a first address for half duplex communication and a second address for full duplex. The CPU 32 outputs transmission data with the first address as the destination when performing half-duplex communication, and outputs transmission data with the second address as the destination when performing full-duplex communication. The data output from the CPU 14 is taken into the transmission shift register 32 in accordance with the transmission timing generated by the transmission timing generation circuit 33. The transmission timing generation circuit 33 determines the transmission timing at a timing corresponding to the baud rate from the baud rate generator 34.

  The address detection circuit 41 detects a destination address (write address) when the CPU 14 accesses the transmission shift register, notifies the standby control circuit 40, and sends the transmission request signal 104 of the transmission data 100 to the standby control circuit 40. Output. The notification of the write address is performed using a flag, for example. The address detection circuit 41 sets the flag level to the first level (for example, high level) indicating the half-duplex communication method when detecting the first address, and the second indicating the full-duplex communication method when detecting the second address. Set to level (for example, low level). That is, in the present invention, the address detection circuit 41 can detect the communication method used in the serial communication system.

  The standby control circuit 40 sets the transmission standby time (standby period) of transmission data according to the notification of reception completion from the reception control circuit 21 and the write address (communication method) detected by the address detection circuit 41. The standby control circuit 40 outputs the transmission request signal 104 output from the address detection circuit 41 to the transmission control circuit 31 as it is as the transmission start signal 105 when communicating by the full-duplex communication method. On the other hand, when communicating by the half-duplex communication method, the standby control circuit 40 controls the transmission request signal 104 output from the address detection circuit 41 as a transmission start signal 105 after waiting for a predetermined period (waiting period). Output to the circuit 31. The standby control circuit 40 sets a standby period based on the transmission timing from the transmission timing generation circuit 33. That is, the time when the transmission start signal 105 is output according to the transmission timing is the end time of the standby period.

  The transmission control circuit 31 sends the transmission data 200 written in the transmission shift register 32 to the transmission terminal 12 (communication bus 10) in response to the transmission start signal 105 from the standby control circuit 40. At this time, the transmission data 200 is transmitted at a transmission timing based on the baud rate.

(Operation)
With reference to FIG.6 and FIG.7, the communication operation | movement by the half duplex communication system of the serial communication system by this invention is demonstrated. FIG. 6 is a timing chart showing an example of operation in the first embodiment of the serial communication system according to the present invention. In the first embodiment, the waiting period Ts is set in advance, and the start time of the waiting period Ts is set according to the detection of the stop bit (reception of the data 100 is completed) (according to the setting of the start time). The end time of the waiting period is also determined). With reference to FIG. 6, the operation of the serial communication system when transmission data is output from the CPU 14 during a preset waiting period Ts will be described.

  Here, the operation of node 2 that transmits transmission data 200 in response to reception of data 100 transmitted from node 1 will be described. The node 1 sends frame data (data 100) including a start bit, data bits (8 bits), and stop bits to the communication bus 10. At time T1, node 2 detects a stop bit. At this time, a high-level reception completion notification signal 102 is set in the standby control circuit 40. At time T2, the standby control circuit 40 is set with the standby control signal 103 at a high level in response to the reception completion notification signal 102. Thereby, a waiting period for data transmission is set. In the present embodiment, standby control signal 103 is set to a high level for a preset period (standby period Ts). That is, the time T5 when the standby period Ts has elapsed from the time T2 is the end time of the standby period.

  On the other hand, when reception of the stop bit is detected, a reception completion interrupt occurs, and at time T3, the transmission data 200 is output from the CPU 14 to the transmission shift register (transmission buffer) 32 and transmitted via the address detection circuit 41. A request signal 104 is output. At this time, the address detection circuit 41 detects that the write address to the transmission shift register 32 is the first address, and notifies the standby control circuit 40 of the detection result. Thereby, the standby control circuit 40 performs control for waiting for the transmission request signal 104 input during the standby period. Specifically, when the time T3 when the transmission request signal 104 is output is within the standby period Ts, that is, when the data 200 is output from the CPU 14 during the standby period Ts, the standby control circuit 40 transmits the transmission request signal 104. During the period from the falling time T4 to the time T5 when the waiting period Ts ends (period Tw), the transmission request signal 104 is made to wait and then output to the transmission control circuit 31 as the transmission start signal 105.

  At time T <b> 6, the transmission control circuit 31 sends the transmission data 200 written in the transmission shift register 32 in response to the transmission start signal 105 from the transmission terminal 11 onto the communication bus 10. The stop bit sent from the node 1 on the communication bus 10 is replaced with the start bit of the data 200 at time T6, but the data width is equal to or longer than the waiting period Ts. Here, by setting the waiting period Ts to 1 bit length or more, the bit length Tst of the stop bit of the data 100 can be set to 1 bit length or more. That is, according to the present invention, even if data 200 is transmitted in response to completion of reception of data 100, the data width of stop bits of data 100 is not shortened. As a result, even if there is a large error (error within an allowable range) in the sampling timing between the node 2 and the other node 3, the data length of the stop bit is secured at least 1 bit, and the node 3 does not cause a reception error. Data 100 can be received.

  In the present invention, the data 200 written from the CPU 14 to the transmission shift register 32 is on standby for a predetermined period Tw. For this reason, the CPU 14 can perform transmission data preparation and output processing in accordance with a reception completion interrupt signal that is output promptly after completion of reception. That is, the CPU 14 can perform an interrupt process for transmitting transmission data immediately after reception is completed. It is possible to eliminate the reduction in the processing efficiency of the CPU and the increase in the time taken from data reception to transmission, which have been problems in the past.

  Furthermore, in the serial communication device 2 according to the present invention, two addresses are assigned to the transmission shift register 32, and the full-duplex communication method and the half-duplex communication method are switched according to the difference in the write address. For example, when there is an access to the second address for the full-duplex communication method, the standby control circuit 40 outputs the transmission request signal 104 as it is to the transmission control circuit 31 as the transmission start signal 105 regardless of the presence or absence of the standby period Ts. . As a result, the node 2 can transmit the transmission data 200 from the CPU 14 and perform full-duplex communication regardless of whether or not data reception is completed.

  FIG. 7 is a timing chart showing another example of the operation in the first embodiment of the serial communication system according to the present invention. With reference to FIG. 7, the operation of the serial communication system when transmission data is output from the CPU 14 after a preset standby period Ts has elapsed will be described.

  Here, as in FIG. 6, the node 1 sends frame data (data 100) including a start bit, a data bit (8 bits), and a stop bit to the communication bus 10. At time T1, node 2 detects a stop bit. At this time, a high-level reception completion notification signal 102 is set in the standby control circuit 40. At time T2, the standby control circuit 40 is set with the standby control signal 103 at a high level in response to the reception completion notification signal 102. Thereby, a waiting period for data transmission is set. In the present embodiment, standby control signal 103 is set to a high level for a preset period (standby period Ts). That is, the time T3 when the standby period Ts has elapsed from the time T2 is the end time of the standby period.

  When reception of the stop bit is detected, a reception completion interrupt is generated. At time T4, the transmission data 200 is output from the CPU 14 to the transmission shift register (transmission buffer) 32, and a transmission request signal is transmitted via the address detection circuit 41. 104 is output. At this time, the address detection circuit 41 detects that the write address to the transmission shift register 32 is the first address, and notifies the standby control circuit 40 of the detection result. Thereby, the standby control circuit 40 performs control for waiting for the transmission request signal 104 input during the standby period.

  Here, when the time T4 when the transmission request signal 104 is output is after the end of the standby period Ts, that is, when the data 200 is output from the CPU 14 after the standby period Ts has elapsed, the standby control circuit 40 transmits The request signal 104 is output to the transmission control circuit 31 as a transmission start signal 105 without waiting (through).

  At time T5, the transmission control circuit 31 sends the transmission data 200 written in the transmission shift register 32 in response to the transmission start signal 105 from the transmission terminal 11 onto the communication bus 10. That is, in the present invention, when the data 200 is sent from the CPU 14 after a predetermined period (waiting period Ts) has elapsed, the data 200 can be sent to the communication bus 10 without waiting. Also in this case, the stop bit sent from the node 1 on the communication bus 10 is replaced with the start bit of the data 200 at time T5, but the data width is equal to or longer than the waiting period Ts. Here, by setting the waiting period Ts to 1 bit length or longer, the bit length Tst of the stop bits of the data 100 becomes 1 bit length or longer.

  In addition, the CPU 14 does not always perform processing according to the interrupt signal as soon as the interrupt signal is input, and the bit length Tst of the stop bit is 1 bit or more even if the data 200 is transmitted. There is. In such a case, in the present invention, since the reception interrupt signal and the data 200 output from the CPU 14 are not delayed, processing can be performed in the shortest time from reception to transmission of the data 200 by the CPU 14. For this reason, when the bit length Tst of the stop bit is sufficiently secured, data transmission can be accelerated compared to the conventional case, and the communication bus efficiency can be improved. Furthermore, in recent years, various peripheral devices have been added, and interrupt processing has also been diversified.

  As described above, in the present invention, since the processing of the CPU 14 is not delayed from the reception of the data 100 to the transmission of the data 200, the processing efficiency of the CPU can be improved. For example, if one frame of received data consists of data (8 bits), start bit (1 bit), and stop bit (1 bit), 10% of one frame that could not be used in the prior art Time can be used for preparation and transmission of transmission data. In the present invention, the data sent from the CPU 14 is put on standby within the waiting period Ts in which the end time is determined with reference to the completion of reception, and the sent data is transmitted without delay after the waiting period Ts has elapsed. As a result, the bit length Tst of the stop bits on the communication bus 10 can be efficiently ensured over the settable standby period Ts regardless of the processing of the CPU 14.

  Furthermore, in the present invention, switching between the full-duplex communication method and the half-duplex communication method is performed using the address. For this reason, unlike mode switching according to the prior art, only the address assigned to the transmission shift register 32 (transmission buffer) is changed, and no significant software change is required. When improving the software, it is necessary to make a change corresponding to each node and to make an improvement consistent with the entire system. For this reason, a lot of cost is required to improve the software. According to the present invention, a serial communication system capable of switching between half-duplex communication and full-duplex communication can be provided by a simple change, so that development costs can be reduced.

2. Second Embodiment With reference to FIG. 8, the operation of the serial communication system according to the second embodiment of the present invention will be described. FIG. 8 is a timing chart showing an operation in the second embodiment of the serial communication system according to the present invention. Since the configuration of the serial communication system according to the second embodiment is the same as that of the first embodiment, description thereof is omitted. In the second embodiment, the start time of the waiting period Ts is set according to detection of the start bit (reception of data 100), and the waiting period Ts is determined according to detection of the stop bit (reception of data 100). End time is set.

  Here, as in FIG. 6, the node 1 sends frame data (data 100) including a start bit, a data bit (8 bits), and a stop bit to the communication bus 10. At time T1, the reception control circuit 21 detects a start bit and outputs a reception start signal 107 to the interrupt control circuit U1 and the standby control circuit 40. At this time, a high level reception start signal 107 is set in the standby control circuit 40. At time T2, the standby control circuit 40 is set with a high-level standby control signal 103 in accordance with the reception start signal 107. Thus, the start time of the data transmission standby period is set. That is, time T2 is the start time of the standby period. The reception control circuit 21 may notify the standby control circuit 40 of the start of reception by a flag instead of the reception start signal 107.

  In the present embodiment, the CPU 14 may generate and output the transmission data 200 regardless of the reception completion interrupt. For example, the transmission data 200 is output from the CPU 14 to the transmission shift register (transmission buffer) 32 at the time T3 in the middle of transmission of the transmission data 100 from the node 1, and the transmission request signal 104 is transmitted via the address detection circuit 41. May be output. In this case, as in the first embodiment, the address detection circuit 41 detects that the write address to the transmission shift register 32 is the first address, and notifies the standby control circuit 40 of the detection result. Thereby, the standby control circuit 40 performs control for waiting for the transmission request signal 104 input during the standby period. That is, when the data 200 is output from the CPU 14 during the standby period Ts, the standby control circuit 40 transmits the transmission request from the falling time T4 of the transmission request signal to the time T7 when the standby period Ts ends (period Tw). After waiting for the signal 104, the signal 104 is output to the transmission control circuit 31 as the transmission start signal 105.

  At time T5, the node 2 detects a stop bit. At this time, a high-level reception completion notification signal 102 is set in the standby control circuit 40. At time T6, the standby control circuit 40 is set with a high-level standby control signal 103 in accordance with the reception completion notification signal 102. Thus, the end time of the data transmission standby period Ts is set. In the present embodiment, the standby control signal 103 is set as a time T7 after a preset period Te from the falling time T6 of the reception completion notification signal 102 as an end time of the standby period Ts.

  At time T <b> 7, the transmission control circuit 31 sends the transmission data 200 written in the transmission shift register 32 in response to the transmission start signal 105 from the transmission terminal 11 onto the communication bus 10. The stop bit sent from the node 1 on the communication bus 10 is replaced with the start bit of the data 200 at time T7, but the data width is equal to or longer than the period Te. Here, by setting the period Te to be 1 bit or longer, the bit length Tst of the stop bits of the data 100 can be made 1 bit or longer. That is, according to the present invention, even if data 200 is transmitted in response to completion of reception of data 100, the data width of stop bits of data 100 is not shortened. As a result, even if there is a large error (error within an allowable range) in the sampling timing between the node 2 and the other node 3, the data length of the stop bit is secured at least 1 bit, and the node 3 does not cause a reception error. Data 100 can be received.

  Further, in the present embodiment, even when transmission data is output from the CPU 14 after the standby period Ts has elapsed, similarly to the example shown in FIG. 7, the output data 200 from the CPU 14 is not delayed and the communication bus is output. 10 can be sent out. Similarly to the first embodiment, half-duplex communication and full-duplex communication can be switched by assigning two addresses to the transmission shift register 32.

  As described above, the serial communication system according to the present embodiment can prepare and output the transmission data 200 by the CPU 14 even before the data reception is completed. Thereby, the processing efficiency of the CPU 14 can be further improved.

  The embodiment of the present invention has been described in detail above, but the specific configuration is not limited to the above-described embodiment, and changes within a scope not departing from the gist of the present invention are included in the present invention. . In the above-described embodiment, the system capable of switching between the half-duplex communication method and the full-duplex communication method has been described. However, the present invention can also be applied to a serial communication system that uses only the half-duplex communication method. Further, the standby control circuit 40 sets the end time of the standby period according to the reception completion notification signal 102, but it may be set according to the reception interrupt signal from the interrupt control circuit U1.

1-3: Node 10: Communication bus (data bus)
11: Reception terminal 12: Transmission terminal 13: Communication bus 14: CPU
21: Reception control circuit 22: Reception shift register 23: Reception buffer 24: Reception sampling generation circuit 31: Transmission control circuit 32: Transmission shift register 33: Transmission timing generation circuit 34: Baud rate generator 40: Wait control circuit (Wait Tim control circuit) )
41: Address detection circuit (address check)
100: Data (received data, transmission data of node 1)
101: Reception sampling signal 102: Reception completion notification signal 103: Standby control signal 104: Transmission request signal 105: Transmission start signal 107: Reception start signal 200: Data (transmission data)
U1: Interrupt control circuit U2: Reception unit U3: Transmission unit

Claims (14)

Comprising a node for serial communication with other nodes via a communication bus;
The node is
An arithmetic processing unit that generates transmission data to the other nodes;
A transmission buffer for holding the transmission data;
When performing half-duplex communication, after waiting for transmission data held in the transmission buffer for a predetermined period, a transmission control circuit for transmitting to the other node;
With
Serial communication system. The serial communication system according to claim 1,
The node further includes a standby control circuit that sets an end time of the standby period with reference to the completion of data reception,
When performing half-duplex communication, the transmission control circuit transmits the transmission data written in the transmission buffer during the standby period to the other node after waiting for the end time. The serial communication system according to claim 2,
The transmission buffer is assigned a first address for half-duplex communication,
The node further includes an address detection circuit that detects a write address to the transmission buffer by the arithmetic processing unit;
The transmission control circuit waits for transmission of transmission data written in the transmission buffer when the first address is detected as the write address during the standby period. The serial communication system according to claim 2 or 3,
The transmission buffer is further assigned a second address for full duplex communication,
The transmission control circuit transmits the transmission data written in the transmission buffer without waiting when the second address is detected as the write address. The serial communication system according to any one of claims 2 to 4,
When transmission data is written to the transmission buffer after the waiting period has elapsed, the transmission control circuit transmits the data written to the transmission buffer without waiting.
Serial communication system. The serial communication system according to any one of claims 2 to 5,
The arithmetic processing unit issues a transmission request signal together with the generation of the transmission data,
When performing half-duplex communication, the standby control circuit holds the transmission request signal received during the standby period until the end time, and then outputs to the transmission control circuit as a transmission start signal,
The transmission control circuit transmits transmission data held by the transmission buffer to the other node in response to the transmission start signal. The serial communication system according to claim 6, wherein
The transmission request signal received after the standby period has elapsed is transmitted as the transmission start signal without waiting.
Serial communication system. In a communication method performed in a node that performs serial communication with another node via a communication bus,
An arithmetic processing unit generating transmission data to the other node;
A transmission buffer holding the transmission data;
When performing half-duplex communication, waiting for a predetermined period of the transmission data to be held, and then transmitting to the other node;
A communication method comprising: The communication method according to claim 8, wherein
Further comprising the step of setting the end time of the waiting period with reference to the completion of data reception;
The step of transmitting the transmission data includes a step of transmitting the transmission data written in the transmission buffer during the standby period to the other node after waiting for the transmission data to the end time. The communication method according to claim 9, wherein
The transmission buffer is assigned a first address for half-duplex communication,
Further comprising detecting a write address to the transmission buffer by the arithmetic processing unit;
The step of transmitting the transmission data waits for transmission of the transmission data written in the transmission buffer when the first address is detected as the write address during the standby period. The communication method according to claim 9 or 10,
The transmission buffer is further assigned a second address for full duplex communication,
A communication method further comprising the step of transmitting without waiting the transmission data written to the transmission buffer when the second address is detected as the write address. The communication method according to any one of claims 9 to 11,
A communication method further comprising the step of transmitting without waiting the data written in the transmission buffer when transmission data is written in the transmission buffer after the waiting period has elapsed. The communication method according to any one of claims 9 to 12,
The arithmetic processing unit further comprises a step of issuing a transmission request signal together with the generation of the transmission data,
The step of transmitting the transmission data includes:
Holding the transmission request signal received during the waiting period until the end time, and then outputting to the transmission control circuit as a transmission start signal;
Transmitting the transmission data held in the transmission buffer to the other node in response to the transmission start signal. The communication method according to claim 13,
The method further includes the step of transmitting the transmission request signal received after the standby period has elapsed as the transmission start signal without waiting.
Communication method.

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