JP2010198429A - Interruption control unit and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interruption control unit capable of reducing the processing load of an arithmetic unit and enhancing certainty that interrupt processing with a high priority is executed, and an image forming apparatus. <P>SOLUTION: The interruption control unit includes: a priority setting part 104 for receiving an interrupt signal for requesting interrupt processing of the arithmetic unit and setting a priority corresponding to the interrupt processing to be executed by the arithmetic unit on the basis of the received interrupt signal to the interrupt signal; a period setting part 107 for setting the period of an enabling signal for allowing the interrupt signal to be output to the arithmetic unit in accordance with the priority; and an outputting part 106 for outputting the interrupt signal to the arithmetic unit on the basis of the interrupt signal and the enabling signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an interrupt control device and an image forming apparatus.

  When an image forming apparatus connected to a network such as a LAN (Local Area Network) receives packet data transmitted via the network, the image forming apparatus interrupts the arithmetic processing unit every time packet data is received. The received packet data is processed.

  In Patent Document 1, an interrupt is generated when a specified period has passed since the previous interrupt, or when a packet arrives when the number of packets that have arrived after the previous interrupt exceeds a threshold value. .

Japanese Patent Laid-Open No. 9-223091

  An object of the present invention is to provide an interrupt control device and an image forming apparatus that reduce the processing load of an arithmetic device and increase the certainty that an interrupt process with a high priority is executed.

  The interrupt control device according to claim 1 accepts an interrupt signal for requesting an interrupt process from the arithmetic device, and sets a priority according to the interrupt process to be executed by the arithmetic device based on the received interrupt signal. Priority setting means for setting the interrupt signal; period setting means for setting a period of a permission signal for permitting output of the interrupt signal to the arithmetic unit according to the priority; and the interrupt signal; Output means for outputting the interrupt signal to the arithmetic unit based on the permission signal.

  The interrupt control device according to claim 2 is the interrupt control device according to claim 1, wherein the cycle setting unit sets the cycle after the output unit outputs a first interrupt signal. It is characterized by starting.

  The image forming apparatus according to claim 3, wherein an arithmetic device that executes an operation and an interrupt signal that requests the arithmetic device to perform an interrupt process are received and an interrupt that is executed by the arithmetic device based on the received interrupt signal. Priority setting means for setting a priority according to an interrupt process to the interrupt signal, and a period for setting a cycle of a permission signal that permits the output of the interrupt signal to the arithmetic unit according to the priority Setting means; and output means for outputting the interrupt signal to the arithmetic unit based on the interrupt signal and the permission signal.

  According to a fourth aspect of the present invention, in the image forming apparatus according to the third aspect, the cycle setting unit starts setting the cycle after the output unit outputs the first interrupt signal. Features.

  The invention according to claim 1 reduces the processing load of the arithmetic processing unit and increases the certainty that the arithmetic processing executes the interrupt processing having a high priority.

  The invention according to claim 2 outputs an interrupt signal to the arithmetic processing unit if an interrupt signal exists when no interrupt signal is output to the arithmetic unit.

  The invention according to claim 3 reduces the processing load on the arithmetic processing unit and increases the certainty that the arithmetic processing unit executes the interrupt processing with a high priority.

  According to a fourth aspect of the present invention, if an interrupt signal is present when no interrupt signal is output to the arithmetic unit, the interrupt signal is output to the arithmetic processing unit.

1 is a diagram illustrating an example of a configuration of an image forming system. 1 is a diagram illustrating an example of a system configuration of an image forming apparatus to which the present invention is applied. It is a figure which shows an example of a structure of a communication control part and a control part. It is a figure which shows an example of a structure of an interruption control part. It is a figure which shows an example of the relationship between the kind of packet data, and a priority. 6 is a timing chart illustrating an example of an interrupt signal output process when an interrupt process occurs. 6 is a timing chart illustrating an example of an interrupt signal output process when an interrupt process occurs.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

First, an example of the configuration of an image forming system including an image forming apparatus to which the present invention is applied will be described with reference to FIG.
The image forming system includes an image forming apparatus 100, a terminal device 200, and an image reading apparatus 300. Each device is connected to the network 400 and can communicate with each other via the network 400.
The image forming apparatus 100 is an apparatus that receives image data from the terminal apparatus 200 and the image reading apparatus 300 and forms an image based on the image data on a recording sheet. Examples of the image forming apparatus 100 include a printer apparatus, a facsimile apparatus, a copying apparatus, and a multi-function machine having a combination of the functions of the above-described apparatuses.

The terminal device 200 is a personal computer or the like handled by the user. The user selects a desired file (image data) from the terminal device 200 and requests the image forming apparatus 100 to form an image. The terminal device 200 requests the image forming apparatus 100 to form an image by transmitting packet data requesting the image forming apparatus 100 to form an image. The terminal device 200 transmits various packet data (details will be described later) to the image forming apparatus 100.
In addition, the user requests the image reading device 300 to read the document placed on the document table of the image reading device 300 from the terminal device 200.

In accordance with a request from the terminal device 200 or an instruction from a user received by the operation unit, the image reading apparatus 300 scans a figure or the like by scanning from a document placed on the document table or a document conveyed on the document table. Scan a photo or text and convert it to digital data (image data). An example of the image reading device 300 is a scanner device.
In the present embodiment, one image forming apparatus 100, one terminal apparatus 200, and one image reading apparatus 300 are connected to the network 400, but a plurality of the image forming apparatus 100, the terminal apparatus 200, and the image reading apparatus 300 may be connected to the network 400. A configuration without the reading device 300 may be employed.

Next, an example of the system configuration of the image forming apparatus to which the present invention is applied will be described with reference to FIG.
The image forming apparatus 100 includes a communication control unit 10, an image input unit 20, an image processing unit 30, an image output unit 40, and a control unit 50.

  The communication control unit 10 receives image data from the terminal device 200 or the like via a network. The terminal device 200 receives a signal for inquiring about a MAC (Media Access Control) address and an SNMP (Simple Network Management Protocol) signal transmitted from the terminal device 200.

The image input unit 20 is a unit that reads an image from a printed material (original) or the like, and is, for example, a scanner device.
The image processing unit 30 processes the image data received from the terminal device 200 or the like by the image input unit 20 or the communication control unit 10 via the network into a format that the image output unit 40 can output.
The image output unit 40 forms an image on a recording sheet based on the image data processed by the image processing unit 30 and outputs the image.

  The control unit 50 is connected to the image input unit 20, the image processing unit 30, the image output unit 40, and the communication control unit 10. The control unit 50 controls the image reading operation by the image input unit 20, controls the transmission and reception of data with the terminal device 200 and the like performed by the communication control unit 10 via the network, and the image data processing operation by the image processing unit 30. And control of image formation on the recording paper and output operation by the image output unit 40.

  Next, referring to FIG. 3, an example of the configuration of the communication control unit 10 and the control unit 50 will be described, and transmission / reception of data between the two will be described.

  First, an example of the configuration of the control unit 50 will be described. The control unit 50 includes an input / output unit 504 that inputs and outputs signals, and a ROM that stores a program for controlling the image input unit 20, the image processing unit 30, the image output unit 40, and the entire image forming apparatus 100. (Read Only Memory) 503, a central processing unit (CPU) 501 that reads a program stored in the ROM 503 and executes control processing and arithmetic processing, and a temporary processing used when the program is executed It comprises a RAM (Random Access Memory) 502 that temporarily stores data and packet data such as image data (details will be described later).

The input / output unit 504 receives signals from the packet receiving unit 101 and the interrupt control unit 102 of the communication control unit 10 to be described later.
When the input / output unit 504 receives packet data from the packet receiving unit 101, the control unit 50 stores the packet data in the RAM 502.
The input / output unit 504 that has received the interrupt signal from the interrupt control unit 102 transmits the interrupt signal to the CPU 501. When the CPU 501 receives the interrupt signal, the CPU 501 reads packet data corresponding to the interrupt signal from the RAM 502 and executes control processing or arithmetic processing.

  Next, an example of the configuration of the communication control unit 10 will be described with continued reference to FIG. The communication control unit 10 includes a packet receiving unit 101, an interrupt control unit 102, and a time measuring unit 103.

The packet receiving unit 101 is connected to the terminal device 200, the interrupt control unit (interrupt control device) 102, and the input / output unit 504 constituting the control unit 50 via a network.
The packet receiving unit 101 receives packet data transmitted by the terminal device 200 or the like. When receiving the packet data, the packet receiving unit 101 outputs the received packet data to the input / output unit 504 of the control unit 50. The packet receiving unit 101 outputs an interrupt signal to the interrupt control unit 102 when transmission of the received packet data is completed.

  Here, the packet data received by the packet receiving unit includes an ARP (Address Resolution Protocol) request that requests transmission of the MAC address of the image forming apparatus 100, and an LPR (Line PRinter daemon protocol that requests image formation from the image forming apparatus 100. ) Requests, SNMP requests for requesting notification of the operating status of the image forming apparatus 100, and the like.

The interrupt control unit 102 is connected to the packet receiving unit 101, the time measuring unit 103, and the input / output unit 504 of the control unit 50.
The interrupt control unit 102 receives an interrupt signal from the packet receiving unit 101. The interrupt signal from the packet receiving unit 101 has data for identifying the type of packet data received by the packet receiving unit 101. The interrupt control unit 102 acquires the type of packet data from the interrupt signal, and controls the timing for outputting the interrupt signal to the input / output unit 504 based on the type of packet data. The interrupt control unit 102 acquires time information from the time measuring unit 103 in order to determine the timing for outputting the interrupt signal. Then, the interrupt control unit 102 controls the timing of outputting an interrupt signal using the time information acquired from the time measuring unit 103, thereby limiting the number of interrupt processes that the CPU 501 processes within a certain period. .

  The timer 103 is connected to the interrupt controller 102. The time measuring unit 103 is a means for measuring time, for example, a timer. The time measuring unit 103 outputs the time measured to the interrupt control unit 102.

Next, an example of the configuration of the interrupt control unit 102 will be described with reference to FIG.
The interrupt control unit 102 includes a priority setting unit (priority setting means) 104 and mask circuits 105-1 to 105-n (hereinafter referred to as a mask circuit 105 unless otherwise distinguished).

The priority setting unit 104 is connected to the packet receiving unit 101 and each of the mask circuits 105-1 to 105-n.
The priority setting unit 104 receives an interrupt signal from the packet receiving unit 101. As described above, since the interrupt signal from the packet receiving unit 101 includes data for identifying the type of packet data, the priority setting unit 104 acquires the type of packet data from the received interrupt signal. To do.
Since the priority for causing the CPU 501 to execute the interrupt processing is determined depending on the type of packet data, the priority setting unit 104 sets the priority for the interrupt signal based on the acquired type of packet data, and sets the priority. An interrupt signal is output to the mask circuit 105 corresponding to the degree.

Here, an example of the relationship between the type of packet data and the priority will be described with reference to FIG. FIG. 5 is a diagram illustrating an example of priorities set based on the type of packet data.
According to FIG. 5, when the packet data received by the packet receiving unit 101 is an ARP request for requesting transmission of a MAC address, an LRP request for requesting printing, and an SNMP for inquiring an operation state, the priority of the ARP request. Is the highest, followed by LRP request and SNMP request.
Therefore, if the type of the acquired packet data is an ARP request, the priority setting unit 104 sets the priority to “high” and outputs an interrupt signal to the mask circuit 105 corresponding to the priority “high”. . For example, if the mask circuit corresponding to the priority “high” is the mask circuit 105-1, the priority setting unit 104 outputs an interrupt signal to the mask circuit 105-1.
Here, the packet data received by the packet receiving unit 101 and the priority thereof are not limited to the present embodiment. The priority may be determined based on the frequency with which the terminal device 200 or the like transmits packet data, or whether or not the packet data is retransmitted when no response is received from the image forming apparatus 100. .

The configuration of the interrupt control unit 102 will be described again with reference to FIG. The mask circuit 105 is connected to the priority setting unit 104, the time measuring unit 103, and the control unit 50. The mask circuits 105-1 to 105-n are provided in accordance with the priority with which the CPU 501 of the control unit 50 performs the packet data interrupt process.
The mask circuit 105 determines whether or not an interrupt signal is received from the priority setting unit 104 for each period, and outputs an interrupt signal to the control unit 50 if the interrupt signal is received from the priority setting unit 104. To do. The mask circuit 105 acquires time information from the time measuring unit 103 in order to measure a certain period.

  The cycle for determining whether or not the mask circuit 105 accepts the interrupt signal becomes shorter as the priority corresponding to the mask circuit 105 becomes higher. Accordingly, the higher the corresponding priority is, the more frequently the mask circuit 105 determines whether or not the interrupt signal is received from the priority setting unit 104.

  Next, the configuration of the mask circuit 105 will be described with reference to FIG. Mask circuit 105-1 to mask circuit 105-n are output units (output means) 106-1 to 106-n (hereinafter referred to as output unit 106 unless otherwise distinguished) and cycle setting unit ( (Cycle setting means) 107-1 to 107-n (hereinafter referred to as cycle setting unit 107 unless otherwise required).

The output unit 106 is connected to the priority setting unit 104, the cycle setting unit 107, and the control unit 50. The output unit 106 receives an interrupt signal from the priority setting unit 104. When receiving the interrupt signal from the priority setting unit 104, the output unit 106 holds the interrupt signal as an interrupt status signal until the permission signal permits the output of the interrupt signal to the control unit 50.
Further, the output unit 106 outputs an interrupt signal to the control unit 50 when the permission signal permits the output of the interrupt signal to the control unit 50 when holding the interrupt status signal.
Here, the permission signal is a signal that permits an interrupt signal to be output to the control unit 50 for each period set by the period setting unit 107. Further, the period of the permission signal set by the period setting unit 107 becomes shorter as the priority corresponding to the mask circuit 105 is higher.

The period setting unit 107 is connected to the time measuring unit 103 and the output unit 106. The cycle setting unit 107 sets the cycle of the permission signal and outputs the permission signal to the output unit 106.
That is, if the mask circuit 105-1 corresponds to the highest priority among the mask circuits 105-1 to 105-n, the period set by the period setting unit 107-1 as the permission signal is It becomes the shortest cycle among the cycle setting units 107-1 to 107-n. If the mask circuit 105-n corresponds to the lowest priority among the mask circuits 105-1 to 105-n, the period set by the period setting unit 107-n as the permission signal is It becomes the longest cycle among the cycle setting units 107-1 to 107-n.

Next, the timing for outputting an interrupt signal when each mask circuit receives the interrupt signal will be described with reference to FIG. FIG. 6 is a timing chart showing the relationship between the priority set for the interrupt signal and the timing at which each mask circuit outputs the interrupt signal.
FIGS. 6 (1), (2), and (3) respectively show the relationship between the permission signal, the interrupt status signal, and the interrupt signal in the mask circuit 105-1, the mask circuit 105-2, and the mask circuit 105-n. .
In the present embodiment, description will be made assuming that the priority corresponding to the order of the mask circuit 105-1, the mask circuit 105-2, and the mask circuit 105-n is low.

  FIG. 6 (1) shows the relationship among the permission signal, interrupt status signal, and interrupt signal in the mask circuit 105-1. In the mask circuit 105-1, the permission signal permits the output of the interrupt signal at the period of T1. That is, the period setting unit 107-1 sets T1 as a period in which the permission signal permits the output of the interrupt signal. In this embodiment, the permission signal is prohibited when the signal level is HIGH (hereinafter abbreviated as HI), and output of the interrupt signal is prohibited, and when the signal level is LOW (hereinafter abbreviated as LO). Enables the output of an embedded signal. However, the permission signal may be configured to permit the output of the interrupt signal when the signal level is HI and to prohibit the output of the interrupt signal when the signal level is LO.

When the output unit 106-1 receives an interrupt signal from the priority setting unit 104, the output unit 106-1 holds the interrupt status signal. In FIG. 6 (1), the output unit 106-1 accepts an interrupt signal from the priority setting unit 104 at times a1, c, and f.
Even if the output unit 106 receives the interrupt signal from the priority setting unit 104, the output unit 106 controls the interrupt signal until the permission signal permits the output of the interrupt signal, that is, until the signal level of the permission signal becomes LO. The interrupt signal is held as an interrupt status signal without being output to the unit 50.
The output unit 106-1 accepts the interrupt signal at time a1, but since the signal level of the permission signal is HI, it does not output the interrupt signal to the control unit 50, and the signal level of the permission signal becomes LO. An interrupt signal is output to the controller 50 at the time b1. Similarly, output unit 106-1 receives an interrupt signal at time c and outputs the interrupt signal to control unit 50 at time d when the signal level of the permission signal becomes LO.
When the output unit 106-1 has not received an interrupt signal from the priority setting unit 104, the output unit 106-1 does not output the interrupt signal to the control unit 50 even if the signal level of the permission signal is LO.

FIG. 6B shows the relationship among the permission signal, the interrupt status signal, and the interrupt signal in the mask circuit 105-2. Since the priority corresponding to the mask circuit 105-2 is lower than the priority corresponding to the mask circuit 105-1, the permission signal of the mask circuit 105-2 is longer than the period T1 of the permission signal of the mask circuit 105-1. Interrupt signal output is permitted with a long period of T2.
When the output unit 106-2 receives the interrupt signal from the priority setting unit 104, the output unit 106-2 holds the interrupt status signal. In FIG. 6 (2), the output unit 106-2 accepts an interrupt signal from the priority setting unit 104 at times a2 and h.
The output unit 106-2 receives the interrupt signal at time a2, but outputs the interrupt signal to the control unit 50 at time b2 when the output of the permission signal becomes LO.
Similarly, output unit 106-2 receives an interrupt signal at time h, and outputs the interrupt signal to control unit 50 at time i when the signal level of the permission signal becomes LO.

FIG. 6 (3) shows the relationship among the permission signal, interrupt status signal, and interrupt signal in the mask circuit 105-n. In the mask circuit 105-n, the permission signal permits the output of the interrupt signal with a period of Tn longer than the period T2 of the mask circuit 105-2.
When the output unit 106-n receives the interrupt signal from the priority setting unit 104, the output unit 106-n holds the interrupt status signal. In FIG. 6 (3), the output unit 106-n receives an interrupt signal from the priority setting unit 104 at the time of a 3.
The output unit 106-n receives the interrupt signal at time a3, but outputs the interrupt signal to the control unit 50 at time b3 when the signal level of the permission signal becomes LO.

Next, the relationship between the priority of interrupt processing and the timing at which an interrupt signal is output to the control unit 50 will be described with reference to FIG.
In FIG. 6, the mask circuit 105-1, the mask circuit 105-2, and the mask circuit 105-n accept interrupt signals from the priority setting unit 104 at substantially the same times a1, a2, and a3.
However, in the mask circuit 105-1, since the cycle T1 in which the permission signal permits the output of the interrupt signal is shorter than the mask circuit 105-2 and the mask circuit 105-n, the mask circuit 105-1 has three masks. An interrupt signal is first output to the control unit 50 in the circuit. Next, the mask circuit 105-2 outputs an interrupt signal to the control unit 50 (b2), and then the mask circuit 105-n outputs an interrupt signal to the control unit 50 (b3).

  Further, between time A and time B indicated by a broken line in FIG. 6, the mask circuit 105-1 has a timing at which an interrupt signal can be output three times, and the mask circuit 105-2 has a timing at which an interrupt signal can be output. It can be seen that the timing at which the interrupt signal can be output is once in the mask circuit 105-n.

  That is, the mask circuit 105 increases the number of interrupt signals that can be output to the CPU 501 within a certain period as the corresponding priority increases. However, even if the mask circuit 105 receives the interrupt signal from the priority setting unit 104, the mask circuit 105 does not output the interrupt signal to the control unit 50 unless the permission signal permits the output of the interrupt signal. The number of interrupt signals received by the CPU 501 is limited.

As is apparent from the above description, according to the first embodiment, the mask circuit 105 limits the number of interrupt signals received by the CPU 501 within a certain period, so that the packet receiving unit 101 receives one packet. The frequency of requesting interrupt processing is reduced compared to the case where an interrupt signal is output to the CPU 501 every time, and the processing load on the CPU 501 is reduced. As a result, it is possible to reduce the occurrence of failures such as image cuts that cause the image forming apparatus 100 to form images in the image forming process and the display on the user interface provided in the image forming apparatus 100 being disturbed.
Further, as the corresponding priority of the mask circuit 105 increases, the number of interrupt signals that can be output to the CPU 501 increases within a certain period, so that the priority setting unit 104 is assigned to the mask circuit 105 corresponding to the priority. By outputting the interrupt signal, the probability that the high-priority packet data is interrupted by the CPU 501 is higher than the low-priority packet data.
More specifically, when the number of interrupt signals received by the CPU 501 is limited, packet data is stored in the RAM 502 until the CPU 501 receives the interrupt signal. In this case, if the priority is not set to the interrupt signal, the CPU 501 performs only the interrupt processing of the low priority packet data and executes the interrupt processing of the high priority packet data. There is a possibility that the transferred packet data exceeds the memory capacity of the RAM 502 and packet data having a high processing priority is discarded.
On the other hand, when priority is set for the interrupt signal, since the interrupt signal is output more frequently for the packet data having a high interrupt processing priority than the packet data having a low priority, the CPU 501 is interrupted. The probability of being processed is increased.

  In the first embodiment, the cycle setting unit 107 permits the output of the interrupt signal for each cycle regardless of the presence or absence of the interrupt signal, but sets the cycle after the output of the interrupt signal and outputs the permission signal. You may make it start.

  Since the system configurations of the image forming apparatus 100, the control unit 50, the communication control unit 10, and the interrupt control unit 102 are the same as those in the first embodiment, description thereof is omitted. Here, an interrupt signal is transmitted with reference to FIG. A configuration in which the cycle setting unit starts outputting the permission signal after output will be described with reference to a time chart.

FIG. 7 shows the permission signal in each mask circuit when the configuration of the second embodiment is applied to the mask circuit 105-1, and the configuration of the first embodiment is applied to the mask circuit 105-2 and the mask circuit 105-n. 5 is a timing chart showing the relationship between an interrupt status signal and an interrupt signal.
Also in the second embodiment, description will be made assuming that the priority corresponding to the order of the mask circuit 105-1, the mask circuit 105-2, and the mask circuit 105-n is low.

FIG. 7A shows a relationship among the permission signal, the interrupt status signal, and the interrupt signal in the mask circuit 105-1.
In the mask circuit 105-1, the period setting unit 107 sets the signal level of the permission signal to LO and sets the interrupt signal when the interrupt signal is not output from the output unit 106-1, even if a predetermined time has elapsed. Allow output of.
When receiving the interrupt signal (a1), the output unit 106-1 outputs the interrupt signal to the control unit 50 (b1) because the signal level of the permission signal is LO.
When the output unit 106-1 outputs an interrupt signal, the cycle setting unit 107-1 sets a cycle in the permission signal. The permission signal permits the control unit 50 to output an interrupt signal at a cycle T1.

  After the permission signal permits the output of the interrupt signal to the control unit 50 in the cycle T1, the output unit 106-1 receives the interrupt signal (c), but the signal level of the permission signal is LO. The interrupt signal is not output until becomes. Then, the output unit 106-1 outputs an interrupt signal when the signal level of the permission signal becomes LO (d). Similarly, the output unit 106-1 receives an interrupt signal (f), and outputs an interrupt signal when the signal level of the permission signal is LO (g).

  The cycle setting unit 107-1 sets the cycle when the output unit 106-1 does not output an interrupt signal when one cycle has elapsed after the output unit 106-1 outputs the interrupt signal. Is stopped, the output of the permission signal is set to LO, and the output of the interrupt signal is permitted. Note that the timing at which the cycle setting unit 107-1 stops setting the cycle and sets the output of the permission signal to LO is not limited to the present embodiment, and is, for example, two cycles, three cycles, or predetermined. When the time elapses, the setting of the cycle may be stopped.

  The timing charts of the mask circuit 105-2 and the mask circuit 105-n shown in FIGS. 7 (2) and 7 (3) are the same as the timing charts described in FIGS. 6 (1) and 6 (2). Therefore, the description is omitted.

As is clear from the above description, according to the second embodiment, when the interrupt signal is not output from the output unit 106-1 even after a predetermined time has elapsed, the cycle setting unit 107 outputs the permission signal. Set to LO to enable interrupt signal output. Therefore, when the output unit 106 receives the interrupt signal, it immediately outputs the interrupt signal to the control unit 50. Therefore, when the CPU 501 is not executing an interrupt process and the processing load is low, the CPU 501 can cause the CPU 501 to execute the interrupt process as soon as the packet reception unit 101 receives the packet data. In addition, after the interrupt signal is output, the mask circuit 105 limits the number of interrupt signals received by the CPU 501 within a certain period, so that the packet receiving unit 101 receives an interrupt signal every time it receives one packet. The frequency of requesting interrupt processing is reduced compared to the case of outputting an interrupt signal, and the processing load on the CPU 501 is reduced. As a result, it is possible to reduce the occurrence of failures such as image cuts that cause the image forming apparatus 100 to form images in the process of image formation or the display of the user interface provided in the image forming apparatus 100 being disturbed.
Further, as the corresponding priority of the mask circuit 105 increases, the number of interrupt signals that can be output to the CPU 501 increases within a certain period, so that the priority setting unit 104 is assigned to the mask circuit 105 corresponding to the priority. By outputting the interrupt signal, the probability that the high-priority packet data is interrupted by the CPU 501 is higher than the low-priority packet data.

The embodiment described above is one of the embodiments of the present invention. However, the present invention is not limited to this, and various modifications can be made without departing from the scope of the present invention.
In the first and second embodiments, the priority corresponding to the order of the mask circuit 105-1, the mask circuit 105-2,..., And the mask circuit 105-n is low. The circuit 105-2,..., And the mask circuit 105-n may be configured so that the priority becomes higher in the order. Alternatively, the priority of the mask circuit 105 can be changed by changing the period set by the period setting unit 107.
In addition, part or all of the configurations of the priority setting unit 104 and the mask circuit 105 may be realized by software processing within a range that does not affect the arithmetic processing executed by the CPU 501.

DESCRIPTION OF SYMBOLS 10 ... Communication control part 20 ... Image input part 30 ... Image processing part 40 ... Image output part 50 ... Control part 100 ... Image forming apparatus 101 ... Packet receiving part 102 ... Interrupt control part 103 ... Time measuring part 104 ... Priority setting part 105, 105-1, 105-2, 105-n ... mask circuits 106, 106-1, 106-2, 106-n ... output units 107, 107-1, 107-2, 107-n ... priority setting units 200 ... Terminal device 300 ... Image reading device 400 ... Network 501 ... CPU
502 ... RAM
503 ... ROM
504 ... Input / output unit

Claims (4)

A priority setting means for accepting an interrupt signal for requesting an interrupt processing to the arithmetic device and setting a priority according to the interrupt processing to be executed by the arithmetic device based on the received interrupt signal in the interrupt signal; ,
A period setting means for setting a period of a permission signal that permits output of the interrupt signal to the arithmetic unit according to the priority;
Based on the interrupt signal and the permission signal, output means for outputting the interrupt signal to the arithmetic unit;
An interrupt control device comprising:   The interrupt control apparatus according to claim 1, wherein the cycle setting unit starts setting the cycle after the output unit outputs an initial interrupt signal. A computing device for performing computations;
Priority setting means for accepting an interrupt signal for requesting an interrupt process to the arithmetic device, and setting a priority corresponding to the interrupt process to be executed by the arithmetic device based on the accepted interrupt signal in the interrupt signal When,
According to the priority, a cycle setting means for setting a cycle of a permission signal that permits output of the interrupt signal to the arithmetic device;
An image forming apparatus comprising: an output unit that outputs the interrupt signal to the arithmetic unit based on the interrupt signal and the permission signal.   The image forming apparatus according to claim 3, wherein the cycle setting unit starts setting the cycle after the output unit outputs an initial interrupt signal.

Images