JP2013243509A - Communication apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a communication apparatus that satisfies time requirements necessary for a Modbus communication in a RTU mode even when a CPU having low processing capacity to a communication speed is used.SOLUTION: A control circuit (a CPU 11 and an external circuit 17): based on outputs of comparison circuits 172, 173, 174 monitoring a predetermined first time (CTO), second time (FTO), and third time (RTO), respectively from a count value of a timer counter circuit 171 when a reception interval of unit data in the frame exceeds the first time and the unit data is received within the second time, discards the unit data in a target communication frame; and transmits a response frame within the third time each time the communication frame is received in a normal time interval.

Description

  The present invention relates to a communication apparatus, and more particularly to a communication apparatus that satisfies a time rule using UART in Modbus communication in an RTU mode.

  A network that implements the Modbus protocol as a communication protocol is referred to as Modbus (registered trademark). Modbus is a communication protocol developed by Modicon for its PLC (Programmable Logic Controller). Modbus (registered trademark) is currently a de facto standard communication protocol in the industry, and is widely used as a means for connecting field devices to which sensors and the like are connected to a relatively small network. (World Wide Web) Published on the page.

  For example, Patent Document 1 discloses a configuration example of a Modbus control system that connects a host system such as DCS (Distributed Control System) or SCADA (Supervisory Control And Data Acquisition) and a control device such as PLC. Modbus communication includes an ASCII mode and an RTU (Remote Terminal Unit) mode. Regarding the ASCII mode, the protocol at the physical layer level is equivalent to UART (Universal Asynchronous Receiver Transmitter).

  On the other hand, communication in the RTU mode has three time rules: CTO (Character Time Out) or less, FTO (Frame Time Out) or more, and RTO (Response Time Out) or less. Specifically, as shown in FIG. 3, the time interval between data (characters) in a communication frame (here, a received frame) is CTO, and the time interval between the last character of the communication frame and the first character of the following communication frame is FTO. When the time interval from receiving the communication frame to transmitting the response frame is RTO, the data (character) in one received frame is received within the CTO time, and the data (character) between the received frames is It is necessary to satisfy three time rules, such as reception exceeding the FTO time and transmission of a response frame within the RTO time.

  For this reason, for example, as shown in FIG. 4, the reception frame # 1 and the reception frame #, which are target communication frames received within the FTO time when the time interval between characters as unit data of the communication frame exceeds the CTO time. 2 must be discarded. As shown in FIG. 5, it is necessary to transmit a response frame (response frame # 1) within the RTO time after receiving the communication frame (reception frame # 1). Here, the response frame is received within the RTO time. The response frame (response frame # 1) is not transmitted when the time rule for transmitting the message cannot be satisfied (timeout occurs). Therefore, it is necessary to retransmit the transmission side on the assumption that the previously transmitted communication frame was not normally received.

  FIG. 6 shows a configuration example of a conventional communication apparatus 100 using UART for performing Modbus communication. The communication device 100 shown in FIG. 6 includes a bus in which a CPU 110 and peripheral LSIs such as a memory 120, a UART 130, an interrupt control circuit 140, and a register interface circuit 150 are configured with a plurality of lines for address, data, and control. 180 is commonly connected.

  The UART 130 is further connected to an external communication interface circuit 160 and transmits / receives a communication frame to / from the outside via the external communication interface circuit 160. The interrupt control circuit 140 outputs an FTO excess interrupt signal to the CPU 110 when the set FTO time is exceeded. The interrupt control circuit 140 includes a timer counter circuit 171 and an FTO setting excess comparison circuit 172. An external circuit 170 is connected. Further, the register interface circuit 150 is assigned with an FTO setting register 151 in which values are set (written) in a programmable manner by the CPU 110, and a time measurement enable register 152, and a predetermined value is held here.

  Here, the operation of Modbus communication in the conventional RTU mode will be described with reference to FIG. First, the CPU 110 sets the FTO time in the FTO setting register 151 via the bus 180. Subsequently, the CPU 110 sets a time measurement enable value “1” in the time measurement enable register 152. As a result, the FTO setting register 151 can output the FTO setting value to the FTO setting excess comparison circuit 172. In addition, the time measurement enable register 152 outputs the set time measurement enable value “1” to the FTO setting excess comparison circuit 172.

  On the other hand, when the external communication interface circuit 160 receives a communication frame from the outside, the external communication interface circuit 160 transfers the received signal to the UART 130, and the UART 130 stores the received frame in a buffer containing the received frame. Also, an interrupt signal is output to the CPU 110 as necessary. When the CPU 110 receives the interrupt signal, the CPU 110 moves the received frames stored in the built-in buffer of the UART 130 to the memory 120 via the bus 180.

  When the UART 130 detects the start bit of the character in the communication frame from the received signal, it outputs a start bit detection signal to the timer counter circuit 171, and the timer counter circuit 171 clears the internal counter every time it receives the start bit detection signal. The count up operation is started. When the counter value reaches the maximum value, the timer counter circuit 171 stops the count-up operation while holding the maximum value. During this time, the timer counter circuit 171 outputs the value of the internal counter to the FTO setting excess comparison circuit 172 as the count value.

  Only when the time measurement enable signal is “1”, the FTO setting excess comparison circuit 172 sets “0” indicating that the FTO signal is within the FTO time to the interrupt control circuit 140 when the count value ≦ the FTO setting value. Output. On the other hand, when the count value> the FTO set value, “1” indicating that the FTO time is exceeded is output to the interrupt control circuit 140 as the FTO signal. When the time measurement enable signal is “0”, “0” indicating that it is within the FTO time is always output to the interrupt control circuit 140 as the FTO signal. When the interrupt control circuit 140 detects a change of the FTO signal from “0” to “1”, the interrupt control circuit 140 outputs the FTO interrupt signal “1” to the CPU 110. Further, the interrupt control circuit 140 clears the FTO interrupt signal (“0”) by register write from the CPU 110.

  When the communication device 100 receives a communication frame from the outside, the external communication interface circuit 160 outputs the received signal to the UART 130 as a reception signal. In response to this, the UART 130 accumulates the received data in the built-in buffer, issues an interrupt to the CPU 110 as necessary, and the CPU 110 moves the data accumulated in the UART 130 to the memory 120 from the interrupt. Further, when the UART 130 detects the start bit of the character from the received signal, it outputs “1” as the start bit detection signal.

  Each time the timer counter circuit 171 receives the start bit detection signal, the timer counter circuit 171 clears the internal counter and starts a count-up operation. The timer counter circuit 171 uses the value of the internal counter as a count value. Output to the FTO setting excess comparison circuit 172. When the FTO setting excess comparison circuit 172 detects the count value> FTO setting value, it outputs “1” indicating that the FTO time is exceeded to the interrupt control circuit 140. Thereby, the FTO time is detected.

  When detecting the change of the FTO signal from “0” to “1”, the interrupt control circuit 140 outputs “1” to the CPU 110 as the FTO interrupt signal. The CPU 110 detects the FTO time excess by detecting “1” of the FTO interrupt signal, and executes a response frame transmission process. Note that details regarding the transmission processing are not directly related to the present invention, and thus description thereof is omitted. With the above operation, transmission of a response frame that satisfies the FTO time can be realized.

JP 2011-234171 A

  As described above, in Modbus communication in the conventional RTU mode using UART, a reception timeout detection mechanism is provided by the external circuit 170 configured by the timer counter circuit 171 and the FTO setting excess comparison circuit 172. For this reason, it is possible to set the FTO time and to detect the FTO set time exceeding, but it is not possible to detect the CTO and RTO set time exceeded. Therefore, the reception error shown in FIG. 4 and the error shown in FIG. There is a problem that the response frame timeout processing cannot be realized accurately.

  Currently, the CPU 110 having a sufficiently high processing capacity with respect to the communication speed is used. As a result, the above time rule is satisfied, but it is unclear whether the time rule is actually satisfied correctly. In addition, when the CPU 110 having a low processing capability is used for the purpose of reducing the power consumption of the field device, it is difficult to satisfy the respective time rules. Furthermore, there is an example in which a plurality of timeout settings can be made, but only the detection mechanism is mounted, and communication frame processing may not be performed correctly when transmission / reception and timeout timing conflict.

  The present invention has been made to solve the above-described problems, and provides a communication apparatus that satisfies the time regulation necessary for Modbus communication in the RTU mode even when a CPU having a low processing capacity with respect to the communication speed is used. The purpose is to do.

  In order to solve the above-described problem, the present invention sets the time interval between predetermined unit data in a communication frame to a first time, between the last unit data of the communication frame and the first unit data of the following communication frame. When the time interval is the second time, and the time from when the communication frame is received until the response frame is transmitted is the third time, the reception of the unit data in the communication frame is the first time The communication apparatus is configured to receive the unit data between the communication frame and the subsequent communication frame within the time, and transmit the response frame within the third time exceeding the second time. A timer counter circuit that starts counting each time a start bit of each unit data in the received frame is detected, and a count of the timer counter circuit From the comparison circuit that monitors each of the first time, the second time, and the third time set in advance, and the time interval at which the unit data in the frame is received by the output of the comparison circuit When the unit data exceeds the first time or is received within the second time, the unit data in the target communication frame is discarded and each time the communication frame is received, And a control circuit for transmitting the response frame.

  According to the present invention, the control circuit monitors each of the preset first time (CTO), second time (FTO), and third time (RTO) from the count value of the timer counter circuit. When the reception interval of the unit data in the frame exceeds the first time and is received within the second time due to the output of the comparison circuit, the unit data in the target communication frame is discarded and discarded. Each time a communication frame that has not been received is received, a response frame is transmitted within the third time. In this way, even when a CPU having a low processing capability with respect to the communication speed is used by monitoring the time rule necessary for Modbus communication in the RTU mode and discarding unnecessary transmission / reception data when a time rule violation is detected, A communication device that satisfies the time rules required for Modbus communication can be realized. Also, a commercially available UART can be used with only a small amount of hardware added, and implementation of the RTU mode in Modbus communication can be realized while improving quality and improving development efficiency.

  In the present invention, “a timer counter circuit that counts each time a start bit of unit data in a received communication frame is detected” corresponds to, for example, the timer count circuit 171 of the external circuit 17 shown in FIG. The “comparison circuit for monitoring each of the first time, the second time, and the third time set in advance from the count value of the timer counter circuit” is, for example, the external circuit shown in FIG. This corresponds to the CTO setting excess comparison circuit 173, the FTO setting excess comparison circuit 172, and the RTO setting excess comparison circuit 174 of the circuit 17, respectively. Further, “if the output of the comparison circuit causes the unit data reception interval of the unit data in the frame to exceed the first time and is received within the second time, the unit data in the target communication frame is The control circuit that transmits the response frame within the third time each time it is discarded and received without discarding the communication frame is, for example, the interrupt control circuits 14, 21, and 22 shown in FIG. , 23, the error frame detection circuit 175 of the external circuit 17, the reception mask circuit 176, and the CPU 11 operate in cooperation.

  The present invention further includes an interrupt control circuit, wherein the control circuit receives a first time excess detection signal, a second time excess detection signal output from the comparison circuit, and unit data in the communication frame. When an error frame is detected after the first time is exceeded and before the second time is exceeded by a completion detection signal, the interrupt control circuit is activated, and based on the interrupt processing request from the interrupt control circuit, Until the second time is exceeded, the unit data in the communication frame received thereafter is discarded or a process of not receiving is executed. According to the present invention, in addition to the second time setting exceeded, the first time setting exceeded, the third time setting exceeded, and even the detection of an error frame is processed by interruption, so that the control circuit handles these. Since it is not necessary to constantly monitor, the processing load is reduced. Therefore, the control circuit can be realized by a CPU having a low processing capability.

  In the present invention, the control circuit restricts transmission of unit data to the outside in the communication frame based on a third time excess detection signal output from the comparison circuit. According to the present invention, since there are fewer opportunities to transmit unnecessary data, the processing load on the control circuit can be reduced accordingly.

  In the present invention, it further comprises a memory and a DMA controller, and the control circuit creates a response frame and stores it in the memory when the comparison circuit outputs the first excess time detection signal. If the error frame is not detected when the second time excess detection signal is output by the comparison circuit, a response frame transmission request is output to the DMA controller. According to the present invention, when a CPU having a short time difference between the second time setting and the third time setting and having insufficient processing capacity for the time specification is used for the control circuit, the control circuit causes the first time excess. Response frame transmission is started by creating a response frame at the time of detection and storing it in the memory, and starting the DMA controller at the second time excess detection time to transfer transmission data from the memory. The efficiency of the process can be realized.

  In the present invention, a register interface circuit is further provided, and the control circuit controls the validity / invalidity of each time monitoring by the comparison circuit by writing a constant value in a predetermined register assigned to the register interface circuit. It is characterized by that. According to the present invention, it is possible to cope with a case where there is no time regulation by individually enabling control of each time monitoring for the comparison circuit by the register interface circuit.

  According to the present invention, it is possible to provide a communication device that satisfies the time regulation necessary for Modbus communication in the RTU mode even when a CPU having a low processing capacity with respect to the communication speed is used.

It is a block diagram which shows the structure of the communication apparatus which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the communication apparatus which concerns on Embodiment 2 of this invention. It is the figure quoted in order to demonstrate the time regulation of Modbus communication by RTU mode. It is the figure quoted in order to demonstrate the reception error of Modbus communication by RTU mode. It is the figure quoted in order to demonstrate the response timeout of Modbus communication by RTU mode. It is a block diagram which shows the structure of the conventional communication apparatus which performs Modbus communication by RTU mode.

  Hereinafter, an embodiment for carrying out the present invention (hereinafter simply referred to as the present embodiment) will be described in detail with reference to the accompanying drawings.

(Configuration of Embodiment 1)
FIG. 1 is a block diagram illustrating a configuration of a communication device 10 according to the first embodiment. As shown in FIG. 1, the communication apparatus 10 according to the first embodiment has interrupt control circuits 21, 22, and 23 added as peripheral LSIs to the communication apparatus 100 that performs Modbus communication in the conventional RTU mode shown in FIG. Further, a small amount of hardware is added to the external circuit 170 included in the conventional communication device 100 to indicate the external circuit 17, and the number of registers assigned to the register interface circuit 150 is increased to indicate the register interface circuit 15. .

  Specifically, in the communication apparatus 10 according to the first embodiment, the CPU 11 and the peripheral LSI including the memory 12, the UART 13, the interrupt control circuits 14, 21, 22, 23, and the register interface circuit 15 include addresses, data, and control. Are commonly connected via a bus 18 composed of a plurality of lines. The UART 13 is further connected to the external communication interface circuit 16 and transmits / receives a communication frame to / from the outside via the external communication interface circuit 16.

  The interrupt control circuit 14 outputs an FTO excess interrupt signal to the CPU 11 when the set FTO time is exceeded, and an external circuit 17 is connected to the interrupt control circuit 14. When receiving an error frame, the interrupt control circuit 21 outputs an error frame interrupt signal to the CPU 11, and an external circuit 17 is connected to the interrupt control circuit 21. The interrupt control circuit 22 outputs a CTO excess interrupt signal to the CPU 11 when the set CTO time is exceeded, and an external circuit 17 is connected to the interrupt control circuit 22. The interrupt control circuit 23 outputs an RTO excess interrupt signal to the CPU 11 when the set RTO is exceeded, and an external circuit 17 is connected to the interrupt control circuit 23.

  In addition to the timer counter circuit 171 and the FTO setting excess comparison circuit 172, the external circuit 17 includes a CTO setting excess comparison circuit 173, an RTO setting excess comparison circuit 174, an error frame detection circuit 175, a reception mask circuit 176, and a transmission mask circuit 177. It is comprised including. In addition to the FTO setting register 151 and the time measurement enable register 152, a CTO setting register 153, an RTO setting register 154, and a counter clear register 155 are newly assigned to predetermined areas in the register interface circuit 15. Here, a predetermined value is written by the CPU 11 in a programmable manner.

  According to FIG. 1, the CTO setting excess comparison circuit 173 includes a count value counted by the timer counter circuit 171, a value set in the CTO setting register 153, and a value set in the time measurement enable register 152. The output is input to the error frame detection circuit 175 and the interrupt control circuit 22 that issues an interrupt for exceeding the CTO setting. The RTO setting excess comparison circuit 174 receives the count value counted by the timer counter circuit 171, the value set in the RTO setting register 154, and the value set in the time measurement enable register 152. The output is configured to be output to the transmission mask circuit 177 and the interrupt control circuit 23 that issues an interrupt for exceeding the RTO setting.

  When the error frame detection circuit 175 detects an error frame, the error frame detection circuit 175 notifies the interrupt control circuit 21 and the reception mask circuit 176 of this. When the reception mask circuit 176 obtains a reception signal from the external communication interface circuit 16 and receives an error frame detection signal from the error frame detection circuit 175, under the control of the CPU 11, characters in the received communication frame before the FTO excess is received. Perform processing that discards or does not receive data. Specifically, the CPU 11 executes a process of discarding data that has already been received and transferred to the memory 12 or data stored in a buffer (not shown) built in the UART 13, or the reception mask circuit 176 A process for not receiving data after the occurrence of an error frame is executed. The transmission mask circuit 177 acquires transmission data from the UART 13 and restricts transmission of character data in the communication frame to the outside by the RTO signal of the RTO setting excess comparison circuit 174 under the control of the CPU 11.

(Operation of Embodiment 1)
Hereinafter, the operation of the communication apparatus 10 according to the first embodiment will be described in detail. First, the operation at the time of normal frame transmission / reception will be described. First, the CPU 11 sends “character time + CTO time” to the CTO setting register 153 of the register interface circuit 15, “character time + FTO time” to the FTO setting register 151, and “character time” to the RTO setting register 154 via the bus 18. Set "Time + RTO time". The CPU 11 also sets a value (“1”) that permits time measurement to the time measurement enable register 152 via the bus 18.

  On the other hand, when receiving a communication frame from the outside, the external communication interface circuit 16 generates a reception signal and outputs it to the timer counter circuit 171 and the reception mask circuit 176 of the external circuit 17. When the reception mask circuit 176 receives the reception signal, the reception mask circuit 176 outputs the reception data to the UART 13. The UART 13 stores the received data in a built-in buffer. Further, the UART 13 issues an interrupt to the CPU 11 as necessary, and the CPU 11 that has received the interrupt moves the data accumulated in the UART 13 from the interrupt to the memory 12 via the bus 18.

  Whenever the timer counter circuit 171 detects the start bit of the character from the received signal, the timer counter circuit 171 clears the internal counter and starts the count-up operation. When the counter value reaches the maximum value, the timer counter circuit 171 stops counting up while maintaining the maximum value. The timer counter circuit 171 outputs the value of the internal counter to the CTO setting excess comparison circuit 173, the FTO setting excess comparison circuit 172, and the RTO setting excess comparison circuit 174.

  Here, when the time measurement enable signal is “1” and the count value ≦ the CTO setting value, the CTO setting excess comparison circuit 173 sets “0” (below the CTO time) as the CTO signal indicating that it is within the CTO time. Is output to the interrupt control circuit 22 and the error frame detection circuit 175. On the other hand, when the count value> CTO setting value, “1” is output to the interrupt control circuit 22 and the error frame detection circuit 175 as a CTO signal (first time excess detection signal) indicating the CTO time excess. When the time measurement enable signal is “0”, “1” is always output as the CTO signal. When the CTO signal changes from “0” to “1”, the interrupt control circuit 22 outputs “1” to the CPU 11 as the CTO interrupt signal. The interrupt control circuit 22 clears (“0”) the CTO interrupt signal by register write from the CPU 11.

  When the CTO setting excess comparison circuit 173 detects the elapse of character time + CTO time from the received frame (start bit), “1” is output to the CTO interrupt signal via the interrupt control circuit 22. By detecting the CTO interrupt signal, the CPU 11 recognizes that the CTO time has been exceeded and starts preparation for transmitting a response frame. Even after the CTO time has elapsed, the internal counter of the timer counter circuit 171 continues to count up.

  Further, the FTO setting excess comparison circuit 172 sends the FTO signal to the interrupt control circuit 14 and the error frame detection circuit 175 within the FTO time as the FTO signal when the time measurement enable signal is “1” and the count value ≦ the FTO setting value. “0” is output to indicate that On the other hand, when the count value> the FTO set value, “1” indicating that the FTO time is exceeded is output to the interrupt control circuit 14 and the error frame detection circuit 175 as the FTO signal (second time excess signal). When the time measurement enable signal is “0”, “0” is always output as the FTO signal.

  When detecting the change of the FTO signal from “0” to “1”, the interrupt control circuit 14 outputs “1” to the CPU 11 as the FTO interrupt signal. The interrupt control circuit 14 clears the FTO interrupt signal (“0”) by register write from the CPU 11. Thus, the passage of “character time + FTO time” is detected from the received frame (start bit), and “1” is output to the CPU 11 as an FTO interrupt signal via the above-described circuit. The CPU 11 detects that the FTO time is exceeded by detecting “1” of the FTO interrupt signal, starts a response frame transmission process, and transfers the response frame to the UART 13. Even after the FTO time has elapsed, the internal counter of the timer counter circuit 171 continues to count up.

  Subsequently, the UART 13 outputs the transmission data to the transmission mask circuit 177 and the timer counter circuit 171 using the response frame as transmission data. The transmission mask circuit 177 generates a transmission signal from the transmission data and transmits a response frame to an external device (not shown) via the external communication interface circuit 16. The timer counter circuit 171 detects the start bit of the transmission data and stops the operation of the internal counter.

  When the time measurement enable signal is “1” and the count value ≦ the RTO setting value, the RTO setting excess comparison circuit 174 outputs “0” indicating that it is within the RTO time to the interrupt control circuit 23. When the count value> the RTO set value, “1” indicating that the RTO time is exceeded is output to the interrupt control circuit 23 as the RTO signal (third time exceeded signal). When the time measurement enable signal is “0”, “0” is always output to the interrupt control circuit 23 as the RTO signal.

  When the response frame is normally transmitted, the internal counter value of the timer counter circuit 171 stops within “character time + RTO time”, so that the RTO time is output as the RTO signal output from the RTO setting excess comparison circuit 174. “0” indicating that it is within the range is output. The interrupt control circuit 23 outputs “1” to the CPU 11 as an RTO interrupt signal when detecting the change of the RTO signal from “0” to “1”. Here, since the operation is performed at the time of normal frame transmission / reception, the RTO signal is “0” and the RTO interrupt signal is also “0”, so no interrupt is generated.

  Next, the operation when receiving an error frame will be described. When the CTO time has passed and the FTO time is not reached, the CTO setting excess comparison circuit 173 outputs the CTO signal “1”, and the FTO setting excess comparison circuit 172 outputs the FTO signal “0”. At this time, when the error frame detection circuit 175 detects the character (start bit) of the reception signal with the CTO signal being “1” and the FTO signal being “0”, the interrupt control circuit 21 and the reception mask circuit 176 are detected. "1" is output as an error frame detection signal. Once “1” is output as the error frame detection signal, the output of “1” is continued as the error frame detection signal until the FTO signal “1” is detected (“0” when the FTO signal “1” is detected). Is output).

  The interrupt control circuit 21 outputs “1” as an error frame interrupt signal when detecting a change from “0” to “1” of the error frame detection signal. The interrupt control circuit 21 clears the error frame interrupt signal (“0”) by register write from the CPU 11. The CPU 11 detects the generation of an error frame by detecting the error frame interrupt signal “1”, discards the error frame, and does not execute response frame transmission.

  The reception mask circuit 176 that has detected the error frame detection signal “1” discards the reception frame based on the reception signal while the error frame detection signal is “1”, that is, does not transfer the reception data to the UART 13. As a result, acquisition of received data after error frame detection can be restricted.

  Next, an operation at the time of detecting a response frame timeout will be described. Here, assuming that the RTO time exceeded is detected, “1” indicating the RTO time exceeded is output to the interrupt control circuit 23 as the RTO signal. When the interrupt control circuit 23 detects a change of the RTO signal from “0” to “1”, it outputs an RTO interrupt signal “1” to the CPU 11. The interrupt control circuit 23 clears the RTO interrupt signal (“0”) by register write from the CPU 11.

  The CPU 11 detects that the RTO time has been exceeded by detecting “1” of the RTO interrupt signal, and cancels if the response frame transmission process is being executed.

  When the transmission mask circuit 177 detects the RTO signal “1” (RTO time exceeded), the transmission data from the UART 13 is discarded and output to the external communication interface circuit 16 while the RTO signal is “1”. Is not generated. By this process, even when the response frame has already been transferred from the CPU 11 to the UART 13, it is avoided that the transmission data is output as an external communication signal after the RTO time has elapsed. The CPU 11 detects that the buffer (for transmission) built in the UART 13 is empty, and confirms that a response frame that should not be transmitted has been discarded after the RTO time has elapsed.

  The CPU 11 writes the counter clear data to the counter clear register 155 via the bus 18. When the counter clear register 155 detects writing of the counter clear data, it outputs “1” to the timer counter circuit 171 as a counter clear request. When the timer counter circuit 171 detects the counter clear signal “1”, the timer counter circuit 171 clears the counter built in the timer counter circuit 171 (zero setting). This operation returns the entire circuit to the idle state.

(Effect of Embodiment 1)
The communication device 10 according to the first embodiment described above uses the first time interval (CTO) as the time interval between predetermined unit data (for example, characters) in a communication frame (for example, predetermined length character data). The time interval between the last unit data of the frame and the first unit data of the following communication frame is the second time (FTO), and the time interval from the reception of the communication frame to the transmission of the response frame is the third time interval. In the case of time (RTO), the reception of the unit data in the communication frame is within the first time, the reception of the unit data between the communication frame and the subsequent communication frame exceeds the second time, This is applied to the communication apparatus 10 that needs to satisfy the time rule for transmitting the response frame within the time of 3. In this communication apparatus 10, the control circuit monitors each of the preset first time (CTO), second time (FTO), and third time (RTO) from the count value of the timer counter circuit 171. By the outputs of the comparison circuits 172, 173, and 174, the unit data reception interval in the communication frame exceeds the first time and is received within the second time. Each time the unit data is discarded and the communication frame is received without discarding, the response frame is transmitted within the third time. Therefore, for example, the CPU 11 that detects the time rule required for Modbus communication in the RTU mode and discards unnecessary transmission / reception data when this time rule violation is detected, and the external circuit 17 that operates in cooperation with the CPU 11. By realizing the control circuit described above with (control circuit), even when the CPU 11 having a low processing capacity with respect to the communication speed is used, a circuit that satisfies the time regulation required for Modbus (RTU mode) communication is realized. be able to.

(Configuration of Embodiment 2)
FIG. 2 is a block diagram illustrating a configuration of the communication apparatus 10 according to the second embodiment. A difference in configuration from the first embodiment shown in FIG. 1 is that a load is reduced on the CPU 11 by further connecting a DMA (Dynamic Memory Access) controller 24 to the bus 18. Therefore, a DMAC activation control circuit 178 that activates the DMA controller 24 is added to the external circuit 17. The DMAC activation control circuit 178 is connected to the output of the FTO setting excess comparison circuit 172 and the output of the error frame detection circuit 175.

  Further, as a response to the case where there is no time regulation (the set time is ∞), the register interface circuit 15 has the RTO measurement enable register 152a, the FTO measurement enable register 152b, and the CTO measurement enable register 152c instead of the time measurement enable register 152. Each is assigned, and each time measurement can be individually turned ON / OFF.

(Operation of Embodiment 2)
When the CPU processing capacity is sufficiently high with respect to the generation time regulation of the DMA controller activation signal, there is no problem with the configuration of the first embodiment shown in FIG. 1, but the CPU 11 has a short time difference between the FTO time and the RTO time, and the processing capacity It is conceivable to use a type that lacks. In this case, the CPU 11 starts creating a response frame when the CTO time is detected and stores it in the memory 12 in advance, starts the DMA controller 24 when the FTO time is detected, and transfers transmission data from the memory 12 to the UART 13. By providing the mechanism, it is possible to realize the efficiency of processing up to response frame transmission.

  Specifically, when the UART 13 receives the communication frame and the CTO setting excess comparison circuit 173 detects the CTO setting excess, the interrupt control circuit 22 asserts the CTO interrupt signal. Receiving this, the CPU 11 generates a response frame corresponding to the received communication frame and stores it in a predetermined area of the memory 12. Next, when the FTO setting excess comparison circuit 172 detects that the FTO setting is exceeded, an FTO signal “1” is generated, and this FTO signal is output to the DMAC activation control circuit 178 of the external circuit 17 in addition to the interrupt control circuit 14. Is done. In addition, an error frame detection signal is also input from the error frame detection circuit 175 to the DMAC activation control circuit 178.

  When the FTO signal is “1” and the error frame detection signal is “0”, the DMAC activation control circuit 178 outputs “1” as the DMAC activation signal and activates the DMA controller 24. When the error frame detection signal is “1”, “0” is output as the DMAC activation signal, and the DMA controller 24 is not activated. That is, the external circuit 17 activates the DMA controller 24 when no error frame is detected, and does not activate the DMA controller 24 when an error frame is detected.

  When the DMA controller 24 detects “1” of the DMAC activation signal output by the DMA activation control circuit 178 of the external circuit 17, the CPU 11 reads out the response frame generated in advance and stored in the memory 12 from the memory 12. Transfer to UART13. As a result, even when the set time difference between the FTO time and the RTO time is short and the processing capacity of the CPU 11 is insufficient, the processing efficiency up to the response frame transmission can be improved.

  On the other hand, when there is no time regulation (set time ∞), the CPU 11 stores the RTO measurement enable register 152a, the FTO measurement enable register 152b, and the CTO measurement enable register 152c assigned to a predetermined area of the register interface circuit 15. On the other hand, “0” is set. As a result, the FTO signal and the RTO signal are not asserted (always “0” output and the CTO signal is always “1” output), and the operation based on the time specification does not occur, so there is no time specification. Can be realized.

(Effect of Embodiment 2)
According to the communication device 10 according to the second embodiment described above, the CPU 11 that has a short time difference between the second time setting (FTO) and the third time setting (RTO) and has insufficient processing capacity with respect to the time specification is provided as a control circuit. The control circuit starts generating a response frame at the time when the first time excess is detected and stores it in the memory 12, and activates the DMA controller 24 at the time when the second time excess is detected. By adopting a configuration in which transmission data is transferred from the memory 12, the efficiency of processing up to response frame transmission can be realized. When the register interface circuit 15 performs enable control individually for the FTO setting excess comparison circuit 172, the CTO setting excess comparison circuit 173, and the RTO setting excess comparison circuit 174, and there is no time regulation. Can also respond.

  As described above, according to the present invention, it is possible to provide the communication device 10 that satisfies the time rule necessary for Modbus communication in the RTU mode even when the CPU 11 having a low processing capacity with respect to the communication speed is used. In addition, according to the communication apparatus 10 which concerns on this Embodiment 1, 2, although the case where it applied to a field device was illustrated and demonstrated, it was applied to all the apparatuses which implement Modbus communication in RTU mode irrespective of a field device. Applicable.

  A method for newly developing a circuit for realizing Modbus communication is also conceivable. However, when supporting Modbus communication, it is necessary to implement both the ASCII mode and the RTU mode. Here, since the ASCII mode can be realized by the existing UART, the implementation of the ASCII mode can improve the quality and the development efficiency by using the existing UART as it is. On the other hand, since the RTU mode is the same as the ASCII mode except for the time regulation, the quality and the development efficiency can be improved by adding an external circuit to the existing UART.

  As mentioned above, although preferred embodiment of this invention was explained in full detail, it cannot be overemphasized that the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiments. Further, it is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  DESCRIPTION OF SYMBOLS 10 ... Communication apparatus, 11 ... CPU, 12 ... Memory, 13 ... UART, 14, 21, 22, 23 ... Interrupt control circuit, 15 ... Register interface circuit, 16 ... External communication interface circuit, 17 ... External circuit, 18 ... Bus 24 ... DMA controller 151 ... FTO setting register 152a ... RTO measurement enable register 152b ... FTO measurement enable register 152c ... CTO measurement enable register 153 ... CTO setting register 154 ... RTO setting register 155 ... Counter clear register 171 ... Timer counter circuit, 172 ... FTO setting excess comparison circuit, 173 ... CTO setting excess comparison circuit, 174 ... RTO setting excess comparison circuit, 175 ... Error frame detection circuit, 176 ... Reception mask circuit, 177 ... Transmission mask circuit, 17 ... DMAC start-up control circuit

Claims (5)

The time interval between predetermined unit data in the communication frame is a first time, the time interval between the last unit data of the communication frame and the first unit data of the following communication frame is a second time, and the communication frame is When the time from reception until transmission of the response frame is a third time, the unit data is received in the communication frame within the first time, and the communication frame is followed by the communication frame. Receiving the unit data during a period exceeding the second time, and transmitting the response frame within the third time,
A timer counter circuit that starts counting each time it detects unit data in the received communication frame;
A comparison circuit for monitoring each of the first time, the second time, and the third time set in advance from the count value of the timer counter circuit;
When the time interval at which the unit data in the frame is received exceeds the first time and is received within the second time by the output of the comparison circuit, the unit data in the target communication frame is A control circuit that transmits the response frame within the third time each time it receives a communication frame that is discarded and not discarded;
A communication apparatus comprising: An interrupt control circuit;
The control circuit includes:
After the first time is exceeded by the first time excess detection signal, the second time excess detection signal, and the reception completion detection signal of the unit data in the communication frame, which are output from the comparison circuit. When an error frame is detected before the second time is exceeded, the interrupt control circuit is activated, and the communication frame received thereafter until the second time is exceeded based on an interrupt processing request from the interrupt control circuit. The communication apparatus according to claim 1, wherein unit data in the network is discarded or not received. The control circuit includes:
3. The communication apparatus according to claim 1, wherein transmission of unit data to the outside in the communication frame is limited based on a third time excess detection signal output from the comparison circuit. A memory and a DMA controller;
The control circuit includes:
When the comparison circuit outputs the first time excess detection signal, a response frame is created and stored in the memory, and the comparison circuit outputs the second time detection signal. 4. The communication device according to claim 1, wherein if the error frame is not detected, a transmission request for the response frame is output to the DMA controller. 5. It has a register interface circuit,
The control circuit includes:
5. The validity / invalidity of each time monitoring by the comparison circuit is controlled by writing a fixed value in a predetermined register assigned to the register interface circuit. Communication equipment.

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