JP2010170591A - Nonvolatile semiconductor storage device and method for driving the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device in which the repetitive operation reliability of a charge storage type memory cell is improved, and a method for driving the same. <P>SOLUTION: The nonvolatile semiconductor storage device is provided with a memory cell and a drive unit. The memory cell comprises: a semiconductor layer comprising a channel and source/drain regions provided on both sides of the channel; a laminated structure having a first insulation film provided on the channel and the a charge storage layer provided on the first insulation film; and a gate electrode provided on the laminated structure. The drive unit applies, between the semiconductor layer and the gate electrode, a first pulse for writing or deleting data while lowering the potential of the gate electrode than that of the semiconductor layer, and applies, between the semiconductor layer and the gate electrode, a second pulse for injecting electrons into the laminated structure while raising the potential of the gate electrode than that of the semiconductor, on the basis of the number of times of applying the first pulse. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device and a driving method thereof.

  In the conventional flash memory, a floating gate made of conductive polysilicon is used as a charge retention layer for storing information. However, as a higher performance next-generation flash memory, a memory having an insulating charge retention layer is used. It is being considered.

  For example, a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure memory using insulating silicon nitride as a charge retention layer has been conventionally used by using a charge storage layer such as silicon nitride instead of a floating gate. It is considered that interference between adjacent cells, which is a problem in the floating gate type memory, and damage of retained data due to a defect of the tunnel insulating film are reduced.

  However, when a nonvolatile semiconductor memory device having an insulating charge storage layer such as a MONOS type memory is put to practical use, there is a problem that reliability of repeated operation is low (for example, see Non-Patent Document 1). . That is, dielectric breakdown occurs in the memory cell due to stress of repetitively applied write and erase operations. In addition, a memory having a silicon-oxide-nitride-oxide-silicon structure having an insulating charge storage layer (see, for example, Non-Patent Document 2) and a memory using nanocrystals as a charge storage layer (see, for example, Non-Patent Document 3) ), The same dielectric breakdown occurs, and the reliability of repeated operation is a problem.

  Note that in a floating gate type nonvolatile semiconductor memory device, writing is performed by applying voltage stress to the gate insulating film in a state where channel current does not flow and extracting electrons trapped in the gate insulating film to the floating gate side. A technique for restoring characteristics is disclosed (for example, Patent Document 1).

JP-A-7-1222091

“Nitride Engineering and The Effect of Interface on Charge Trap Flash Performance and Reliability”, IEEE CFP08RPS-CDR 46th Annual International Reliability Physics Symposium Proceedings, Phoenix, pp.406-410, 2008. “Polarity-Dependent Device Degradation in SONOS Transistors Due to Gate Conduction under Nonvolatile Memory Operations”, IEEE Transactions on Device and Materials Reliability, vol.6 No.2, pp.334-342 June 2006. “Performance and Reliability Features of Advanced Nonvolatile Memories Based on Discrete Traps (Silicon Nanocrystals, SONOS)”, IEEE Transactions on Device and Materials Reliability, vol.4 No.3, pp.377-389, September 2004.

  The present invention provides a nonvolatile semiconductor memory device and a driving method thereof in which the repetitive operation reliability of a charge storage type memory cell is improved.

  According to one embodiment of the present invention, a semiconductor layer having a channel and a source region and a drain region provided on both sides of the channel, a first insulating film provided on the channel, and the first insulating film A memory cell having a stacked structure including a charge storage layer provided on the gate electrode, a gate electrode provided on the stacked structure, and a potential of the gate electrode lower than that of the semiconductor layer. Then, a first pulse for performing one of data writing and erasing is applied between the semiconductor layer and the gate electrode, and based on the number of times of application of the first pulse, the gate more than the semiconductor layer. A non-volatile semiconductor memory device comprising: a drive unit that applies a second pulse for injecting electrons into the stacked structure by increasing an electrode potential between the semiconductor layer and the gate electrode Proposed It is.

  According to another aspect of the present invention, a semiconductor layer having a channel and a source region and a drain region provided on both sides of the channel, a first insulating film provided on the channel, and the first A memory cell having a stacked structure including a charge storage layer provided on the insulating film; a gate electrode provided on the stacked structure; and a potential of the gate electrode relative to the semiconductor layer. And applying a first pulse for writing or erasing data between the semiconductor layer and the gate electrode and reducing the gate electrode from the semiconductor layer based on a predetermined time. A non-volatile semiconductor memory device comprising: a driving unit that applies a second pulse for injecting electrons into the stacked structure by increasing the potential of the semiconductor layer between the semiconductor layer and the gate electrode. Provided That.

According to another aspect of the present invention, a semiconductor layer having a channel and a source region and a drain region provided on both sides of the channel, a first insulating film provided on the channel, and the first A memory cell having a stacked structure having a charge storage layer provided on an insulating film, a gate electrode provided on the stacked structure charge storage layer, and an input to which a start signal is input And applying a first pulse between the semiconductor layer and the gate electrode for lowering the potential of the gate electrode lower than that of the semiconductor layer and writing or erasing data. Based on the input start signal, a second pulse for injecting electrons into the stacked structure by applying a potential of the gate electrode higher than that of the semiconductor layer is applied between the semiconductor layer and the gate electrode. With drive The nonvolatile semiconductor memory device characterized by comprising a are provided.
According to another aspect of the present invention, a semiconductor layer having a channel and a source region and a drain region provided on both sides of the channel, a first insulating film and the first insulation provided on the channel A driving method of a nonvolatile semiconductor memory device having a memory cell having a stacked structure having a charge storage layer provided on a film and a gate electrode provided on the charge storage layer, A first pulse for writing or erasing data with a potential of the gate electrode lower than that of the semiconductor layer is applied between the semiconductor layer and the gate electrode, and the number of times the first pulse is applied And applying a second pulse for injecting electrons into the stacked structure with a potential of the gate electrode higher than that of the semiconductor layer, between the semiconductor layer and the gate electrode. Method for driving the nonvolatile semiconductor memory device is provided.

  According to the present invention, there is provided a nonvolatile semiconductor memory device and a driving method thereof in which repetitive operation reliability of charge storage type memory cells is improved.

1 is a schematic view illustrating the configuration of a nonvolatile semiconductor memory device according to a first embodiment of the invention. FIG. 4 is a flowchart illustrating the operation of the nonvolatile semiconductor memory device according to the first embodiment of the invention. FIG. 4 is a schematic view illustrating the operation of the nonvolatile semiconductor memory device according to the first embodiment of the invention. FIG. 4 is a graph illustrating characteristics of the nonvolatile semiconductor memory device according to the first embodiment of the invention. FIG. 10 is a flowchart illustrating the operation of a nonvolatile semiconductor memory device of a comparative example. 6 is a schematic view illustrating the operation of a nonvolatile semiconductor memory device of a comparative example. FIG. It is a graph which illustrates the characteristic of the non-volatile semiconductor memory device of a comparative example. FIG. 6 is a graph illustrating characteristics of another nonvolatile semiconductor memory device according to the first embodiment of the invention. FIG. 6 is a schematic view illustrating the operation of a nonvolatile semiconductor memory device according to a second embodiment of the invention. FIG. 6 is a graph illustrating characteristics of the nonvolatile semiconductor memory device according to the second embodiment of the invention. FIG. 10 is a schematic view illustrating the operation of another nonvolatile semiconductor memory device according to the second embodiment of the invention. FIG. 10 is a flowchart illustrating the operation of the nonvolatile semiconductor memory device according to the third embodiment of the invention. FIG. 10 is a schematic view illustrating the operation of a nonvolatile semiconductor memory device according to a third embodiment of the invention. FIG. 10 is a flowchart illustrating the operation of the nonvolatile semiconductor memory device according to the fourth embodiment of the invention. FIG. 10 is a schematic view illustrating the operation of a nonvolatile semiconductor memory device according to a fourth embodiment of the invention. FIG. 9 is a schematic view illustrating the configuration of a nonvolatile semiconductor memory device according to a fifth embodiment of the invention. FIG. 10 is a schematic view illustrating the configuration of a nonvolatile semiconductor memory device according to a sixth embodiment of the invention. FIG. 16 is a flowchart illustrating the operation of the nonvolatile semiconductor memory device according to the seventh embodiment of the invention. FIG. 10 is a schematic view illustrating the configuration of a nonvolatile semiconductor memory device according to an eighth embodiment of the invention. FIG. 25 is a flowchart illustrating a method for driving a nonvolatile semiconductor memory device according to a ninth embodiment of the invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio coefficient of the size between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratio coefficient may be represented differently depending on the drawing.
Further, in the present specification and each drawing, the same reference numerals are given to the same elements as those described above with reference to the previous drawings, and detailed description thereof will be omitted as appropriate.

(First embodiment)
FIG. 1 is a schematic view illustrating the configuration of the nonvolatile semiconductor memory device according to the first embodiment of the invention.
That is, this figure illustrates the configuration of the memory cell of the nonvolatile semiconductor memory device 101 according to the first embodiment of the present invention as a schematic cross-sectional view, and represents one transistor type memory cell.

  As shown in FIG. 1, the nonvolatile semiconductor memory device 101 according to this embodiment includes a semiconductor layer 1 having a channel 1a and a source region 2a and a drain region 2b provided on both sides of the channel 1a. On the semiconductor layer 1, a laminated structure (laminated insulating film) 3 including a charge storage layer 3B is provided. A gate electrode 4 is provided on the laminated structure 3. The laminated structure 3 includes a charge storage layer 3B, a first insulating film 3A provided between the charge storage layer 3B and the semiconductor layer 1, and a first insulating film provided between the charge storage layer 3B and the gate electrode 4. 2 insulating film 3C.

  The drive unit 20 is connected to the memory cell 8 having such a structure. The driving unit 20 is connected to the semiconductor layer 1 and the gate electrode 4, an output unit 21 that supplies a voltage applied between the semiconductor layer 1 and the gate electrode 4, and a control unit 22 connected to the output unit 21. Have.

For example, a 4 nm thick SiO ₂ film is used for the first insulating film 3A. For example, a 5 nm thick Si ₃ N ₄ film is used as the charge storage layer 3B. For the second insulating film 3C, for example, an Al ₂ O ₃ film having a thickness of 17 nm is used. The first insulating film 3A is, for example, a tunnel insulating film, and the second insulating film 3C is, for example, a block insulating film. The gate electrode 4 can be made of n ⁺ polysilicon. That is, the memory cell 8 of this specific example is a MONOS type memory cell.

  Note that the nonvolatile semiconductor memory device 101 may be an interface trap type nonvolatile semiconductor memory device that captures charges at the interface between the first insulating film 3A and the second insulating film 3C. In this case, the interface between the insulating film and the insulating film is regarded as the charge storage layer 3B.

  Further, charges are trapped in the charge storage layer 3B, at the interface between the first insulating film 3A and the charge storage layer 3B, and at the interface between the charge storage layer 3B and the second insulating film 3C. A nonvolatile semiconductor memory device having a nanodot layer with a structure in which nanodots (nanocrystals) are embedded can also be provided. Further, the charge storage layer 3B may be a nanodot layer. The nanodots are silicon, germanium, or organic or metal particles, and have a size of 0.5 nm to 3 nm. Nanodots are preferably as small as possible in order to fit a sufficient number in one memory cell, and the size is preferably 0.5 nm to 2 nm.

  The charge storage layer 3B has a function of capturing the injected charge. The charge storage layer 3B has, for example, discrete traps. The discrete traps are spatially distributed, in the charge storage layer 3B, in the vicinity of the interface of the charge storage layer 3B on the semiconductor layer 1 side (that is, on the first insulating film 3A side), or in the charge storage layer. It is distributed near the interface on the 3B second insulating film 3C side. For example, a silicon nitride film can be used for the charge storage layer 3B, and a metal oxide film having a high density of discrete traps can also be used. It is also possible to form the charge storage layer 3B by laminating a plurality of materials having discrete traps. Furthermore, an insulating layer that does not have a discrete trap in the charge storage layer 3B can be applied to the charge storage layer 3B.

  As illustrated in FIG. 1, the non-volatile semiconductor memory device 101 is a MONOS type non-volatile semiconductor memory device having memory cells 8 constituted by the stacked structure 3. A SONOS type (Semiconductor-Oxide-Nitride-Oxide-Semiconductor) type may be used.

  However, as will be described later, the second insulating film 3C can be omitted, that is, a non-volatile semiconductor memory device having a MNOS (Metal-Nitride-Oxide-Semiconductor) type structure can be provided. Hereinafter, the MONOS structure illustrated in FIG. 1 will be described as an example.

In the above description, the SiO ₂ film is used as the first insulating film 3A, the Si ₃ N ₄ film is used as the charge storage layer 3B, and the Al ₂ O ₃ film is used as the second insulating film 3C. The material used is arbitrary.

The charge storage layer 3B includes, for example, silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), aluminum oxynitride (AlON), hafnia (HfO ₂ ), hafnium aluminum Nate (HfAlO ₃ ), Hafnia nitride (HfON), Hafnium nitride aluminate (HfAlON), Hafnium silicate (HfSiO), Hafnium nitride silicate (HfSiON), Lanthanum oxide (La ₂ O ₃ ) and Lanthanum aluminate ( LaAlO ₃ ) or the like can be used. The charge storage layer 3B may have a structure in which layers of at least one material selected from these materials are stacked.

The first insulating film 3A includes, for example, silicon oxide (SiO ₂ ) silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), aluminum oxynitride (AlON), Hafnia (HfO ₂ ), hafnium aluminate (HfAlO ₃ ), nitrided hafnia (HfON), nitrided hafnium aluminate (HfAlON), hafnium silicate (HfSiO), nitrided hafnium silicate (HfSiON), lanthanum oxide (La ₂₎ O ₃ ) and lanthanum aluminate (LaAlO ₃ ) can be used. The charge storage layer 3B may have a structure in which layers of at least one material selected from these materials are stacked.

The second insulating film 3C includes, for example, silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), aluminum oxynitride (AlON), hafnia (HfO ₂ ), hafnium-aluminate (HfAlO ₃ ), Nitrided hafnia (HfON), nitrided hafnium aluminate (HfAlON), hafnium silicate (HfSiO), hafnium nitride silicate (HfSiON), lanthanum oxide (La ₂ O ₃ ) and lanthanum aluminate (LaAlO ₃ ), lanthanum aluminum Silicate (LaAlSiO) or the like can be used. Similarly to the case of the charge storage layer 3B, the second insulating film 3C may have a structure in which layers of at least one material selected from these materials are stacked.

  For the semiconductor layer 1, various semiconductor substrates such as silicon, SiGe, SiGeC, and Ge can be used. Furthermore, an SOI (Silicon on Insulator) layer, a GOI (Germanium on Insulator) layer, an SGOI layer, or the like can be used for the semiconductor layer 1.

  The memory cell 8 may have a vertical structure in which, for example, the main surface of the semiconductor layer 1 intersects the main surface of the substrate.

  In the nonvolatile semiconductor memory device 101 according to this embodiment, the conductivity type is arbitrary. Hereinafter, the case where the nonvolatile semiconductor memory device 101 has the N-channel type memory cell 8 will be described.

That is, a gate electrode 4 is formed on the stacked structure 3, and an N-type source is formed in the semiconductor layer 1 by ion-implanting an N-type impurity into the P-type semiconductor layer 1 using the gate electrode 4 as a mask. Region 2a and drain region 2b are formed. Then, a channel 1a is formed in the semiconductor layer 1 between the source region 2a and the drain region 2b.
Note that the nonvolatile semiconductor memory device 101 according to the present embodiment is not limited to the N-channel type but can be applied to the P-channel type. At that time, the impurities in the source region 2a and drain region 2b and the semiconductor layer 1 have opposite polarities.

  Hereinafter, the operation of the nonvolatile semiconductor memory device 101 according to the present embodiment and the driving method of the nonvolatile semiconductor memory device according to the embodiment of the present invention will be described. The following operations and driving methods are realized by the driving unit 20.

  In the following, data writing to the memory cell 8 is performed when the potential of the gate electrode 4 is higher than the potential of the semiconductor layer 1, and erasing of the data written to the memory cell 8 is performed on the semiconductor layer 1. The description will be made assuming that the process is performed when the potential of the gate electrode 4 is lower than the potential. That is, for example, a case where data writing is injection and capture of electrons into the charge storage layer 3B and data erasing is injection and capture of holes into the charge storage layer 3B will be described. Hereinafter, the potential of the gate electrode 4 when the semiconductor layer 1 is used as a reference is referred to as a gate voltage Vg.

FIG. 2 is a flowchart illustrating the operation of the nonvolatile semiconductor memory device according to the first embodiment of the invention.
FIG. 3 is a schematic view illustrating the operation of the nonvolatile semiconductor memory device according to the first embodiment of the invention.
As shown in FIG. 2, in the nonvolatile semiconductor memory device 101, first, data is written to the memory cell 8 (step S110). That is, a write operation is performed.
That is, as shown in FIG. 3, the write pulse Pw (third pulse P <b> 3) having a higher potential than the potential of the semiconductor layer 1 is applied to the gate electrode 4 in the memory cell 8 of the nonvolatile semiconductor memory device 101. That is, a positive write pulse Pw is applied to the gate electrode 4. The voltage of the write pulse Pw (write pulse voltage Vw) is, for example, 10 V to 30 V, and the application time of the write pulse Pw (write pulse time width Tw) is 10 μs to 100 μs. However, in the present invention, the voltage in the write pulse Pw and the application time are arbitrary. Thereby, desired data is stored in the nonvolatile semiconductor memory device 101.

Thereafter, the data stored in the memory cell 8 is held for an arbitrary holding period Th (step S120).
At this time, as shown in FIG. 3, the gate voltage Vg in the holding period Th is lower than the write pulse voltage Vw, and is 0 V in this specific example. However, the gate voltage Vg in the holding period Th may be a voltage that does not substantially affect the written data, and is set to a predetermined value depending on the design of the memory cell 8. For example, the absolute value of the gate voltage Vg in the holding period Th is set lower than the absolute value of the write pulse voltage Vw and the absolute value of an erase pulse voltage Ve described later.

  The length of the holding period Th is determined by the usage state of the nonvolatile semiconductor memory device 101 and is arbitrary. In some cases, the data holding step S120 may be omitted, and the process may directly move from step S110 to the following step S130.

Then, when the held data is rewritten or erased, for example, a predetermined trigger is obtained and the process proceeds to the next step to erase the data in the memory cell 8 (step S130). That is, an erase operation is performed. This is an operation of erasing data once written in the memory cell 8, and is an operation executed before writing new data in the memory cell 8, for example.
At this time, as shown in FIG. 3, an erase pulse Pe (first pulse P <b> 1) having a potential lower than that of the semiconductor layer 1 is applied to the gate electrode 4. That is, the negative erase pulse Pe is applied to the gate electrode 4. The voltage of the erase pulse Pe (erase pulse voltage Ve) is, for example, −10 V to −30 V, and the application time (erase pulse time width Te) is 1 ms to 10 ms. However, in the present invention, the voltage and application time in the erase pulse Pe are arbitrary. As a result, the data stored in the nonvolatile semiconductor memory device 101 is erased, and preparations for writing new data, for example, are made.

  Then, step S110 of the write operation and step S130 of the erase operation are repeated. At this time, the data holding step S120 is also repeated.

  In the operation and driving method of the nonvolatile semiconductor memory device 101 according to the present embodiment, when the number of times that the above-described erase operation step S130 is repeated reaches a certain number, the gate is formed with respect to the semiconductor layer 1. A recovery pulse Pr that makes the potential of the electrode 4 positive is applied between the semiconductor layer 1 and the gate electrode 4 (step S150).

  For example, in this specific example, as shown in FIG. 2, the number n is set to 0 in the initial state (step S105). The number n is the number of times the above write operation (step S110) and erase operation (step S130) are executed, and the number n is an integer of 0 or more. In the first operation, first, n is set to 1 of n + 1 (step S106). Then, said step S110, step S120, and step S130 are performed.

  And it is judged whether the frequency | count n is more than the predetermined setting frequency | count N (predetermined value) (step S140). The set number N is arbitrary, and may be changed according to the cumulative number of executions of the write operation and the erase operation, as will be described later. Here, the set number N is, for example, 10 times. At this time, if the number n is smaller than the set number N, the process returns to step S106, and the above steps S110, S120, and S130 are repeated. That is, for example, step S110, step S120, and step S130 described above are repeated nine times.

  In step S140, when the number n reaches the set number N, that is, when the number n becomes equal to or greater than the set number N, the process proceeds to step S150. That is, for example, when step S110, step S120, and step S130 are repeated 10 times, the next step S150 is performed.

As shown in FIG. 3, in step S <b> 150, the recovery pulse Pr (second pulse P <b> 2) is applied to the gate electrode 4, for example. The recovery pulse Pr is a voltage at which the potential of the gate electrode 4 becomes positive with respect to the semiconductor layer 1. Then, electrons are injected into the laminated structure 3 by applying the recovery pulse Pr.
The voltage of the recovery pulse Pr (recovery pulse voltage Vr) is, for example, 10 to 30 V, and the application time of the recovery pulse Pr (recovery pulse time width Tr) is, for example, longer than 100 μs and not longer than 10 s. However, the present invention is not limited to this, and the recovery pulse voltage Vr and the recovery pulse time width Tr in the recovery pulse Pr are arbitrary. Here, the operation of applying the recovery pulse Pr is referred to as “recovery operation”.

After the application of the recovery pulse Pr, an initialization pulse Pi (fourth pulse P4) that makes the potential of the gate electrode 4 negative with respect to the semiconductor layer 1 is applied between the semiconductor layer 1 and the gate electrode 4. Then, the memory cell is initialized (step S160).
That is, as shown in FIG. 3, the initialization pulse Pi is applied to the gate electrode 4. The voltage of the initialization pulse Pi is a voltage at which the potential of the gate electrode 4 is negative with respect to the semiconductor layer 1. Thereby, for example, holes are injected into the charge storage layer 3B, and the data storage state of the memory cell 8 is initialized. The voltage of the initialization pulse Pi is defined as an initialization pulse voltage Vi, and the application time is defined as an initialization pulse time width Ti. The initialization pulse voltage Vi and the initialization pulse time width Ti are arbitrary. The operation of applying the initialization pulse Pi is referred to as “initialization operation”.

  And it returns to step S105 again, makes the frequency | count n 0, and repeats said operation | movement.

As described above, the driving unit 20 lowers the potential of the gate electrode 4 lower than that of the semiconductor layer 1 and performs the first pulse P <b> 1 for writing or erasing data between the semiconductor layer 1 and the gate electrode 4. Apply. Then, based on the number n of times of application of the first pulse P1, the potential of the gate electrode 4 is made higher than that of the semiconductor layer 1, and the second pulse P2 (recovery pulse Pr) for injecting electrons into the stacked structure 3 is used as the semiconductor. Applied between layer 1 and gate electrode 4. Here, the first pulse P1 is the erase pulse Pe, and the recovery pulse Pr is applied based on the number of erase operations.
By applying the recovery pulse Pr, it is possible to improve the reliability of repeated operation of the charge storage type memory cell.

  As described above, in this specific example, the erase pulse Pe is the first pulse P1, and the recovery pulse Pr is the second pulse P2. At this time, the write pulse Pw is set to the third pulse P3. That is, the drive unit 20 makes the potential of the gate electrode 4 higher than that of the semiconductor layer 1 and performs the other operation (write operation in this example) of the data write and erase (write pulse Pw). ) Is applied between the semiconductor layer 1 and the gate electrode 4.

FIG. 4 is a graph illustrating characteristics of the nonvolatile semiconductor memory device according to the first embodiment of the invention.
That is, this figure illustrates the measurement result of the flat band voltage when the above-described write operation and erase operation are repeatedly executed in the nonvolatile semiconductor memory device 101. In the figure, the horizontal axis represents the number of repetitions n of the write operation and the erase operation, and the vertical axis represents the flat band voltage Vfbw after the write operation and the flat band voltage Vfbe after the erase operation. In this measurement experiment, the maximum number of times n was 10,000, that is, the write operation and the erase operation were repeated 10,000 times.

  In this specific example, the write pulse voltage Vw is 22 V, and the write pulse time width Tw is 100 μs. On the other hand, the erase pulse voltage Ve is −23V, and the erase pulse time width Te is 10 ms. The recovery pulse voltage Vr was 22 V and the recovery pulse time width Tr was 100 ms. The set number N is set to 10. That is, the above-mentioned recovery pulse Pr was applied with the number of repetitions n of the write operation and the erase operation once every 10 times. Then, the initialization pulse Pi was applied after the application of each recovery pulse Pr. At that time, the initialization pulse voltage Vi was −23 V, and the initialization pulse time width Ti was 10 ms.

  As shown in the figure, in the nonvolatile semiconductor memory device 101 according to the present embodiment, it is possible to measure the flat band voltages Vfbw and Vfbe up to 10,000 times of the repeated operation n in which the measurement is performed. It did not change much from the initial state. That is, in the nonvolatile semiconductor memory device 101, no element breakdown occurred until the number n of repeated operations was at least 10,000.

(Comparative example)
FIG. 5 is a flowchart illustrating the operation of the nonvolatile semiconductor memory device of the comparative example. FIG. 6 is a schematic view illustrating the operation of the nonvolatile semiconductor memory device of the comparative example.
As shown in FIGS. 5 and 6, the recovery pulse Pr is not applied in the nonvolatile semiconductor memory device 109 (not shown) of the comparative example.

  That is, first, data is written into the memory cell 8 (step S110), and then the data stored in the memory cell 8 is held for an arbitrary holding period Th (step S120). Data erasure is performed (step S130). That is, only the application of the write pulse Pw, the retention of data for an arbitrary retention period Th, and the application of the erase pulse Pe are repeated. Then, the number of repetitions n is not counted.

FIG. 7 is a graph illustrating characteristics of the nonvolatile semiconductor memory device of the comparative example.
That is, this figure illustrates the measurement result of the flat band voltage when the above write operation and erase operation are repeatedly executed in the nonvolatile semiconductor memory device 109 of the comparative example. In this measurement experiment, the above operation was repeated until the element was destroyed.

  As shown in FIG. 7, in the case of the nonvolatile semiconductor memory device 109 of the comparative example, the memory cell 8 causes dielectric breakdown (indicated by a broken line BD) when the number of repeated operations n is 1500 times, and more In the case of n, the flat band voltage Vfbw after the write operation and the flat band voltage Vfbe after the erase operation could not be measured.

  As described above, in the comparative example in which the recovery pulse Pr is not used, element breakdown occurs in 1500 operations, whereas in the nonvolatile semiconductor memory device 101 of the present embodiment using the recovery pulse Pr, 10,000. The device was not destroyed even in the operation more than once. As described above, by performing the step S150 of applying the recovery pulse Pr, the dielectric breakdown lifetime of the MONOS type memory cell is significantly improved.

The principle of improving the dielectric breakdown lifetime by applying the recovery pulse Pr will be described below.
According to the inventors' previous experiments, it has been found that the dielectric breakdown phenomenon of the MONOS type memory cell is rate-determined by the erasing operation for setting the semiconductor layer 1 to a positive voltage relative to the gate electrode 4. This is because the stacked insulating film 3 (first insulating film) is generated by holes injected from the semiconductor layer 1 to the charge storage layer 3B or back tunnel electrons injected from the gate electrode 4 side to the charge storage layer 3B by the erase operation. This indicates that at least one of the film 3A, the charge storage layer 3B, and the second insulating film 3C is deteriorated, and finally dielectric breakdown occurs.

  Furthermore, according to the experiment by the inventors, in the memory cell 8 deteriorated by hole injection or back tunnel electron injection, a voltage with the gate electrode 4 having a positive polarity is applied to the semiconductor layer 1 to form a laminated insulation. It was found that the deterioration of the film 3 recovered to some extent. That is, the deterioration of the stacked insulating film 3 can be recovered by injecting electrons from the semiconductor layer 1 into the stacked insulating film 3 (at least one of the first insulating film 3A, the charge storage layer 3B, and the second insulating film 3C). it can.

  That is, in the case of a memory cell having a laminated insulating film structure such as a MONOS structure, the deterioration or dielectric breakdown phenomenon depends on the polarity of the voltage applied to the memory cell. For example, when a voltage having such a polarity as to inject holes from the semiconductor layer 1 is applied as in the erasing operation, the deterioration of the memory cell 8 is promoted, and finally dielectric breakdown occurs. On the other hand, even if a voltage having a polarity for injecting electrons is applied as in the write operation, the deterioration leading to dielectric breakdown does not occur, but rather the portion deteriorated by hole injection is recovered to some extent.

  In general, in the case of a memory cell having a laminated insulating film structure such as a MONOS structure, the erase operation is slower than the write operation, and therefore the erase pulse time width Te tends to be longer than the write pulse time width Tw. Also in this specific example, the erase pulse time width Te is 10 ms, which is two orders of magnitude larger than the write pulse time width Tw of 100 μs.

  Therefore, when the recovery pulse Pr is not applied as in the comparative example, the memory cell 8 deteriorated by the erasing operation, that is, the hole injection, cannot be recovered due to the short application time of the voltage by the electron injection by the writing operation, and the insulation It will lead to destruction. That is, the deteriorated portion cannot be sufficiently recovered only by the electron injection by the writing operation. In order to sufficiently recover the deterioration only by the write operation, it is conceivable to lengthen the application time of the write pulse Pw. However, in this case, the write operation speed is significantly reduced. Although it is conceivable to increase the voltage of the write pulse Pw, since it is necessary to control the write level for each memory cell in the write operation, the write pulse Pw is applied for a long time with a high voltage. It is not possible.

  On the other hand, unlike the nonvolatile semiconductor memory device 101 of this embodiment, separately from the write operation, the recovery pulse Pr is applied at an appropriate frequency and a large amount of electrons are injected, so that only the electron injection for the write operation is performed. Then, it is possible to recover the deterioration of the laminated insulating film 3 by making up for the portion that could not be recovered. That is, by applying the recovery pulse Pr, the memory cell 8 that has deteriorated due to the erase operation can be sufficiently recovered. As a result, the dielectric breakdown life is improved. Note that the recovery pulse Pr can be applied simultaneously to a plurality of memory cells, and the time required for the application is short as a whole, so there is no practical problem.

  The technique disclosed in Patent Document 1 aims at recovering a writing failure due to electrons trapped in the tunnel gate insulating film, so that a channel current does not flow when voltage stress is applied to extract the trapped electrons. To be. If the channel current flows, electrons cannot be extracted, and there is a concern that the electron capture into the tunnel gate insulating film is promoted. For this reason, the source line is controlled to be in an open state.

  On the other hand, the nonvolatile semiconductor memory device 101 of the present embodiment is intended to improve the dielectric breakdown resistance of the laminated insulating film 3, and in order to inject electrons into the laminated structure 3 by the recovery pulse Pr, A current flows. For this reason, for example, the source line is not in a released state, but is set to a predetermined potential.

  Note that in the floating gate type nonvolatile semiconductor memory device that is the subject of Patent Document 1, the tunnel gate insulating film is relatively thick, which causes a write failure due to the trapping of electrons in the tunnel insulating film. appear. In contrast, in the charge storage layer type nonvolatile semiconductor memory device targeted by the present embodiment, the first insulating film 3A corresponding to the tunnel gate insulating film is relatively thin. For this reason, in this embodiment, it is practically not a problem that electrons are captured in the first insulating film 3A by the application of the recovery pulse Pr. For example, when the write characteristics (Vfbw) of FIG. 4 (this embodiment) and FIG. 7 (comparative example) are compared, the write characteristics of both are substantially the same, and the deterioration of the first insulating film 3A due to the recovery pulse Pr. It is clear that is not encouraged.

  In the nonvolatile semiconductor memory device 101, the recovery pulse voltage Vr of the recovery pulse Pr may be equal to or higher than the voltage at which electrons are injected from the semiconductor layer 1 into the stacked insulating film 3, but according to the experiments of the inventors, for example, 10V or higher A voltage of 30V or less is desirable. That is, when the voltage is lower than 10V, the deterioration recovery effect is low, and when the voltage is higher than 30V, another dielectric breakdown may occur. The recovery pulse voltage Vr is more preferably 15 V or more and 30 V or less. By using a voltage of 15 V or more, the recovery effect of deterioration is more effectively exhibited.

  The recovery pulse time width Tr is preferably equal to or larger than the write pulse time width Tw. When the recovery pulse time width Tr is shorter than the write pulse time width Tw, the recovery effect of deterioration is low, and by making the recovery pulse time width Tr equal to or greater than the write pulse time width Tw, the recovery effect of deterioration is more effective. Is demonstrated.

  The recovery pulse time width Tr is preferably longer than 100 μs and not longer than 10 seconds, for example. If it is 100 μs or less, the effect of recovery from deterioration is low, and if it is longer than 10 s, the recovery operation takes a long time and the practicality is lowered. The recovery pulse time width Tr is more preferably 1 ms or longer and 10 seconds or shorter. That is, by setting the time to 1 ms or more, the recovery effect of deterioration is more effectively exhibited.

  The set number N is preferably 1 or more and 100 or less. According to the inventor's experiment, when the recovery pulse Pr is applied to the memory cell 8 in which the number of repetitions n of the operation is 100 times or less, the effect of suppressing the element breakdown is high. descend.

  In some cases, the recovery pulse Pr may be applied for each write operation and erase operation. However, in this case, since the operation speed as the nonvolatile semiconductor memory device is lowered depending on the time for applying the recovery pulse Pr, an appropriate numerical value as the set number of times N from the viewpoint of the element destruction suppression effect and the operation speed. Is set. Further, as will be described later, the set number N may be changed based on the cumulative number of repeated operations.

  When the set number N is 1, the recovery pulse Pr is applied in each write operation and erase operation (specifically, application of the first pulse P1). Thus, even when the recovery pulse Pr is applied in each writing operation and erasing operation, the recovery pulse Pr can be considered to be applied based on the number of times of application of the first pulse P1.

  In the above description, the operation of applying the recovery pulse Pr every predetermined number of times N has been described. However, the present invention is not limited to this. For example, as will be described later, the voltage (recovery pulse voltage Vr) of the recovery pulse Pr (second pulse P2) and the application time (based on the number of times of application (cumulative number) of the erase pulse Pe (first pulse P1) ( At least one of the recovery pulse time width Tr) and the number of pulses included in the recovery pulse Pr may be changed. Thus, even when the recovery pulse Pr whose voltage, application time, and number of included pulses change based on the number of times of application of the first pulse P1, is applied each time the first pulse P1 is applied. Alternatively, it may be applied every set number of times N.

  By the way, in the operation illustrated in FIG. 2, when the number n of repetitive operations (number of times of application of the first pulse P1) reaches a preset number N (for example, 10 times) which is a predetermined value, the recovery pulse Pr Although it has been described that the (second pulse P2) is applied, the recovery pulse is generated when the cumulative number m of operations reaches a plurality of predetermined number of times (for example, 10, 20, 30 to 100,000, etc.). Pr may be applied. Also in this case, it is considered that “when the number of times of application of the first pulse P1 reaches a set number of times that is a predetermined value, the second pulse P2 is applied”. Thus, when the cumulative number is used as the “number of times of application of the first pulse P 1”, the cumulative number is also used as the “set number”. In this case, it is desirable that a plurality of intervals included in the cumulative set number of times be 1 or more and 100 or less.

  In the above description, the case where the number of repetitions of the writing operation and the erasing operation is used as the number of repetitions n has been described. However, the number of operations for applying a negative voltage may be used. That is, in the above specific example, since the deterioration of the laminated insulating film 3 proceeds in the erase operation in which a negative voltage is applied, the number of application of the erase pulse Pe can be used as the number n of the repeated operations.

  In general, the write operation and the erase operation are performed as a set. For example, a writing operation for applying a positive voltage is performed as one set before or after an erasing operation for applying a negative voltage. In this case, the number of application times of the positive polarity write pulse (third pulse P3) substantially corresponds to the number of application times n of the negative polarity erase pulse Pe (first pulse P1). Therefore, applying the second pulse P2 based on the number of times of applying the third pulse P3 is included in applying the second pulse P2 based on the number of times of applying the first pulse P1.

  Further, in the specific example described above, the write operation is an operation in which a positive voltage is applied to the gate electrode 4 and, for example, electrons are injected into the charge storage layer 3B, and the erase operation is performed in a negative voltage. 4 is an operation of injecting holes into the charge storage layer 3B, for example. In this case, the recovery pulse Pr, which is a positive voltage, is applied to the gate electrode 4. Not limited to this.

  For example, the write pulse P3 may include a plurality of sub-pulses, and any of the sub-pulses may be a negative-polarity sub-pulse. Similarly, in the erase operation, the erase pulse Pe (first pulse P1) may include a plurality of sub-pulses, and any of the sub-pulses may be positive. Also in this case, the recovery pulse Pr, which is a positive polarity voltage, is applied based on the number of times of application of the first pulse P1.

  For example, the writing operation is an operation in which a negative voltage is applied to the gate electrode 4 to inject holes into the charge storage layer 3B, for example, and the erasing operation is performed by applying a positive voltage to the gate electrode 4. For example, the present invention can also be applied to an operation of injecting electrons into the charge storage layer 3B. In this case, a recovery pulse Pr having a positive polarity voltage is applied to the gate electrode 4.

That is, in the memory cell 8, the stacked insulating film 3 deteriorates when holes are injected from the semiconductor layer 1 into the charge storage layer 3B or when back tunnel electrons are transferred from the gate electrode 4 side to the charge storage layer 3B. In this case, the write operation is performed. Even in this case, this deterioration can be recovered by applying the recovery pulse Pr, which is a voltage having the gate electrode 4 having a positive polarity with respect to the semiconductor layer 1, to the memory cell 8.
In this case, it is possible to employ at least the number of repetitions of the write operation in which a negative voltage that causes deterioration is applied as the number of repetitions n.

  That is, as the number of repetitions n, the number of times of application of the first pulse for performing either data writing or erasing operation with the potential of the gate electrode 4 lower than that of the semiconductor layer 1 can be employed.

  The operation illustrated in FIG. 2 is performed by the drive unit 20. That is, control of each operation of the above steps S105 to S160 is performed by the control unit 22, and according to the control of the control unit 22, voltages corresponding to steps S110, S130, S150 and S160 are generated by the output unit 21, Applied to the memory cell 8.

  As shown in FIG. 1, the control unit 22 is provided with a storage unit 23 that stores, for example, the number n of repetitions of the above-described write operation and erase operation. Further, a calculation unit 24 that increases the number of times n for every number n of repeated operations is provided, and the above-described operation is performed based on the number of times n.

  Further, when a plurality of the memory cells are provided, the recovery pulse Pr can be applied to each memory cell 8 separately. However, in order to operate in a short time and increase the efficiency, the recovery pulse Pr can be collectively applied to the plurality of memory cells 8.

  That is, the nonvolatile semiconductor memory device 101 includes a plurality of memory cells 8, and the storage unit 23 stores the number of times n of application of the first pulse P <b> 1 of the plurality of memory cells 8. Then, the driving unit 20 applies the second pulse P <b> 2 to the plurality of memory cells 8 based on the number n of the plurality of memory cells 8 stored in the storage unit 23.

  At this time, for example, when the nonvolatile semiconductor memory device 101 is a flash memory, the above erasing operation can perform block collective erasure in which a plurality of memory cells 8 are erased collectively. In this case, the storage unit of the control unit 22 may be configured to store the number n of repetitive operations for each block instead of the number n of repetitive operations of each memory cell 8.

That is, the plurality of memory cells 8 are divided into a plurality of blocks, and the storage unit 23 stores the number of times n of application of the first pulse P1 for each block. And the drive part 20 applies the 2nd pulse P2 for every block based on the said frequency | count n for every block memorize | stored in the memory | storage part 23. FIG.
As a result, the element configuration of the nonvolatile semiconductor memory device is simplified, the size can be further reduced, and the operation speed can be further increased.

FIG. 8 is a graph illustrating characteristics of another nonvolatile semiconductor memory device according to the first embodiment of the invention.
That is, this figure shows the nonvolatile semiconductor memory device 101 in which the recovery pulse voltage Vr and the recovery pulse time width Tr are changed. 8A shows the result when the recovery pulse voltage Vr is 18 V and the recovery pulse time width Tr is 500 ms, and FIG. 8B shows the result when the recovery pulse voltage Vr is 24 V and the recovery pulse time width Tr. Is the result when 100 ms. Also in this case, the set number N is set to 10 times, that is, each time the write operation and the erase operation are repeated 10 times, the recovery pulse Pr is inserted and applied once. The write pulse Pw, erase pulse Pe, and initialization pulse Pi are the same as those in FIG. 4 (this embodiment) and FIG. 7 (comparative example).

  As shown in FIG. 8A, when the recovery pulse voltage Vr is 18 V and the recovery pulse time width Tr is 500 ms, element breakdown occurs when the number of repetitions n is 3000. That is, also in this case, the device lifetime was improved as compared with 1500 times of the comparative example illustrated in FIG. Thus, the recovery pulse voltage Vr may be 18V, which is lower than 22V of the write pulse voltage Vw, and the device life can be improved.

On the other hand, as shown in FIG. 8B, when the recovery pulse voltage Vr is 24 V and the recovery pulse time width Tr is 100 ms, device breakdown occurs when the number of repetitions n is 5000. That is, also in this case, the device lifetime was improved as compared with 1500 times of the comparative example illustrated in FIG. When the recovery pulse voltage Vr is made higher than that illustrated in FIG. 8A, the device life is further improved even if the recovery pulse time width Tr is shortened.
Thus, the recovery pulse voltage Vr and the recovery pulse time width Tr can be arbitrarily set.

(Second Embodiment)
FIG. 9 is a schematic view illustrating the operation of the nonvolatile semiconductor memory device according to the second embodiment of the invention.
As shown in FIG. 9, in the nonvolatile semiconductor memory device 102 according to the second embodiment of the present invention, the recovery pulse Pr has a plurality of pulses. Since other than that is the same as that of the non-volatile semiconductor memory device 101, description is abbreviate | omitted.

  That is, the recovery pulse Pr has a positive first sub-pulse Pr 1 and a second sub-pulse Pr 2 that make the gate electrode 4 higher in potential than the semiconductor layer 1. In this specific example, a pause period T01 is provided between the first sub-pulse Pr1 and the second sub-pulse Pr2. In this specific example, the gate voltage Vg is set to 0 in the rest period T01.

FIG. 10 is a graph illustrating characteristics of the nonvolatile semiconductor memory device according to the second embodiment of the invention.
In the specific example shown in the figure, the first and second subpulse voltages Vr1 and Vr2 of the first subpulse Pr1 and the second subpulse Pr2 are both 22V. The first sub-pulse time width Tr1 and the second sub-pulse time width Tr2, which are the application times of the first sub-pulse Pr1 and the second sub-pulse Pr2, are both 45 ms. The rest period T01 is 10 ms. Then, the above-described recovery pulse Pr (the first sub-pulse Pr1 and the second sub-pulse Pr2) was applied with the number n of repetitions of the write operation and the erase operation being 10 times.

  As shown in FIG. 10, in the nonvolatile semiconductor memory device 102 according to the present embodiment, element destruction did not occur until the number n of repeated operations was 5000 times. As described above, even when the recovery pulse Pr has a plurality of pulses, it is possible to provide a nonvolatile semiconductor memory device in which the repetitive operation reliability of the charge storage type memory cell is improved.

  The first and second sub-pulse voltages Vr1 and Vr2 may be the same or different. Further, the first and second sub-pulse time widths Tr1 and Tr2 may be the same or different.

  In the above description, the value of the gate voltage Vg in the pause period T01 is arbitrary. However, the absolute value of the gate voltage Vg in the pause period T01 is set small so as not to affect the writing and erasing states. Further, the first sub-pulse Pr1 and the second sub-pulse Pr2 may be continuously applied without providing the pause period T01. That is, for example, the recovery pulse Pr may be composed of an arbitrary plurality of pulses having different voltages.

FIG. 11 is a schematic view illustrating the operation of another nonvolatile semiconductor memory device according to the second embodiment of the invention.
As shown in FIG. 11, in the nonvolatile semiconductor memory device 102a according to the second embodiment of the present invention, the recovery pulse Pr has three pulses. Since other than that is the same as that of the non-volatile semiconductor memory device 101, description is abbreviate | omitted.

  That is, the recovery pulse Pr has a first sub-pulse Pr1, a second sub-pulse Pr2, and a third sub-pulse Pr3. The first to third sub-pulse voltages Vr1 to Vr3 of these pulses are different from each other. The first to third sub-pulse time widths Tr1 to Tr3, which are the application times of the first to third sub-pulses Pr3, are also different from each other. In addition, pause periods T01 and T02 are inserted between these pulses. The gate voltage Vg in the idle period is arbitrary so as not to affect the state of writing and erasing, for example.

  Thus, the recovery pulse Pr may include any number of three or more pulses (sub-pulses). The voltage and time width of each of the three or more pulses are arbitrary. Further, an arbitrary pause period may be provided between each of the three or more pulses, and the pause period may not be provided.

  As described above, the recovery pulse Pr can include an arbitrary plurality of pulses having a positive polarity that makes the gate electrode 4 have a higher potential than the semiconductor layer 1. In this case as well, the conventional recovery pulse Pr is not applied. Compared to a nonvolatile semiconductor memory device, the breakdown life can be improved.

(Third embodiment)
FIG. 12 is a flowchart illustrating the operation of the nonvolatile semiconductor memory device according to the third embodiment of the invention.
As shown in FIG. 12, in another nonvolatile semiconductor memory device 103 according to the present embodiment, at least one of the set number N and the recovery pulse Pr depending on the cumulative number m of the repeated operation of the erase operation (step S130). The recovery pulse Pr is applied by changing the above.

  That is, as the set number N, a set number N (m) that is a function of the cumulative number m is used. The set number N (m) is also a predetermined value. For example, when the cumulative number m of the repetitive operation is 1 to 30 times, the set number of times N (m) is 30 times, and when the cumulative number m is 31 to 70 times, the set number of times N (m) is 20 times. When the cumulative number m is 71 to 100, the set number N (m) is 10 times. When the cumulative number m is 101 times or more, the set number N (m) is 5 times.

  At this time, the recovery pulse Pr is not applied when the cumulative number m of repetitive operations is 1 to 29, and the recovery pulse Pr is applied when the cumulative number m is 30. The recovery pulse Pr is not applied at 31 to 49 times, and the recovery pulse Pr is applied at 50 times. The recovery pulse Pr is not applied at 51 to 69 times, and the recovery pulse Pr is applied at 70 times. In 71 to 100 times, the recovery pulse Pr is applied every 10 times of 80 times, 90 times, and 100 times. And when it is 101 times or more, the recovery pulse Pr is applied every 5 times.

  When deterioration progresses as the cumulative number m of repeated operations in the memory cell 8 increases, the deterioration in the stacked insulating film 3 is reduced by changing the application interval of the recovery pulse Pr based on the cumulative number m as described above. When the number of times of accumulation m is small, the time required for applying the recovery pulse Pr (m) can be shortened, and it becomes easy to use.

  Further, as the recovery pulse Pr, a recovery pulse Pr (m) that is a function of the cumulative number m may be used. That is, the voltage value and time width of the recovery pulse Pr (m) can be changed according to the cumulative number m. For example, a recovery pulse voltage Vr (m) and a recovery pulse time width Tr (m) that are functions of the cumulative number m are used. For example, the recovery pulse voltage Vr (m) is increased as the cumulative number m increases. Further, for example, the recovery pulse time width Tr (m) is increased as the cumulative number m increases. Moreover, these are used together.

  Furthermore, the number of subpulses when the recovery pulse Pr (m) includes a plurality of subpulses, and the voltage value and time width of each subpulse may be changed based on the cumulative number m. For example, the recovery pulse Pr (m) is composed of subpulses having a constant recovery pulse voltage Vrs and a constant recovery pulse time width Trs, and the number of subpulses is increased as the cumulative number m increases. can do.

  As a result, the deterioration in the laminated insulating film 3 is efficiently suppressed, and when the cumulative number m is small, the time required for applying the recovery pulse Pr (m) can be shortened and it is easy to use.

  Also, changing the set number N (m) according to the cumulative number m and changing the recovery pulse Pr (m) may be performed simultaneously.

FIG. 13 is a schematic view illustrating the operation of the nonvolatile semiconductor memory device according to the third embodiment of the invention.
This figure illustrates a part of the repetition of the write operation and the erase operation.
As shown in FIG. 13, in the nonvolatile semiconductor memory device 103, the first recovery pulse Prm1 is applied to the memory cell 8 that has undergone a cycle of a certain write operation and erase operation. In this specific example, the first recovery pulse Prm1 is a single pulse, the voltage value thereof is, for example, 20 V, and the time width is 150 ms.

  Then, for example, after the write operation and the erase operation are repeated 30 times, the second recovery pulse Prm2 is applied. In this specific example, the second recovery pulse Prm2 has a voltage value of 22V, a first subpulse Pr1 having a time width of 80 ms, a second subpulse Pr2 having a voltage value of 24V and a time width of 120 ms, and a voltage value of 20V. And a third sub-pulse Pr3 having a time width of 100 ms.

  Then, for example, after the write operation and the erase operation are repeated 20 times, the third recovery pulse Prm3 is applied. In this specific example, the third recovery pulse Prm3 is a single pulse, and has a voltage value of 26 V and a time width of 500 ms.

  Thus, the interval (interval) of the repetitive operation when applying the recovery pulse Pr can be arbitrarily changed, and the voltage value, the time width, and the number of pulses (sub-pulses) included in each of the recovery pulses Pr are as follows. Is optional.

(Fourth embodiment)
FIG. 14 is a flowchart illustrating the operation of the nonvolatile semiconductor memory device according to the fourth embodiment of the invention.
FIG. 15 is a schematic view illustrating the operation of the nonvolatile semiconductor memory device according to the fourth embodiment of the invention.
As shown in FIGS. 14 and 15, in the nonvolatile semiconductor memory device 104 according to this embodiment, the order in the combination of the write operation and the erase operation is opposite to the order in the nonvolatile semiconductor memory device 101.
That is, in the nonvolatile semiconductor memory device 104, the erase operation (step S130) is performed before the write operation (step S110). Then, after the write operation, data is held for an arbitrary period (step S120). Then, when rewriting or erasing the stored data, for example, a predetermined trigger is obtained and the process proceeds to the next step. At that time, the number n of repetitions of the operation is determined (step S140).

If the number n of repetitions of the operation is smaller than the set number N, the process returns to step S106, and the erase operation and the write operation are performed again.
When the number n of repetitions of the operation reaches the set number N, the recovery pulse Pr is applied as the recovery operation. In this specific example, the initialization operation, that is, the initialization pulse Pi is omitted. Then, the next write operation is performed through the erase operation. Also in this case, it is possible to provide a nonvolatile semiconductor memory device in which the reliability of repeated operation of the charge storage type memory cell is improved.

As described above, when the erase operation is performed before the write operation, the initialization operation (application of the initialization pulse Pi) after the recovery operation (application of the recovery pulse Pr) can be omitted.
It should be noted that the operation without this erasing operation, the operation of configuring the recovery pulse Pr described with respect to the second embodiment with a plurality of pulses, the set number of times N based on the cumulative number m described with respect to the third embodiment, The operation of changing the recovery pulse Pr can be performed in combination.

(Fifth embodiment)
FIG. 16 is a schematic view illustrating the configuration of the nonvolatile semiconductor memory device according to the fifth embodiment of the invention.
As shown in FIG. 16, in the nonvolatile semiconductor memory device 105 according to this embodiment, the stacked structure 3 is provided on the semiconductor layer 1. A gate electrode 4 is provided on the laminated structure 3. The laminated structure 3 includes a charge storage layer 3B and a first insulating film 3A provided between the charge storage layer 3B and the semiconductor layer 1. As described above, the nonvolatile semiconductor memory device 105 has a structure in which the second insulating film 3C is omitted from the nonvolatile semiconductor memory device 101 illustrated in FIG.

Also in this case, the drive unit 20 lowers the potential of the gate electrode 4 than the semiconductor layer 1 and performs at least one of data writing and erasing operations (in this example, the erasing pulse Pe). ) Is applied between the semiconductor layer 1 and the gate electrode 4, and the potential of the gate electrode 4 is made higher than that of the semiconductor layer 1 based on the number n of times of application of the first pulse P 1. A second pulse P2 (recovery pulse Pr) is injected between the semiconductor layer 1 and the gate electrode 4.
Thereby, even in the structure in which the second insulating film 3C is omitted, it is possible to improve the repetitive operation reliability of the charge storage type memory cell.
Note that the operations described in the second to fourth embodiments may be applied to a nonvolatile semiconductor memory device having a structure in which the second insulating film 3C is omitted.

  In the above description, the memory cell 8 has an N channel, but the memory cell 8 may have a P channel. In this case, the data write operation is performed by hole injection, and the erase operation is performed by electron injection. That is, the polarities of the voltages of the write pulse Pw and the erase pulse Pe are opposite to those of the N channel. As already described, a positive pulse is used as the recovery pulse Pr at this time as well.

  In addition, since the effect of applying the recovery pulse Pr in the nonvolatile semiconductor memory device according to the embodiment of the present invention relates to the characteristics of the memory cell 8, it does not depend on the connection method at the circuit level, and an arbitrary circuit It can be applied to the configuration. Therefore, the present invention can be applied to a nonvolatile semiconductor memory device having an arbitrary circuit configuration such as a NAND type, a NOR type, an AND type, and a DINOR type.

(Sixth embodiment)
FIG. 17 is a schematic view illustrating the configuration of the nonvolatile semiconductor memory device according to the sixth embodiment of the invention.
As illustrated in FIG. 17, another nonvolatile semiconductor memory device 106 according to the present embodiment includes a memory cell array 11 in which a plurality of the memory cells 8 are arranged, a drive unit 20 that drives the memory cell array 11, Have

The drive unit 20 includes a voltage control circuit 12. The voltage control circuit 12 includes the control unit 22 and the output unit 21 already described. The control unit 22 is provided with, for example, a storage unit 23 that stores the number n of application times of the first pulse P1 and the cumulative number m. Further, a calculation unit 24 may be provided.
The drive unit 20 can further include a voltage generation circuit 13, and the power supply voltage generated by the voltage generation circuit 13 is supplied to the voltage control circuit 12, and the write pulse Pw, erase pulse Pe, and recovery described above are performed. A pulse Pr and an initialization pulse Pi are generated and applied to each memory cell 8 of the memory cell array 11.
Further, the drive unit 20 can include a read circuit 14 and reads the threshold value of each memory cell 8 of the memory cell array 11 to read stored information.

The drive unit 20 performs the operations described with respect to the first to fifth embodiments.
Note that at least a part of the driving unit 20 can be provided on a substrate on which the memory cell array 11 is provided. Thereby, a high-density and small nonvolatile semiconductor memory device can be obtained.

(Seventh embodiment)
In the first to sixth embodiments, the nonvolatile semiconductor memory device is applied with the second pulse P2 based on the number of times of application of the first pulse P1, but the nonvolatile semiconductor memory device according to the present embodiment is also applied. In 107, the second pulse P2 is applied independently of the first pulse P1. That is, for example, the second pulse P2 is applied based on time.

The configuration of the nonvolatile semiconductor memory device 107 can be the same as that of the nonvolatile semiconductor memory devices 101, 105, and 106 illustrated in FIGS. 1, 16, and 17, respectively. An operation of the semiconductor memory device 107 will be described.
FIG. 18 is a flowchart illustrating the operation of the nonvolatile semiconductor memory device according to the seventh embodiment of the invention.

  As shown in FIG. 18, in the nonvolatile semiconductor memory device 107 according to the present embodiment, the drive unit 20 performs a write operation (step S110), and then holds arbitrary data (S120). An erase operation is performed (step S130). At this time, it is determined whether or not the elapsed time tt in the nonvolatile semiconductor memory device 107 is equal to or longer than a predetermined set time TT (predetermined value) (step S140). When the elapsed time tt is shorter than the set time TT, the process returns to step S110 again, and the write operation, data retention, and erase operation are repeated. When the elapsed time tt is equal to or longer than the set time TT, the recovery operation is performed by applying the recovery pulse Pr (second pulse P2) (step S150). Then, an initialization operation is performed by applying an initialization pulse Pi as necessary (step S160). Thereafter, the elapsed time tt is set to 0 as necessary (step S105). Note that when the accumulated elapsed time is used as the elapsed time tt, step S105 is not provided, and a plurality of set times TT can be prepared.

  Through the above operation, for example, a recovery operation can be performed periodically, and the repetitive operation reliability of the charge storage type memory cell can be improved. For example, a timer is provided in, for example, the arithmetic unit 24 of the nonvolatile semiconductor memory device 107, and a set time TT is stored in the memory unit 23, for example, so that the time is recovered when the time based on the set time TT has passed. A pulse Pr is applied. At this time, the recovery pulse Pr is not applied at the moment when the time passes the time based on the set time TT, but at least one of the write operation and the erase operation after the time passes the time based on the set time TT. When performing, the recovery pulse Pr may be applied.

  As described above, in the nonvolatile semiconductor memory device 107, the driving unit 20 applies the first pulse P <b> 1 for performing either data writing or erasing by lowering the potential of the gate electrode 4 than the semiconductor layer 1. 1 is applied between the gate electrode 4 and the potential of the gate electrode 4 is set higher than that of the semiconductor layer 1 based on a predetermined time (for example, the set time TT described above), and electrons are transferred to the stacked structure 3. A second pulse P2 for injecting is applied between the semiconductor layer 1 and the gate electrode 4.

  Also in this case, the predetermined time, that is, the interval (interval) at which the recovery pulse Pr is applied may be changed as time (cumulative time) elapses, and the voltage value and time width of the recovery pulse Pr may be changed. In addition, the number of pulses (sub-pulses) included therein can be arbitrarily changed.

  In the nonvolatile semiconductor memory device 107, when the plurality of memory cells 8 are provided, the second pulse P2 can be applied to the plurality of memory cells 8 at a time based on a predetermined time. For example, when the plurality of memory cells 8 are divided into a plurality of blocks, the second pulse P2 can be applied for each block. Thereby, deterioration of a plurality of memory cells can be efficiently suppressed.

(Eighth embodiment)
In the seventh embodiment, the second pulse P2 is applied based on time in the nonvolatile semiconductor memory device. However, in the nonvolatile semiconductor memory device according to the present embodiment, for example, it is given by the user. A second pulse P2 is applied based on the activation signal.

FIG. 19 is a schematic view illustrating the configuration of the nonvolatile semiconductor memory device according to the eighth embodiment of the invention.
As illustrated in FIG. 19, the nonvolatile semiconductor memory device 108 according to the present embodiment further includes an input unit 25 to which the activation signal 25I is input, in addition to the memory cell 8 and the drive unit 20 described above. The input unit 25 is connected to, for example, the control unit 22 of the drive unit 20.

  The activation signal 25I input to the input unit 25 is an electric signal based on, for example, a “refresh command” arbitrarily input from a user using the nonvolatile semiconductor memory device, for example. That is, in various electronic devices in which the nonvolatile semiconductor memory device is mounted, an electric signal to be recovered from the user is input to the input unit 25 as the activation signal 25I at a desired timing. That is, the activation signal 25I is a signal for executing the operation for recovering the characteristics of the laminated insulating film 3 already described, unlike signals for normal writing and erasing to the nonvolatile semiconductor memory device. For example, when the user feels that the number of write operations and erase operations has exceeded a certain level in the nonvolatile semiconductor memory device, the user inputs a “refresh command” at a desired timing, and an electric signal based on this is input. A certain start signal 25I is generated in, for example, an electronic device.

  Based on the activation signal 25I input to the input unit 25, for example, the control unit 22 generates a predetermined signal and applies the recovery pulse Pr to the memory cell 8. As a result, a nonvolatile semiconductor memory device in which the reliability of repeated operation of the charge storage type memory cell is improved can be provided.

  Note that, in the nonvolatile semiconductor memory device 108, when a plurality of memory cells 8 are provided, the second pulse P2 can be applied to the plurality of memory cells 8. Further, for example, when the plurality of memory cells 8 are divided into a plurality of blocks, for example, a function can be given to designate a block in the “refresh command”, and based on this, the second pulse P2 is set. It can be applied for each block. Thereby, deterioration of a plurality of memory cells can be efficiently suppressed.

(Ninth embodiment)
The ninth embodiment of the present invention is a method for driving a nonvolatile semiconductor memory device.
That is, the semiconductor layer 1 having the source region 2a and the drain region 2b provided on both sides of the channel 1a and the channel 1a, the first insulating film 3A provided on the channel 1a, and the first insulating film 3A This is a method for driving a nonvolatile semiconductor memory device having a memory cell 8 having a charge storage layer 3B provided on the gate electrode 4 and a gate electrode 4 provided on the charge storage layer 3B. Hereinafter, characteristic portions of the nonvolatile semiconductor memory device according to the present embodiment will be described.

FIG. 20 is a flowchart illustrating the method for driving the nonvolatile semiconductor memory device according to the ninth embodiment of the invention.
As shown in FIG. 20, in the method for driving the nonvolatile semiconductor memory device according to this embodiment, first, the potential of the gate electrode 4 is made lower than that of the semiconductor layer 1 to perform either data writing or erasing. The first pulse P1 to be performed is applied between the semiconductor layer 1 and the gate electrode 4 (step S110).

  For example, as illustrated in FIG. 2, the erase pulse Pe is applied as the first pulse P1. As described above, in the specific example illustrated in FIG. 2, the write pulse Pw (third pulse P3) is also applied before the erase pulse Pe is applied, and data is held for an arbitrary period. Then, the application of the write pulse Pw and the erase pulse Pe is repeated, and the write operation and the erase operation are repeated.

Then, based on the number of times of application of the first pulse P1, the potential of the gate electrode 4 is made higher than that of the semiconductor layer 1, and the second pulse (recovery pulse Pr) for injecting electrons into the stacked structure 3 is applied to the semiconductor layer 1. And between the gate electrode 4 and the gate electrode 4 (step S120).
Thereby, it is possible to suppress the deterioration of the laminated insulating film 3, improve the reliability of element destruction, and provide a driving method of a nonvolatile semiconductor memory device that improves the reliability of repeated operation of a charge storage type memory cell. it can.

  For example, the second pulse P2 is applied when the number of times of application of the first pulse P1 reaches a preset number N, which is a predetermined value. At this time, as described above, the set number N may be changed based on the cumulative number m of application of the first pulse P1, and the voltage value of the second pulse P2, the time width, and the number thereof are included therein. The number of pulses (sub-pulses) to be generated may be changed.

The set number of times N is preferably 1 to 100 times.
The second pulse P2 is preferably 10V or more and 30V or less. The time width of the second pulse is preferably longer than 100 μs and not longer than 10 seconds, and more preferably not shorter than 1 ms and not longer than 10 seconds.

In addition, the third pulse P3 (the write pulse Pw in the specific example of FIG. 2) in which the potential of the gate electrode 4 is made higher than that of the semiconductor layer 1 to perform one of data writing and erasing is applied to the semiconductor layer 1 and the gate electrode 4. Apply between. In this case, it is desirable that the application time of the second pulse P2 (recovery pulse time width Tr) is longer than the application time of the third pulse (write pulse time width Tw in the specific example of FIG. 2).
As described above, element breakdown can be more effectively suppressed.

  When the nonvolatile semiconductor memory device includes a plurality of memory cells 8, the second pulse P <b> 2 is applied to the plurality of memory cells 8 based on the number of times the first pulse P <b> 1 is applied to the plurality of memory cells 8. be able to. The plurality of memory cells 8 are divided into a plurality of blocks, and the second pulse P2 can be applied for each block based on the number of times of application of the first pulse P1 for each block. Thereby, deterioration of a plurality of memory cells can be efficiently suppressed.

  Further, a fourth pulse P4 (initialization pulse Pi) that makes the potential of the gate electrode 4 higher than that of the semiconductor layer 1 can be applied between the application of the second pulse P2 and the application of the first pulse P1. As described with reference to FIGS. 14 and 15, the application of the fourth pulse P4 may be omitted.

In another driving method according to the present embodiment, first, the first pulse P1 for performing one of data writing and erasing by making the potential of the gate electrode 4 lower than that of the semiconductor layer 1 is applied to the semiconductor layer 1 and the gate. Applied between the electrodes 4. Then, based on a predetermined time (for example, the set time TT described above), the potential of the gate electrode 4 is made higher than that of the semiconductor layer 1, and the second pulse P2 for injecting electrons into the stacked structure 3 is applied to the semiconductor layer. 1 and the gate electrode 4.
Furthermore, in another driving method according to the present embodiment, first, the first pulse P1 for performing one of data writing and erasing by lowering the potential of the gate electrode 4 than the semiconductor layer 1 is applied to the semiconductor layer 1 and the gate. Applied between the electrodes 4. Then, for example, based on an activation signal according to a command input from the user, the second pulse P2 for injecting electrons into the stacked structure 3 memory cell 8 with the potential of the gate electrode 4 higher than that of the semiconductor layer 1 is generated. The voltage is applied between the semiconductor layer 1 and the gate electrode 4.
This can provide a method for driving a nonvolatile semiconductor memory device in which the reliability of repeated operation of charge storage type memory cells is improved.

  In any of the above driving methods, the interval (interval) at which the recovery pulse Pr is applied can be arbitrarily set, and the voltage value, time width, and number of pulses (sub-pulses) included in the recovery pulse Pr can be set. It can be changed arbitrarily.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, with regard to the specific configuration of each element constituting the nonvolatile semiconductor memory device and the driving method thereof, those skilled in the art can implement the present invention in the same manner by appropriately selecting from a known range, and obtain the same effect Is included in the scope of the present invention as long as possible.
Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, on the basis of the nonvolatile semiconductor memory device and its driving method described above as embodiments of the present invention, all nonvolatile semiconductor memory devices and their driving methods that can be implemented by those skilled in the art with appropriate design changes are also provided. As long as the gist of the invention is included, it belongs to the scope of the present invention.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

DESCRIPTION OF SYMBOLS 1 Semiconductor layer 1a Channel 2a Source region 2b Drain region 3 Laminated insulating film (laminated structure)
3A First insulating film 3B Charge storage layer 3C Second insulating film 4 Gate electrode 8 Memory cell 11 Memory cell array 12 Voltage control circuit 13 Voltage generation circuit 14 Read circuit 20 Drive unit 21 Output unit 22 Control unit 23 Storage unit 24 Calculation unit 25 Input unit 101, 102, 102 a, 103, 104, 105, 106, 107, 108, 109 Nonvolatile semiconductor memory device N Number of times set (predetermined value)
P1 1st pulse P2 2nd pulse P3 3rd pulse P4 4th pulse Pe Erase pulse Pi Initialization pulse Pr Recovery pulse Pr1 to Pr3 1st to 3rd subpulse Prm1 to Prm3 1st to 3rd recovery pulse Pw Write pulse T01 , T02 Rest period Te Erase pulse time width Th Holding period Ti Initialization pulse time width Tr, Tr (m), Trs Recovery pulse time width Tr1-Tr3 First to third sub-pulse time widths TT setting time (specified value)
Tw Write pulse time width Ve Erase pulse voltage Vg Gate voltage Vi Initialization pulse voltage Vr, Vrs Recovery pulse voltage Vr1-Vr3 First to third sub-pulse voltages Vw Write pulse voltage n times m Accumulated times tt Elapsed time

Claims (20)

A semiconductor layer having a channel and a source region and a drain region provided on both sides of the channel;
A laminated structure having a first insulating film provided on the channel, and a charge storage layer provided on the first insulating film;
A gate electrode provided on the stacked structure;
A memory cell having
Applying a first pulse between the semiconductor layer and the gate electrode for lowering the potential of the gate electrode lower than that of the semiconductor layer and writing or erasing data;
Based on the number of times of application of the first pulse, a second pulse for injecting electrons into the stacked structure by raising the potential of the gate electrode higher than the semiconductor layer is interposed between the semiconductor layer and the gate electrode. A drive unit to apply,
A nonvolatile semiconductor memory device comprising:   The said drive part further has a memory | storage part which memorize | stores the frequency | count of the said application, and applies the said 2nd pulse based on the frequency | count of the said application memorize | stored in the said memory | storage part. Nonvolatile semiconductor memory device.   3. The nonvolatile semiconductor memory device according to claim 1, wherein the driving unit applies the second pulse when the number of times of application reaches a predetermined value. 4.   4. The nonvolatile semiconductor memory device according to claim 3, wherein the predetermined value changes based on a cumulative number of times of application of the first pulse.   The nonvolatile semiconductor memory device according to claim 3, wherein the predetermined value is not less than 1 and not more than 100 times.   2. The voltage and application time in the second pulse, and / or the number of pulses included in the second pulse change based on the cumulative number of times of application of the first pulse. The nonvolatile semiconductor memory device according to any one of? The driving unit applies a third pulse between the semiconductor layer and the gate electrode to make the potential of the gate electrode higher than that of the semiconductor layer and perform one of writing and erasing of the data,
The nonvolatile semiconductor memory device according to claim 1, wherein the application time of the second pulse is longer than the application time of the third pulse.   The nonvolatile semiconductor memory device according to claim 1, wherein the application time of the second pulse is longer than 100 μs and not longer than 10 seconds.   9. The nonvolatile semiconductor memory device according to claim 1, wherein the potential of the gate electrode with respect to the semiconductor layer in the second pulse is higher than 10 V and lower than 30 V. 9. A plurality of the memory cells;
The non-volatile device according to claim 1, wherein the driving unit applies the second pulse to the plurality of memory cells based on the number of times of application in the plurality of memory cells. Semiconductor memory device. The plurality of memory cells are divided into a plurality of blocks,
The nonvolatile semiconductor memory device according to claim 10, wherein the driving unit applies the second pulse for each block based on the number of times of application for each block.   The driving unit applies a fourth pulse for lowering the potential of the gate electrode than the semiconductor layer between the application of the second pulse and the application of the first pulse for performing one of the next writing and erasing. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is applied between a semiconductor layer and the gate electrode.   The nonvolatile semiconductor memory according to claim 1, wherein the stacked structure further includes a second insulating film provided between the charge storage layer and the gate electrode. apparatus. A semiconductor layer having a channel and a source region and a drain region provided on both sides of the channel;
A laminated structure having a first insulating film provided on the channel, and a charge storage layer provided on the first insulating film;
A gate electrode provided on the stacked structure;
A memory cell having
Applying a first pulse between the semiconductor layer and the gate electrode for lowering the potential of the gate electrode lower than that of the semiconductor layer and writing or erasing data;
Driving to apply a second pulse for injecting electrons into the stacked structure by making the potential of the gate electrode higher than that of the semiconductor layer based on a predetermined time, between the semiconductor layer and the gate electrode And
A nonvolatile semiconductor memory device comprising: A semiconductor layer having a channel and a source region and a drain region provided on both sides of the channel;
A laminated structure having a first insulating film provided on the channel, and a charge storage layer provided on the first insulating film;
A gate electrode provided on the stacked structure charge storage layer;
A memory cell having
An input unit to which a start signal is input;
Applying a first pulse between the semiconductor layer and the gate electrode for lowering the potential of the gate electrode lower than that of the semiconductor layer and writing or erasing data;
Based on the activation signal input to the input unit, a second pulse for injecting electrons into the stacked structure by raising the potential of the gate electrode higher than that of the semiconductor layer is generated between the semiconductor layer and the gate electrode. A drive unit applied between,
A nonvolatile semiconductor memory device comprising: A semiconductor layer having a channel and a source region and a drain region provided on both sides of the channel; a first insulating film provided on the channel; and a charge storage layer provided on the first insulating film. A driving method of a nonvolatile semiconductor memory device having a memory cell having a stacked structure having a gate electrode provided on the charge storage layer,
Applying a first pulse between the semiconductor layer and the gate electrode for lowering the potential of the gate electrode lower than that of the semiconductor layer and writing or erasing data;
Based on the number of times of application of the first pulse, a second pulse for injecting electrons into the stacked structure by raising the potential of the gate electrode higher than the semiconductor layer is interposed between the semiconductor layer and the gate electrode. A method for driving a nonvolatile semiconductor memory device, comprising: applying the nonvolatile semiconductor memory device.   17. The method of driving a nonvolatile semiconductor memory device according to claim 16, wherein the second pulse is applied when the number of times of application reaches a predetermined value.   18. The method of driving a nonvolatile semiconductor memory device according to claim 16, wherein the predetermined value is 1 time or more and 100 times or less. The nonvolatile semiconductor memory device has a plurality of the memory cells,
The nonvolatile semiconductor memory device according to any one of claims 16 to 18, wherein the second pulse is applied to the plurality of memory cells based on the number of times of application in the plurality of memory cells. Driving method. The plurality of memory cells are divided into a plurality of blocks,
20. The method of driving a nonvolatile semiconductor memory device according to claim 19, wherein the second pulse is applied for each block based on the number of times of application for each block.