JP2010161149A - Trimming circuit, semiconductor device equipped with trimming circuit, and trimming method of the trimming circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that includes a built-in trimming circuit capable of reducing the area occupied by wiring, and to provide a trimming method for the device. <P>SOLUTION: In a fuse meltdown circuit k0 (k=1 to 4), a first signal for selecting whether the meltdown of a first fuse Fk1 is performed is input, when a fuse power source voltage Vp is input while a signal level of a clock signal CK is at a high level; and a second signal for selecting whether the meltdown of the corresponding trimming fuses TF1 to TF3 is performed is input, when a fuse power source voltage Vp is input, while a signal level of a clock signal CK is at a low level. The fuse meltdown circuit outputs the output signals of a memory circuit, including an inverter circuit k2 and NMOS transistors Mk3, Mk4 for temporarily maintaining the state of the first fuse Fk1, when a clock signal CK is at a low level while the next clock signal CK is at a high level as the first signal and the second signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a trimming circuit that selectively blows a current blown trimming fuse, a semiconductor device including the trimming circuit, and a trimming method for the trimming circuit.

In semiconductor devices, variations in the manufacturing process caused variations in each element of the circuit, which varied the circuit characteristics. For this reason, conventionally, when high-precision characteristics are required, the characteristics are improved by trimming. In addition, a trimming circuit is also used when characteristics such as output voltage and output current are changed depending on applications.
FIG. 5 is a circuit diagram showing an example of a conventional bias voltage generating circuit (see, for example, Patent Document 1).
In the circuit of FIG. 5, diode-connected NMOS transistors M102 to M106 are connected in series between the source of a depletion type NMOS transistor M101 biased at 0V and the ground voltage GND. Further, trimming fuses F101 to F104 are connected correspondingly between the source and drain of the NMOS transistors M103 to M106.

In the operation of the circuit of FIG. 5, the drain current of the depletion type NMOS transistor M101 biased to 0V is supplied to the diode-connected NMOS transistor 102, and the bias voltage VRG is applied from the connection between the depletion type NMOS transistor M101 and the NMOS transistor 102. Is output.
By selectively blowing the trimming fuses F101 to F104, an NMOS transistor connected in series to the NMOS transistor M102 is added, so that the bias voltage VRG can be set to increase.

In order to blow the trimming fuses F101 to F104, fusing voltage application terminals T1 to T5 are connected. For example, when the trimming fuse F101 is blown, a high fusing voltage is applied between the fusing voltage application terminals T1 and T2.
As described above, in the current fusing type trimming circuit, since a high fusing voltage is applied to each trimming fuse, the number of external terminals of the semiconductor device increases and the package becomes large. Such a large package increases the cost and hinders downsizing of the device, and therefore, reduction of the number of terminals used for trimming has been demanded.

FIG. 6 is a block diagram showing a configuration example of a conventional trimming circuit (see, for example, Patent Document 2).
In FIG. 6A, the serial / parallel converter receives serial data SD from the chip terminals TM and BP or the dedicated pad P when not operating (manufacturing), and converts the serial data SD into parallel data Q1 to Qm. Convert and output. The trimming circuit section cuts the corresponding fuse in accordance with the parallel data Q1 to Qm input from the serial / parallel conversion section. In FIG. 6A, by using one data input line, a fuse corresponding to an arbitrary bit among m bits can be trimmed, and trimming for m bits can be performed simultaneously. In this case, only one dedicated pad P is required as the data input line.

Further, the chip pad system for the original input signal as the data input line, that is, the chip input terminal TM, or the one dedicated pad P can be deleted by diverting the bonding pad BP before molding. it can. Therefore, the number of dedicated pads for trimming can be greatly reduced, and the work related to trimming can be greatly reduced.
In FIG. 6B, the decoder decodes parallel data D1 to Dn from a plurality of chip terminal systems TM and BP. The trimming circuit section cuts or uncuts the corresponding fuse circuits FC1 to FCn (not shown) according to the decode output signals Q1 to Qn of the decoder. According to such a circuit, it is possible to perform trimming for 2n bits by using a slightly n-bit data input line. Although trimming for 2n bits is performed individually, the parallel data D1 to Dn may be set so as to indicate only the fuse circuit to be trimmed.

  Next, in the circuit of FIG. 6C, the counter CTR counts the clock signal CLK from the chip terminal system TM, BP or the dedicated pad P. The decoder decodes the count value Q of the counter CTR, and the trimming circuit section cuts / uncuts the corresponding fuse circuits FC1 to FCn (not shown) according to the output signals Q1 to Qn of the decoder. In this way, trimming can be performed for an arbitrary number of bits by using one clock input line. Such trimming is performed individually, but the clock signal CLK may be input so as to indicate only the fuse circuit to be trimmed. The circuit of FIG. 6C can greatly reduce the number of dedicated pads for trimming as in the case of FIG.

Japanese Patent Laid-Open No. 2002-231889 JP-A-8-204582

However, the circuit as shown in FIG. 6 requires complex logic circuits such as a serial / parallel conversion circuit, a decoder, and a counter. These circuits occupy a large area on the semiconductor chip, and the size of the semiconductor chip is small. It was a hindrance to conversion.
Conventionally, as shown in FIG. 7, the trimming fuse block A for the circuit portion A is arranged at the upper left of the semiconductor chip, and the trimming fuse block B for the circuit portion B is arranged at the lower left of the semiconductor chip. The trimming fuse block C for the portion C is arranged on the right side of the center of the semiconductor chip. As described above, when the trimming fuse blocks A, B, and C are scattered and arranged in the semiconductor chip, the wiring to the logic circuit section and the trimming fuse block becomes long, and the chip used for the wiring The area was no longer negligible. For example, if there are 10 trimming fuses in each trimming fuse block, usually 10 or more wirings between the logic circuit section and each trimming fuse block are required.

  The present invention has been made to solve such a problem. Trimming fuses are arranged in various parts of a semiconductor chip without using a complicated logic circuit that requires a large chip area. However, it is an object of the present invention to obtain a trimming circuit capable of reducing an area due to wiring, a semiconductor device including the trimming circuit, and a trimming method for the trimming circuit.

The trimming circuit according to the present invention includes a fuse blowing circuit that fuses a trimming fuse connected to a fuse output terminal by inputting a fuse power supply voltage, and selectively trims the trimming fuse.
The fuse blowing circuit is
A first fuse;
A clock input terminal to which a predetermined clock signal is input;
When the fuse power supply voltage is input when the signal level of the clock signal is the first level, the first signal input to the first input terminal for selecting whether or not to blow the first fuse is selected. A first fuse blowing circuit unit for blowing the first fuse in response to one signal;
Whether or not the trimming fuse input to the second input terminal is blown when the fuse power supply voltage is input when the signal level of the clock signal is a second level obtained by inverting the first level A trimming fuse fusing circuit unit for fusing the trimming fuse in response to a second signal for selecting
A storage circuit unit that temporarily holds and outputs the state of the first fuse when the clock signal is at the second level while the clock signal is at the next first level;
With
The memory circuit unit outputs the held signal indicating the state of the first fuse as the first signal from the first output terminal to the first input terminal and as the second signal from the second output terminal. It outputs to 2 input terminals.

Also, comprising a plurality of the fuse blowing circuits cascaded from the upper to the lower,
Each of the fuse blowing circuits has the first output terminal connected to the first input terminal of the fuse blowing circuit connected to a lower level, and the fuse blowing of the second output terminal connected to a higher level. Connected to the second input terminal of the circuit;
The fuse blowing circuit connected to the top is input to the first input terminal, the first signal indicating that the first fuse is blown,
The fuse fusing circuit connected at the bottom is configured so that the trimming fuse is not connected to the fuse output terminal.

  Further, a first blocking means for blocking an external clock signal input from the outside that forms the clock signal is provided.

  Specifically, the first breaking means is constituted by a second fuse that blows when a fusing current of a first predetermined value or more flows.

  Further, a second shut-off means for shutting off the input of the fuse power supply voltage is provided.

  Specifically, the second breaking means is constituted by a third fuse that blows when a fusing current of a second predetermined value or more flows.

  The third fuse has a larger fusing current than the trimming fuse.

  A semiconductor device according to the present invention includes any one of the trimming circuits.

The trimming method according to the present invention is the trimming method in the trimming circuit,
The fuse power supply voltage is inputted while the clock signal goes through the second level state to the next first level state, and the first fuse in the fuse blowing circuit is blown out. Process,
A second step of inputting the fuse power supply voltage only when the trimming fuse is blown while the clock signal is in the next second level state;
To do.

In the trimming method according to the present invention, in the trimming method in the trimming circuit, the fuse power supply voltage is applied while the clock signal is in the next first level state after the second level state. A first step of inputting and fusing the first fuse in the fuse fusing circuit connected to the highest level;
A second step of inputting the fuse power supply voltage only when the trimming fuse connected to the uppermost fuse blow circuit is blown while the clock signal is in the next second level state;
Next, when the clock signal is inverted to the first level, a third step of blowing the first fuse in the fuse fusing circuit connected immediately below,
The fuse power supply voltage is inputted only when the trimming fuse connected to the fuse blowing circuit connected immediately below is blown while the clock signal is in the next second level state. 4 steps,
And
Similarly, the third step of blowing the first fuse in the lower fuse blowing circuit and the fourth step of blowing the trimming fuse connected to each fuse blowing circuit in order. Repeatedly, the trimming operation is finished when the third step of cutting the first fuse in the fuse blowing circuit connected to the lowest is finished.

  Further, when the trimming operation is completed, the input of the external clock signal from the outside forming the clock signal is blocked.

  Further, when the trimming operation is completed, the input of the fuse power supply voltage is cut off.

According to the trimming circuit of the present invention and the semiconductor device including the trimming circuit, each fuse blowing circuit can be configured to be extremely small, so that the fuse blowing circuit can be disposed in the vicinity of the trimming fuse.
Furthermore, these small-scale fuse blow circuits are connected in cascade, and the trimming fuses connected to the lower fuse blow circuit are trimmed in synchronization with the clock signal in order from the trimming fuse connected to the uppermost fuse blow circuit. As a result, the circuit scale of the entire trimming circuit can be reduced.

  Also, the first fuse in the fuse blown circuit is blown in the state of the clock signal half a cycle before the trimming fuse is blown or not blown, and the result is output to the fuse blower circuit connected to the upper and lower sides. As a result, a signal for specifying the fuse to be trimmed becomes unnecessary, and only two signal lines necessary for the fuse blowing circuit, that is, the clock signal and the fuse power supply voltage for performing the fuse blowing, The space for trimming wiring can also be reduced.

  Further, according to the trimming method of the present invention, the fuse power supply voltage is always inputted when the clock signal is at the first level, and the first fuses in the fuse blowing circuit are cascade-connected, starting from the second level of the clock signal. The fuse power supply voltage is input only when the fuse is blown out by determining whether the trimming fuse is blown or not at the second level of the next clock signal after the first fuse is blown. Therefore, many trimming fuses can be processed in a short time by repeating simple steps.

  Furthermore, since the input of the external clock signal and / or the fuse power supply voltage is interrupted after the trimming is completed, no malfunction occurs even if the external clock signal or the fuse power supply voltage is input after the trimming operation is completed. Can be.

It is a figure showing an example of a trimming circuit in a 1st embodiment of the present invention. 2 is a timing chart showing an example of signals at various parts of the trimming circuit 1 of FIG. 1. 2 is a flowchart showing an example of a trimming method for the fuse blow circuit of FIG. 1. It is the flowchart which showed the trimming method of the trimming circuit formed by cascade-connecting many fuse fusing circuits. It is a circuit diagram showing a conventional bias voltage generation circuit. It is the figure which showed the circuit example of the conventional trimming circuit. It is the figure which showed the example of a layout of the semiconductor chip incorporating the conventional trimming circuit.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 is a diagram showing a circuit example of a trimming circuit according to the first embodiment of the present invention.
In FIG. 1, a trimming circuit 1 includes fuse blowing circuits 10, 20, 30, 40 having the same circuit configuration, inverter circuits 2, 3, trimming fuses TF1 to TF3, diodes D1 to D4, resistors R1 to R9, second It comprises a fuse F2 and a third fuse F3, and further comprises an external clock input terminal CKi and a fuse power input terminal Vppi.

Since the fuse blowing circuits 10, 20, 30, and 40 all have the same circuit configuration, the fuse blowing circuit 10 will be described.
The fuse blowing circuit 10 includes a 2-input NAND circuit 11, two inverter circuits 12, 13, a 3-input NAND circuit 14, PMOS transistors M11 and M15, NMOS transistors M12 to M14, NPN transistors Q11 and Q12, and resistors R11 to R13. And the first fuse F11. Further, the fuse blowing circuit 10 includes a clock signal input terminal CK10 to which a clock signal CK is input, a reverse clock signal input terminal CKB10 to which a reverse clock signal CKB having a phase opposite to that of the clock signal CK is input, a first input terminal IN11, A two-input terminal IN12, a first output terminal OUT11, a second output terminal OUT12, a fuse output terminal OUT10, and a fuse power supply terminal Vpp are provided.

  Although not shown, the fuse blowing circuit 10 also includes a power supply terminal to which the power supply voltage Vcc is input and a ground terminal connected to the ground voltage GND. Although the internal circuits of the fuse blowing circuits 30 and 40 are omitted, the following description will be made assuming that they are the same circuit elements as the fuse blowing circuit 10. Further, the subscripts of the constituent elements of the fuse blowing circuits 10, 20, 30, 40 are such that the tenth digits are the same as the tenth digits of the fuse blowing circuits 10, 20, 30, 40, respectively. I have to. For example, if the first fuse of the fuse blowing circuit 10 is F11, the fuse blowing circuits 20, 30 and 40 are like the first fuses F21, F31 and F41.

  Further, the NAND circuit k1 (k = 1 to 4), the PMOS transistor Mk1, the NPN transistor Qk1, and the resistor Rk1 form a first fuse blowing circuit unit, and the inverter circuit k3, the NAND circuit k4, the PMOS transistor k5, the NPN transistor Qk2, and the resistor Rk3 forms a trimming fuse blow circuit part, and the inverter circuit k2, NMOS transistors Mk2 to Mk4, and resistor Rk2 form a memory circuit part.

  In the NAND circuit 11, the first input terminal is connected to the reverse clock signal input terminal CKB10, the second input terminal is connected to the first input terminal IN11, and the output terminal is connected to the gate of the PMOS transistor M11. The source of the PMOS transistor M11 is connected to the fuse power supply terminal Vpp, and the drain of the PMOS transistor M11 is connected to the ground voltage GND through the resistor R11 and is connected to the base of the NPN transistor Q11. The collector of the NPN transistor Q11 is connected to the fuse power supply terminal Vpp, and the emitter of the NPN transistor Q11 is connected to the ground voltage GND through the first fuse F11 and is connected to the source of the NMOS transistor M12.

The gate of the NMOS transistor M12 is connected to the clock signal input terminal CK10, the drain of the NMOS transistor M12 is connected to the power supply voltage Vcc via the resistor R12, and is connected to the input terminal of the inverter circuit 12 and the drain of the NMOS transistor M13. Each is connected.
The gate of the NMOS transistor M13 is connected to the output terminal of the inverter circuit 12, and the source of the NMOS transistor M13 is connected to the drain of the NMOS transistor M14. The gate of the NMOS transistor M14 is connected to the reverse clock signal input terminal CKB10, and the source of the NMOS transistor M14 is connected to the ground voltage GND.

  The output terminal of the inverter circuit 12 is further connected to the input terminal of the inverter circuit 13 and the second output terminal OUT12. The output terminal of the inverter circuit 13 is connected to the first output terminal OUT11 and the second input terminal of the NAND circuit 14, respectively. In the NAND circuit 14, the first input terminal is connected to the clock signal input terminal CK10, the third input terminal is connected to the second input terminal IN12, and the output terminal is connected to the gate of the PMOS transistor M15. The source of the PMOS transistor M15 is connected to the power supply voltage Vcc, and the drain of the PMOS transistor M15 is connected to the ground voltage GND through the resistor R13 and is connected to the base of the NPN transistor Q12.

The collector of the NPN transistor Q12 is connected to the fuse output terminal OUT10, and the emitter of the NPN transistor Q12 is connected to the ground voltage GND. Further, the reverse clock signal CKB is input to the reverse clock signal input terminal CKB10, and the clock signal CK is input to the clock signal input terminal CK10.
The first input terminal IN11 is connected to the power supply voltage Vcc, the second input terminal IN12 is connected to the second output terminal OUT22 of the fuse blowing circuit 20, and the first output terminal OUT11 is connected to the first input of the fuse blowing circuit 20. Connected to the terminal IN21, the second output terminal OUT12 is open. The fuse output terminal OUT10 is connected to one end of the trimming fuse TF1 and the connection portion of the resistors R3 and R4.

  A reverse clock signal CKB is input to the reverse clock signal input terminal CKB20 of the fuse blowing circuit 20, and a clock signal CK is input to the clock signal input terminal CK20. As described above, the first input terminal IN21 is connected to the first output terminal OUT11 of the fuse blowing circuit 10, and the second input terminal IN22 is connected to the second output terminal OUT32 of the fuse blowing circuit 30. The first output terminal OUT21 is connected to the first input terminal IN31 of the fuse blowing circuit 30, and the second output terminal OUT22 is connected to the second input terminal IN12 of the fuse blowing circuit 10 as described above. The fuse output terminal OUT20 is connected to one end of the trimming fuse TF2 and a connection portion between the resistors R5 and R6.

  Further, the reverse clock signal CKB30 is input to the reverse clock signal input terminal CKB30 of the fuse blowing circuit 30, and the clock signal CK is input to the clock signal input terminal CK30. As described above, the first input terminal IN31 is connected to the first output terminal OUT21 of the fuse blowing circuit 20, and the second input terminal IN32 is connected to the second output terminal OUT42 of the fuse blowing circuit 40. The first output terminal OUT31 is connected to the first input terminal IN41 of the fuse blowing circuit 40, and the second output terminal OUT32 is connected to the second input terminal IN22 of the fuse blowing circuit 20 as described above. The fuse output terminal OUT30 is connected to one end of the trimming fuse TF3 and a connection portion of the resistors R6 and R7.

  In addition, the reverse clock signal CKB is input to the reverse clock signal input terminal CKB40 of the fuse blowing circuit 40, and the clock signal CK is input to the clock signal input terminal CK40. As described above, the first input terminal IN41 is connected to the first output terminal OUT31 of the fuse blowing circuit 30, and the second input terminal IN42 is connected to the ground voltage GND. The first output terminal OUT41 is open, the second output terminal OUT42 is connected to the second input terminal IN32 of the fuse fusing circuit 30 as described above, the fuse output terminal OUT40 is open, and the trimming fuse Is not connected.

  The input terminal of the inverter circuit 2 is connected to the external clock signal input terminal CKi via the second fuse F2, and a resistor R1 and a diode D1 are connected in parallel between the input terminal of the inverter circuit 2 and the ground voltage GND. Has been. The diode D1 has a cathode connected to the input terminal of the inverter circuit 2 and an anode connected to the ground voltage GND. The output terminal of the inverter circuit 2 is connected to the input terminal of the inverter circuit 3 and is an output terminal for outputting the reverse clock signal CKB. As described above, the reverse terminal in the fuse blowing circuits 10, 20, 30, 40 is used. The clock signal input terminals CKB10, CKB20, CKB30, and CKB40 are connected respectively. The output terminal of the inverter circuit 3 is an output terminal for outputting the clock signal CK, and is connected to the clock signal input terminals CK10, CK20, CK30, CK40 in the fuse blowing circuits 10, 20, 30, 40 as described above. Has been.

  The resistors R3 to R9 are connected in series, and the series circuit is connected between the voltage Vout and the ground voltage GND. The voltage Vout is, for example, an output voltage Vout of a constant voltage circuit (not shown), and the resistors R3 to R9 divide the output voltage Vout and feed it back to, for example, an input terminal of an error amplification circuit that forms a control circuit of the constant voltage circuit. Used for applications. A feedback voltage Vfb is output from a connection portion between the resistor R8 and the resistor R9. A trimming fuse TF1 is connected in parallel to the resistor R4, a trimming fuse TF2 is connected in parallel to the resistor R5, and a trimming fuse TF3 is connected in parallel to the resistor R7. By selectively blowing the trimming fuses TF1 to TF3, the feedback voltage Vfb can be adjusted to decrease.

  A connection portion between the resistors R3 and R4 is connected to the fuse output terminal OUT10 of the fuse blowing circuit 10, and a cathode of the diode D3 is connected to a connection portion between the resistors R4 and R5. The anode of the diode D3 is connected to one end of the third fuse F3, and the other end of the third fuse F3 is connected to the fuse power supply input terminal Vppi. A connection portion between the resistors R5 and R6 is connected to the fuse output terminal OUT20 of the fuse blowing circuit 20, and a connection portion between the resistors R6 and R7 is connected to the fuse output terminal OUT30 of the fuse blowing circuit 30.

  The cathode of the diode D4 is connected to the connection between the resistor R7 and the resistor R8, and the anode of the diode D4 is connected to one end of the third fuse F3. A resistor R2 and a diode D2 are connected in parallel between one end of the third fuse F3 and the ground voltage GND. The cathode of the diode D2 is connected to one end of the third fuse F3, and the anode of the diode D2 is connected to the ground voltage GND. It is connected. The fusing current of the third fuse F3 is set to be larger than the fusing currents of the trimming fuses TF1 to TF3.

In such a configuration, FIG. 2 is a timing chart for explaining the operation of the trimming circuit 1 of FIG. 1, and the operation of the trimming circuit 1 will be described with reference to FIG. In FIG. 2, the timing chart of the fuse blowing circuit 40 is omitted.
First, the operation of each unit in the period P1H in which the external clock signal CLK input to the external clock input terminal CKi is at a high level will be described.
The first input terminal IN11 of the fuse blowing circuit 10 is at a high level because the power supply voltage Vcc is input. Since the reverse clock signal CKB is at a low level, the output signal A10 of the NAND circuit 11 is at a high level.

Since the output signal A10 is a gate signal of the PMOS transistor M11, the PMOS transistor M11 is turned off to be cut off and the base current of the NPN transistor Q11 is cut off, so that the NPN transistor Q11 is turned off. The high-level output voltage of the NAND circuit 11 is level-shifted according to the voltage level of the fuse power supply terminal Vpp.
Since the clock signal CK is input to the gate of the NMOS transistor M12, the NMOS transistor M12 is on. Since the source of the NMOS transistor M12 is grounded via the first fuse F11, the input signal B10 of the inverter circuit 12 becomes low level. As a result, the second output terminal OUT12 connected to the output terminal of the inverter circuit 12 is obtained. Becomes high level. The high level signal is input to the gate of the NMOS transistor M13, and the NMOS transistor M13 is turned on. Further, since the reverse clock signal CKB is input to the gate of the NMOS transistor M14, the NMOS transistor M14 is turned off.

  Since the output signal of the inverter circuit 12 is at a high level, the output signal of the inverter circuit 13 is at a low level, and the low level signal is output to the first output terminal OUT11 and the second input terminal of the NAND circuit 14, respectively. . When the second input terminal of the NAND circuit 14 becomes low level, the output signal of the NAND circuit 14 becomes high level. For this reason, the PMOS transistor M15 is turned off and the NPN transistor Q12 is also turned off.

  Further, since the first output terminal OUT11 of the fuse blowing circuit 10 is at a low level, the first input terminal IN21 of the fuse blowing circuit 20 is also at a low level, and the reverse clock signal CKB20 is also at a low level. Output signal A20 becomes high level. That is, the state of each part of the fuse blowing circuit 20 is the same as that of the fuse blowing circuit 10, the first output terminal OUT21 is at a low level, and the second output terminal OUT22 is at a high level. Since the states of the first input terminals IN31 and IN41 of the fuse blowing circuits 30 and 40 and the reverse clock signal input terminals CKB30 and CKB40 are the same as those of the fuse blowing circuit 20, the first output terminals OUT31 and OUT41 are respectively set to a low level. The second output terminals OUT32 and OUT42 are each at a high level.

Next, the operation of each part in the period P1L in which the signal level of the external clock signal CLK is inverted to become a low level will be described.
When the external clock signal CLK becomes low level, the reverse clock signal CKB becomes high level, so that the output signal A10 of the NAND circuit 11 in the fuse blowing circuit 10 becomes low level. Then, when the PMOS transistor M11 is turned on and a predetermined voltage is input to the fuse power supply terminal Vpp, the base current flows through the NPN transistor Q11 and the NPN transistor Q11 can be turned on.

  Since the clock signal CK is at the low level, the NMOS transistor M12 is turned off, but the timing at which the reverse clock signal CKB goes to the high level is earlier by the delay time of the inverter circuit 3 than the timing at which the clock signal CK goes to the low level. . Therefore, the NMOS transistor M14 is turned on immediately before the NMOS transistor M12 is turned off. Since the NMOS transistor M13 is turned on by the output signal of the inverter circuit 12, the input signal B10 of the inverter circuit 12 maintains the low level earlier than the NMOS transistor M12 is turned off. For this reason, even if the NMOS transistor M12 is turned off, the input signal B10 of the inverter circuit 12 remains at a low level. That is, strictly speaking, the inverter circuit 12 and the NMOS transistors M13 and M14 including the resistor R12 form a temporary storage circuit that stores the state of the input signal B10 when the clock signal CK is at a high level before a half cycle. Yes. For this reason, the states of the first output terminal OUT11 and the second output terminal OUT12 do not change.

Further, since the low-level clock signal CK is input to the first input terminal of the NAND circuit 14, the output signal of the NAND circuit 14 remains at the high level, so the NPN transistor Q12 remains off. .
Since the first input terminal IN21 of the fuse blowing circuit 20 is at a low level, the output signal A20 of the NAND circuit 21 is at a high level, so that both the PMOS transistor M21 and the NPN transistor Q21 are off. Further, the input signal B20 of the inverter circuit 22 maintains the low level because the same operation as the operation described in the fuse blowing circuit 10 is performed. Then, the first output terminal OUT21 becomes low level, and the second output terminal OUT22 becomes high level. The fuse blowing circuits 30 and 40 are also in the same operating state as the fuse blowing circuit 20.

During a period P1L, when a predetermined fuse power supply voltage Vp is input to the fuse power supply input terminal Vppi, the NPN transistor Q11 of the fuse blowing circuit 10 is turned on, so the first fuse F11 is blown. Even if the first fuse F11 is blown, the signal level of the input signal B10 of the inverter circuit 12 does not change.
Further, since the NPN transistors Q21, Q31, and Q41 of the fuse blowing circuits 20, 30, and 40 are turned off, the first fuses F21, F31, and F41 are not blown. Further, since the NPN transistors Q12, Q22, and Q32 connected to the fuse output terminals OUT10, OUT20, and OUT30 of the fuse blowing circuits 10, 20, and 30 are also turned off, the trimming fuses TF1, TF2, and TF3 are also blown. There is nothing.

Next, the operation of each unit in the period P2H in which the signal level of the external clock signal CLK is inverted and becomes high level will be described.
Since the first fuse F11 of the fuse blowing circuit 10 is cut, the circuits from the NAND circuit 11 to the NMOS transistor M12 are not related to the operation of the fuse blowing circuit 10. Note that the expression “cut” indicates fusing.
Since the inverse clock signal CKB goes low, the NMOS transistor M14 turns off, the input signal B10 of the inverter circuit 12 goes high, and the output signal of the inverter circuit 12 goes low. As a result, the first output terminal OUT11 becomes high level, and the second output terminal OUT12 becomes low level.

Since the first input terminal IN21 of the fuse blowing circuit 20 is at a high level and the reverse clock signal CKB is at a low level, the output signal A20 of the NAND circuit 21 remains at a high level. For this reason, both the NMOS transistor M21 and the NPN transistor Q21 are off.
Further, since the NMOS transistor M22 is turned on, the input signal B20 of the inverter circuit 22 is at a low level, so the first output terminal OUT21 is at a low level and the second output terminal OUT22 is at a high level.

  Since the second output terminal OUT22 is connected to the third input terminal of the NAND circuit 14 via the second input terminal IN12 of the fuse blowing circuit 10, all three input terminals of the NAND circuit 14 are at a high level. As a result, the output signal of the NAND circuit 14 becomes low level, and both the PMOS transistor M15 and the NPN transistor Q12 are turned on. In the NAND circuit 24 of the fuse blowing circuit 20, since the output signal of the inverter circuit 23 is at a low level as described above, the output signal is at a high level, and both the PMOS transistor M25 and the NPN transistor Q22 are turned off.

  Further, since the reverse clock signal CKB is at low level, the NPN transistors Q31 and Q41 in the fuse blowing circuits 30 and 40 are both turned off, and the second input terminals of the NAND circuits 34 and 44 are both at low level. It has become. For this reason, as in the case of the fuse blowing circuit 20, both the NPN transistors Q32 and Q42 connected to the fuse output terminals OUT30 and OUT40 are also turned off. In this state, when the fuse power supply voltage Vp is input to the fuse power supply input terminal Vppi, the NPN transistor Q12 is turned on, so that a current flows from the third fuse F3 to the trimming fuse TF1 via the diode D3. The fuse TF1 is blown. At this time, since all the NPN transistors connected in series to the other first fuses and the trimming fuse are turned off as described above, they are not blown out.

Next, the operation of each part in the period P2L in which the signal level of the external clock signal CLK is inverted to become a low level will be described.
Since the first fuse F11 of the fuse blowing circuit 10 is cut as described above, the input signal B10 of the inverter circuit 12 is at a high level, the first output terminal OUT11 is at a high level, and the second output terminal OUT12 is at a high level. Low level.
Further, since the first input terminal IN21 of the fuse blowing circuit 20 is at a high level and the reverse clock signal CKB is at a high level, the output signal A20 of the NAND circuit 21 is at a low level. Therefore, the PMOS transistor M21 is turned on, and when the fuse power supply voltage Vp is input, the base current flows through the NPN transistor Q21 and the NPN transistor Q21 can be turned on.

Further, the signal level of the input signal B20 of the inverter circuit 22 is stored as the signal level of the input signal B20 when the clock signal CK before the half cycle is at the high level by the same operation as described for the fuse blowing circuit 10. Therefore, the low level is maintained. For this reason, the first output terminal OUT21 remains at a low level, and the second output terminal OUT22 remains at a high level.
Since the clock signal CK is at a low level, the output signals of the NAND circuits 14, 24, 34 and 44 are at a high level, and the NPN transistors Q12, Q22, Q32 and Q42 are off.

  Further, since the first input terminal IN31 of the fuse blowing circuit 30 is at a low level, the NPN transistor Q31 is turned off. Further, since the first output terminal OUT31 of the fuse blowing circuit 30 is also at a low level, the NPN transistor Q41 of the fuse blowing circuit 40 is similarly turned off. When the fuse power supply voltage Vp is input during this period, only the first fuse F21 of the fuse blowing circuit 20 is blown.

Next, the operation of each part in the period P3H in which the signal level of the external clock signal CLK is inverted and becomes high level will be described.
The first output terminal OUT11 of the fuse blowing circuit 10 is at a high level, and the second output terminal OUT12 remains at a low level. Since the first fuse F21 of the fuse blowing circuit 20 is cut, when the reverse clock signal CKB goes low and the NMOS transistor M24 turns off, the input signal B20 of the inverter circuit 22 goes high. Then, the first output terminal OUT21 of the fuse blowing circuit 20 becomes high level, and the second output terminal OUT22 becomes low level. The operation of the fuse blowing circuit 30 in this state is exactly the same as the operation of the fuse blowing circuit 20 in the period P2H described above.

  Therefore, the first output terminal OUT31 of the fuse blowing circuit 30 is at a low level, the second output terminal OUT32 is at a high level, and the second input terminal IN22 of the fuse blowing circuit 20 is at a high level. Then, since all the input terminals of the NAND circuit 24 are at a high level, the NPN transistor Q22 is turned on. When the fuse power supply voltage Vp is input in this state, the trimming fuse TF2 is blown. However, in the example of FIG. 2, the fuse power supply voltage Vp is not input during this period, so that the trimming fuse TF2 is not cut.

Next, the operation of each part in the period P3L in which the signal level of the external clock signal CLK is inverted to become the low level will be described.
Since the first fuses F11 and F21 are cut, the first output terminals OUT11 and OUT21 of the fuse blowing circuits 20 and 30 are at a high level, and the second output terminals OUT12 and OUT22 are at a low level. Since both the first input terminal IN31 and the reverse clock signal input terminal CKB30 of the fuse blowing circuit 30 are at a high level, the NPN transistor Q31 is turned on when the fuse power supply voltage Vp is input.

  Further, since the clock signal CK is at a low level, the NPN transistor Q32 is turned off. Further, the first output terminal OUT31 is at a low level, and the second output terminal OUT32 is at a high level. Since the first input terminal of the fuse blowing circuit 40 is at a low level, the NPN transistor Q41 is off. Further, since the clock signal CK is at a low level, the NPN transistor Q42 is turned off. When the fuse power supply voltage Vp is input in this state, only the first fuse F31 of the fuse blowing circuit 30 is blown.

Next, the operation of each part in the period P4H in which the signal level of the external clock signal CLK is inverted and becomes high level will be described.
Since the first fuse F31 of the fuse fusing circuit 30 is cut, the first output terminal OUT31 of the fuse fusing circuit 30 is at a high level and the second output terminal OUT32 is at a low level as in the case of the fuse fusing circuit 20 during the period P3H. Respectively. Since the first input terminal IN41 and the reverse clock signal terminal CKB40 of the fuse blowing circuit 40 are each at a low level, the NPN transistor Q41 is off. The first output terminal OUT41 is at a low level, and the second output terminal OUT42 is at a high level.

  Since the second output terminal OUT42 is at the high level, all input terminals of the NAND circuit 34 of the fuse blowing circuit 30 are at the high level, and the NPN transistor Q32 is turned on. When the fuse power supply voltage Vp is input in this state, a current flows from the fuse power supply input terminal Vppi to the trimming fuse TF3 via the third fuse F3 and the diode D4, and the trimming fuse TF3 is blown. At this time, since the second output terminal OUT32 of the fuse blowing circuit 30 is at the low level as described above, the third input terminal of the NAND circuit 24 in the fuse blowing circuit 20 is at the low level, and the NPN transistor Q22. Since is turned off, no current flows through the trimming fuse TF2, and the trimming fuse TF2 is not blown.

Next, the operation of each part in the period P4L in which the signal level of the external clock signal CLK is inverted to become a low level will be described.
As described above, since the first output terminal of the fuse blown circuit in which the first fuse is cut is at the high level and the second output terminal is at the low level, the first input terminal IN41 of the fuse blown circuit 40 is at the high level. It is. Further, since the reverse clock signal CKB is also at a high level, the NPN transistor Q41 in the fuse blowing circuit 40 is turned on when the fuse power supply voltage Vp is input. For this reason, when the fuse power supply voltage Vp is input in this section, the first fuse F41 is blown. Since the first fuse of the lowest fuse blowing circuit is blown, trimming is completed at this stage.

  When the first fuse F41 of the fuse blowing circuit 40 located at the lowest position is cut, the second output terminal OUT42 of the fuse blowing circuit 40 becomes low level in the next cycle of the clock signal CK. Is input to the second input terminal IN32 of the upper fuse blowing circuit 30, and the third input terminal of the NAND circuit 34 is kept at a low level, so that the trimming fuse TF3 connected to the fuse blowing circuit 30 is blown. Even if not, the trimming fuse TF3 cannot be blown.

  In this way, the trimming of the trimming fuses TF1 to TF3 is completed. However, in the present invention, after the fusing / non-blown process for all the trimming fuses is completed, when a predetermined negative voltage is applied to the external clock signal input terminal CKi to blow the second fuse F2, the input of the inverter circuit 2 is performed. The connection between the end and the external clock signal input terminal CKi is cut off. Thereby, it is possible to prevent malfunction when a signal is input to the external clock signal input terminal CKi. Furthermore, the third fuse F3 can be blown by inputting a predetermined negative voltage to the fuse power supply input terminal Vppi. Thus, even if a voltage is erroneously input to the fuse power supply input terminal Vppi, the adjusted feedback voltage Vfb is not affected.

Next, FIG. 3 is a flowchart showing an example of a trimming method for the fuse fusing circuit of FIG.
In FIG. 3, in order to connect the trimming fuse connected to the fuse output terminal of the fuse blowing circuit, the clock signal CK is set to the second level (high level) in step S1. Next, in step S2, the clock signal CK is set to the first level (low level). In step S3, the fuse power supply voltage Vp is input to the fuse power supply input terminal Vppi, and the first fuse is blown. This is the first step.

  Next, in step S4, the clock signal CK is set to the second level (high level), and in step S5, it is determined whether the trimming fuse is to be cut or left as it is. If it is to be cut (YES), the process proceeds to step S6. The fuse power supply voltage Vp is input to the fuse power supply input terminal Vppi, and the trimming fuse is blown. If the trimming fuse is left without being blown in step S5 (NO), the process proceeds to step S7, where the trimming is finished without inputting the fuse power supply voltage Vp to the fuse power supply input terminal Vppi. Step S4 and subsequent steps are the second step.

Next, FIG. 4 is a flowchart showing a trimming method of a trimming circuit formed by cascading a large number of fuse blowing circuits.
In FIG. 4, in step S11, the clock signal CK is set to the second level (high level). Next, in step S12, the clock signal CK is set to the first level (low level). In step S13, the fuse power supply voltage Vp is input to the fuse power supply input terminal Vppi. 1 fuse is blown. This is the first step.

  Next, in step S14, the clock signal CK is set to the second level (high level), and in step S15, it is determined whether to cut or leave the trimming fuse connected to the uppermost fuse blowing circuit. In the case (YES), the process proceeds to step S16, the fuse power supply voltage Vp is input to the fuse power supply input terminal Vppi, and the trimming fuse is blown. When the trimming fuse is left as it is without being blown in step S15 (NO), the process proceeds to step S17, and the fuse power supply voltage Vp is not input to the fuse power supply input terminal Vppi, and the trimming fuse is not cut. Steps S14 to here are the second step.

Next, in step S18, the clock signal CK is set to the first level (low level), and in step S19, the fuse power supply voltage Vp is input to the fuse power supply input terminal Vppi, and the fuse blower circuit connected to the next stage is connected. The first fuse is blown. Next, in step S20, it is confirmed whether or not the fuse blown circuit in which the first fuse is blown in step S19 is the lowest fuse blown circuit. The process from step S18 to here is the third step.
If the confirmation result in step S20 is not the lowest fuse blowing circuit (NO), the process proceeds to step S21, and the clock signal CK is set to the second level (high level).

  Thereafter, in step S22, it is determined whether or not to cut the trimming fuse connected to the fuse blown circuit in which the first fuse has been blown in step S19. If cut (YES), the process proceeds to step S23. The fuse power supply voltage Vp is input to the fuse power supply input terminal Vppi to blow the trimming fuse. If the trimming fuse is not cut in step S22 (NO), the process proceeds to step S24, and the fuse power supply voltage Vp is not input to the fuse power supply input terminal Vppi. The process from step S21 to here is the fourth step. After step S23 or step S24, the process returns to step S18 again.

  In step S20, if the first fuse cut in step S19 is a fuse fusing circuit connected to the lowest position (YES), all trimmings have been completed, so that the process proceeds to step S25, where the external clock The second fuse F2 connected to the signal input terminal CKi is blown. Thereafter, the process proceeds to step S26, and the third fuse F3 connected to the fuse power supply input terminal Vppi is blown. Thus, all the trimming steps are completed.

In this way, starting from the second level (high level) of the clock signal CK, when the clock signal CK is at the first level (low level), the fuse power supply voltage Vp is always input to the fuse power supply input terminal Vppi, and cascade connection is established. The first fuse is blown in order from the top of each fuse blowing circuit. In the second level after the first fuse is blown, it is determined whether the trimming fuse is cut or not cut, and the fuse power supply voltage Vp is input to the fuse power supply input terminal Vppi only when it is cut. Many trimming fuses can be processed in a short time by repeating simple processes.
Further, since the second fuse F2 and the third fuse F3 connected in correspondence with the external clock signal input terminal CKi and the fuse power supply input terminal Vppi are blown after the trimming is completed, the clock is connected to these external terminals. Even if a signal or voltage is input, it is possible to prevent malfunction.

As described above, since the trimming circuit according to the first embodiment can make each fuse blown circuit extremely small, each fuse blown circuit can be arranged in the vicinity of the corresponding trimming fuse. .
Furthermore, these small-scale fuse blow circuits are cascade-connected, and the trimming fuses connected to the lower fuse blow circuit are synchronized with the clock signal CK in order from the trim fuse connected to the uppermost fuse blow circuit. Since the trimming is performed, the circuit scale of the entire trimming circuit can be reduced.

  Also, the first fuse in the fuse blown circuit is blown in the state of the clock signal CK half a cycle before the trimming fuse is blown or not blown, and the result is output to the fuse blower circuit connected to the upper and lower sides. As a result, a signal for specifying the fuse to be trimmed is not required, and only two signal lines are required for the fuse blowing circuit, that is, a clock signal and a fuse power source for fusing, and trimming is performed. The space for wiring can also be reduced.

  In the first embodiment, for the sake of simplicity, the case where there are three trimming fuses has been described as an example. However, the present invention is not limited to this, and the number of trimming fuses is limited. There is no. When the number of trimming fuses increases, it is sufficient to add cascade-connected fuse blow circuits, and as can be seen from the above description, the number of fuse blow circuits is the number of trimming fuses plus one. .

1 Trimming circuit 2, 3 Inverter circuit 10, 20, 30, 40 Fuse fusing circuit F11, F21, F31, F41 First fuse,
F2 Second fuse F3 Third fuse IN11, IN21, IN31, IN41 First input terminal IN12, IN22, IN32, IN42 Second input terminal OUT11, OUT21, OUT31, OUT41 First output terminal OUT12, OUT22, OUT32, OUT42 Second Output terminal TF1, TF2, TF3 Trimming fuse D1-D4 Diode R1-R9 Resistance

Claims (12)

In the trimming circuit for selectively blowing the trimming fuse, the fuse fusing circuit for inputting and blowing the fuse power supply voltage to the trimming fuse connected to the fuse output terminal,
The fuse blowing circuit is
A first fuse;
A clock input terminal to which a predetermined clock signal is input;
When the fuse power supply voltage is input when the signal level of the clock signal is the first level, the first signal input to the first input terminal for selecting whether or not to blow the first fuse is selected. A first fuse blowing circuit unit for blowing the first fuse in response to one signal;
Whether or not the trimming fuse input to the second input terminal is blown when the fuse power supply voltage is input when the signal level of the clock signal is a second level obtained by inverting the first level A trimming fuse fusing circuit unit for fusing the trimming fuse in response to a second signal for selecting
A storage circuit unit that temporarily holds and outputs the state of the first fuse when the clock signal is at the second level while the clock signal is at the next first level;
With
The memory circuit unit outputs the held signal indicating the state of the first fuse as the first signal from the first output terminal to the first input terminal and as the second signal from the second output terminal. A trimming circuit that outputs to two input terminals. A plurality of the fuse blowing circuits cascaded from the upper to the lower,
Each of the fuse blowing circuits has the first output terminal connected to the first input terminal of the fuse blowing circuit connected to a lower level, and the fuse blowing of the second output terminal connected to a higher level. Connected to the second input terminal of the circuit;
The fuse blowing circuit connected to the top is input to the first input terminal, the first signal indicating that the first fuse is blown,
2. The trimming circuit according to claim 1, wherein the trimming fuse is not connected to the fuse output terminal of the fuse fusing circuit connected to the lowest level.   3. The trimming circuit according to claim 1, further comprising a first blocking means for blocking an external clock signal input from the outside that forms the clock signal.   4. The trimming circuit according to claim 3, wherein the first interrupting unit includes a second fuse that blows when a fusing current of a first predetermined value or more flows.   5. The trimming circuit according to claim 1, further comprising a second blocking means for blocking the input of the fuse power supply voltage.   6. The trimming circuit according to claim 5, wherein the second interrupting means comprises a third fuse that blows when a fusing current of a second predetermined value or more flows.   The trimming circuit according to claim 6, wherein the third fuse has a fusing current larger than that of the trimming fuse.   A semiconductor device comprising the trimming circuit according to claim 1. In the trimming method in the trimming circuit according to claim 1,
The fuse power supply voltage is inputted while the clock signal goes through the second level state to the next first level state, and the first fuse in the fuse blowing circuit is blown out. Process,
A second step of inputting the fuse power supply voltage only when the trimming fuse is blown while the clock signal is in the next second level state;
Trimming method characterized by performing. The trimming method in the trimming circuit according to claim 2,
The fuse power supply voltage is inputted while the clock signal is in the next first level state through the second level state, and the fuse signal in the fuse blowing circuit connected to the highest level is input. A first step of fusing the first fuse;
A second step of inputting the fuse power supply voltage only when the trimming fuse connected to the uppermost fuse blow circuit is blown while the clock signal is in the next second level state;
Next, when the clock signal is inverted to the first level, a third step of blowing the first fuse in the fuse fusing circuit connected immediately below,
The fuse power supply voltage is inputted only when the trimming fuse connected to the fuse blowing circuit connected immediately below is blown while the clock signal is in the next second level state. 4 steps,
And
Similarly, the third step of blowing the first fuse in the lower fuse blowing circuit and the fourth step of blowing the trimming fuse connected to each fuse blowing circuit in order. A trimming method comprising: repeatedly performing the trimming operation when the third step of cutting the first fuse in the fuse blowing circuit connected to the lowest is completed.   11. The trimming method according to claim 9, wherein when a trimming operation is completed, an external clock signal input from the outside that forms the clock signal is blocked.   12. The trimming method according to claim 9, wherein the input of the fuse power supply voltage is cut off when the trimming operation is completed.

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