CN115857605B - Fuse trimming circuit - Google Patents
Fuse trimming circuit Download PDFInfo
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- CN115857605B CN115857605B CN202310196294.9A CN202310196294A CN115857605B CN 115857605 B CN115857605 B CN 115857605B CN 202310196294 A CN202310196294 A CN 202310196294A CN 115857605 B CN115857605 B CN 115857605B
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Abstract
The invention relates to the technical field of integrated circuit trimming, and particularly discloses a fuse trimming circuit, which comprises the following components: the fuse trimming control unit is used for generating a first trimming starting signal in a trimming period according to the first fuse programming control signal and generating a first trimming turning-off signal in a non-trimming period; the trimming bit control unit is used for generating a second trimming starting signal in a trimming period according to a second fuse programming control signal, generating a second trimming turning-off signal in a non-trimming period, and trimming according to the first trimming starting signal and the second trimming starting signal in the trimming period; the error trimming protection unit is used for generating a data reading off signal in a trimming period according to the error trimming control signal and generating a data reading on signal in a non-trimming period, wherein the data reading on signal is smaller than the first trimming on signal. The fuse trimming circuit provided by the invention can prevent wrong trimming.
Description
Technical Field
The invention relates to the technical field of integrated circuit trimming, in particular to a fuse trimming circuit.
Background
In integrated circuit design and production and application processes, parameters such as reference voltage, reference current, oscillation frequency, etc. are usually calibrated by fuse trimming to obtain high-precision design expectations. However, in actual practice, there are many factors that cause the fuse that is not trimmed to be trimmed by mistake, so that the error between the actual parameter and the design expectation becomes large, which may affect the circuit key parameter to exceed the customer acceptance criteria, and the circuit key parameter is judged as a defective product.
Therefore, how to reduce the mis-trimming of fuses is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
The invention provides a fuse trimming circuit which solves the problem of fuse wrong trimming in the related technology.
As one aspect of the present invention, there is provided a fuse trimming circuit, comprising: the fuse trimming control unit is connected with the error trimming protection unit, the error trimming protection unit and the fuse trimming control unit are connected with the trimming control unit,
the fuse trimming control unit is used for generating a first trimming starting signal in a trimming period according to a first fuse programming control signal and generating a first trimming turning-off signal in a non-trimming period;
the trimming bit control unit is used for generating a second trimming starting signal in a trimming period according to a second fuse programming control signal, generating a second trimming turning-off signal in a non-trimming period, and trimming parameters to be trimmed according to the first trimming starting signal and the second trimming starting signal in the trimming period;
the error trimming protection unit is used for generating a data reading off signal in a trimming period according to the error trimming protection signal and generating a data reading on signal in a non-trimming period, wherein the data reading on signal is smaller than the first trimming on signal;
the first fuse programming control signal and the second fuse programming control signal are programming control signals output by an external trimming control circuit.
Further, the fuse trimming control unit comprises a first MOS tube and a first resistor, wherein the driving end of the first MOS tube is connected with the first fuse programming control signal, the first end of the first MOS tube is connected with a power supply, the second end of the first MOS tube is connected with the trimming control unit, one end of the first resistor is connected with the power supply, the other end of the first resistor is connected with the driving end of the first MOS tube,
when the trimming period is in, the first MOS tube can be conducted when the driving end of the first MOS tube receives the first fuse programming control signal, so that fuse programming current generated by the power supply flowing through the first MOS tube flows into the trimming bit control unit;
when the first MOS tube is in the non-trimming period, the first MOS tube can be turned off when the driving end of the first MOS tube receives the first fuse programming control signal.
Further, the trimming control unit comprises N trimming units, each trimming unit is connected with the fuse trimming control unit, each trimming unit comprises a trimming resistor and a control module, one end of the trimming resistor is connected with the second end of the first MOS tube, the other end of the trimming resistor is connected with the control module,
the control module can be conducted according to the second fuse programming control signal when the trimming period is in the trimming period so as to allow the fuse programming current to flow into the trimming resistor;
the trimming resistor can be fused when the fuse programming current flows in so as to realize trimming of parameters to be trimmed;
and N is a natural number which is more than or equal to 1, and the fuse programming current is more than the current required by fusing of the trimming resistor.
Further, the control module comprises a second MOS tube and a second resistor, the driving end of the second MOS tube is used for inputting a second fuse programming control signal, the first end of the second MOS tube is connected with the other end of the trimming resistor, the second end of the second MOS tube is connected with the signal ground, one end of the second resistor is connected with the driving end of the second MOS tube, the other end of the second resistor is connected with the signal ground,
when the trimming period is in, the second MOS tube can be conducted when the driving end of the second MOS tube receives the second fuse programming control signal, so that the fuse programming current flows into the trimming resistor;
when the second MOS tube is in the non-trimming period, the second MOS tube can be turned off when the driving end of the second MOS tube receives the second fuse programming control signal.
Further, each trimming bit unit further comprises a data reading module and a data latching module, wherein the data reading module is connected with the other end of the trimming resistor, the data latching module is connected with the data reading module, the data reading module is used for reading the data trimmed by the fuse according to the data reading control signal, and the data latching module is used for storing the data trimmed by the fuse.
Further, the data reading module includes: the driving end of the fourth MOS tube is used for inputting a first data reading control signal, the first end of the fourth MOS tube is connected with the other end of the trimming resistor, the second end of the fourth MOS tube is connected with one end of the first constant current source, the driving end of the fifth MOS tube is used for inputting a second data reading control signal, the first end of the fifth MOS tube is connected with the other end of the first constant current source, and the second end of the fifth MOS tube is connected with signal ground.
Further, the data latch module includes: a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube and an eleventh MOS tube,
the driving end of the sixth MOS tube is connected with the driving end of the ninth MOS tube, the first end of the sixth MOS tube is connected with a power supply, the second end of the sixth MOS tube is connected with the first end of the seventh MOS tube,
the driving end of the seventh MOS tube is used for inputting a first data latch control signal, the second end of the seventh MOS tube is connected with one end of the first constant current source,
the driving end of the eighth MOS tube is used for inputting a second data latch control signal, the first end of the eighth MOS tube is connected with one end of the first constant current source, the second end of the eighth MOS tube is connected with the first end of the ninth MOS tube, the second end of the ninth MOS tube is connected with the signal ground,
the driving end of the tenth MOS tube and the driving end of the eleventh MOS tube are both connected with one end of the first constant current source, the first end of the tenth MOS tube is connected with a power supply, the second end of the tenth MOS tube is connected with the driving end of the sixth MOS tube,
the first end of the eleventh MOS tube is connected with the driving end of the sixth MOS tube, the second end of the eleventh MOS tube is connected with the signal ground,
the second end of the tenth MOS tube and the first end of the eleventh MOS tube are both data latch signal ends.
Further, the first MOS tube, the fourth MOS tube, the sixth MOS tube, the seventh MOS tube and the tenth MOS tube are P-type MOS tubes, the fifth MOS tube, the eighth MOS tube, the ninth MOS tube and the eleventh MOS tube are N-type MOS tubes, the driving ends of the first MOS tube, the fourth MOS tube, the sixth MOS tube, the seventh MOS tube and the tenth MOS tube are gates, the first ends of the first MOS tube, the fourth MOS tube, the sixth MOS tube, the seventh MOS tube and the tenth MOS tube are sources, the second ends of the first MOS tube, the fourth MOS tube, the sixth MOS tube, the seventh MOS tube and the tenth MOS tube are drains, the driving ends of the fifth MOS tube, the eighth MOS tube, the ninth MOS tube and the eleventh MOS tube are gates, the first ends of the fifth MOS tube, the eighth MOS tube, the ninth MOS tube and the eleventh MOS tube are drains, and the second ends of the fifth MOS tube, the eighth MOS tube and the eleventh tube are sources.
Further, the error correction protection unit comprises a third resistor and a third MOS tube, wherein the driving end of the third MOS tube is used for inputting an error correction control signal, the first end of the third MOS tube is connected with a power supply, the second end of the third MOS tube is connected with the correction control unit, one end of the third resistor is connected with the power supply, the other end of the third resistor is connected with the driving end of the third MOS tube,
when the third MOS tube is in the trimming period, the third MOS tube can be turned off when the driving end of the third MOS tube receives the error trimming control signal;
when the third MOS tube is in the non-trimming period, the third MOS tube can be conducted when the driving end of the third MOS tube receives the error trimming control signal to form a conducting current, and the conducting current is smaller than the current required by the trimming resistor to fuse.
Further, the third MOS tube is a P-type MOS tube, the driving end of the third MOS tube is a grid, the first end of the third MOS tube is a source electrode, and the second end of the third MOS tube is a drain electrode.
According to the fuse trimming circuit provided by the invention, trimming of the parameter to be trimmed is realized through the fuse trimming control unit and the trimming position control unit, and the error trimming protection unit can be kept off in the trimming period and is started in the non-trimming period, and the data reading starting signal of the error trimming protection unit is smaller than the trimming starting signal of the fuse trimming control unit, so that the trimming data is allowed to be read, and meanwhile, the trimming position control unit is not caused to be started by mistake, namely, the error trimming phenomenon is effectively prevented, and therefore, the fuse is greatly protected from being trimmed by mistake during data reading.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate the invention and together with the description serve to explain, without limitation, the invention.
Fig. 1 is a block diagram of a fuse trimming circuit according to the present invention.
Fig. 2 is a schematic circuit diagram of a fuse trimming circuit according to the present invention.
Detailed Description
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other. The invention will be described in detail below with reference to the drawings in connection with embodiments.
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In this embodiment, a fuse trimming circuit is provided, and fig. 1 is a block diagram of a fuse trimming circuit according to an embodiment of the present invention, as shown in fig. 1, including: the fuse trimming control unit 100, the error trimming protection unit 200 and the trimming control unit 300 are connected with the fuse trimming control unit 100 and the error trimming protection unit 200, the error trimming protection unit 200 and the fuse trimming control unit 100 are connected with the trimming control unit 300,
the fuse trimming control unit 100 is configured to generate a first trimming on signal during a trimming period according to a first fuse programming control signal, and generate a first trimming off signal during a non-trimming period;
the trimming bit control unit 300 is configured to generate a second trimming on signal in a trimming period according to a second fuse programming control signal, generate a second trimming off signal in a non-trimming period, and perform trimming on a parameter to be trimmed according to the first trimming on signal and the second trimming on signal in the trimming period;
the error trimming protection unit 200 is configured to generate a data reading off signal in a trimming period according to an error trimming control signal, and generate a data reading on signal in a non-trimming period, where the data reading on signal is smaller than the first trimming on signal;
the first fuse programming control signal and the second fuse programming control signal are programming control signals output by an external trimming control circuit.
According to the fuse trimming circuit provided by the embodiment of the invention, trimming of the parameter to be trimmed is realized through the fuse trimming control unit and the trimming bit control unit, and the error trimming protection unit can be kept off in the trimming period and is started in the non-trimming period, and the data reading starting signal of the error trimming protection unit is smaller than the trimming starting signal of the fuse trimming control unit, so that the trimming data is allowed to be read, and meanwhile, the trimming bit control unit is not started by mistake, namely, the error trimming phenomenon is effectively prevented, and therefore, the fuse is greatly protected from being trimmed by mistake in the data reading process.
It should be understood that the first fuse programming control signal is a first fuse programming control signal V1 output by the external trimming control circuit, and the second fuse programming control signal is a second fuse programming control signal V2 output by the external trimming control circuit.
Specifically, as shown in fig. 2, the fuse trimming control unit 100 includes a first MOS transistor Q1 and a first resistor R1, wherein the driving end of the first MOS transistor Q1 is connected to the first fuse programming control signal V1, the first end of the first MOS transistor Q1 is connected to a power supply VDD, the second end of the first MOS transistor Q1 is connected to the trimming control unit 300, one end of the first resistor R1 is connected to the power supply VDD, the other end of the first resistor R1 is connected to the driving end of the first MOS transistor Q1,
when the trimming period is in the trimming period, the first MOS transistor Q1 may be turned on when the driving end thereof receives the first fuse programming control signal, so as to flow the fuse programming current generated by the power supply flowing through the first MOS transistor Q1 into the trimming bit control unit 300;
when the first MOS transistor Q1 is in the non-trimming period, the first fuse programming control signal V1 can be received by the driving end of the first MOS transistor Q1.
In the embodiment of the present invention, the first MOS transistor Q1 may be a P-type MOS transistor, and in this embodiment, the driving end of the first MOS transistor Q1 is a gate of the P-type MOS transistor, the first end of the first MOS transistor Q1 is a source of the P-type MOS transistor, and the second end of the first MOS transistor Q1 is a drain of the P-type MOS transistor.
As shown in fig. 1, the trimming control unit 300 includes N trimming units 310, each trimming unit 310 is connected to the fuse trimming control unit 100, each trimming unit 310 includes a trimming resistor and a control module 311, one end of the trimming resistor is connected to the second end of the first MOS transistor Q1, the other end of the trimming resistor is connected to the control module 311,
the control module 311 is capable of being turned on according to the second fuse programming control signal V2 when the trimming period is in order to allow the fuse programming current to flow into the trimming resistor;
the trimming resistor can be fused when the fuse programming current flows in so as to realize trimming of parameters to be trimmed;
and N is a natural number which is more than or equal to 1, and the fuse programming current is more than the current required by fusing of the trimming resistor.
It should be understood that the trimming control unit 300 includes N trimming units, each including a trimming resistor, where when trimming, the N trimming units may be sequentially trimmed, or may be trimmed in groups, and the specific trimming sequence may be selected according to needs, which is not limited herein.
In fig. 2 of the embodiment of the present invention, only one trimming unit 310 is schematically shown, that is, taking the example shown in fig. 2 as an example, the trimming unit 310 includes a trimming resistor R10 and a control module 311.
As shown in fig. 2, the control module 311 includes a second MOS transistor Q2 and a second resistor R2, where the driving end of the second MOS transistor Q2 is used to input a second fuse programming control signal V2, a first end of the second MOS transistor Q2 is connected to the other end of the trimming resistor R10, a second end of the second MOS transistor Q2 is connected to the signal ground, one end of the second resistor R2 is connected to the driving end of the second MOS transistor Q2, and the other end of the second resistor R2 is connected to the signal ground,
when the trimming period is in, the second MOS transistor Q2 can be turned on when the driving end thereof receives the second fuse programming control signal, so that the fuse programming current flows into the trimming resistor R10;
when the second MOS transistor Q2 is in the non-trimming period, the second fuse programming control signal V2 can be received by the driving end of the second MOS transistor Q2.
In the embodiment of the present invention, the error correction protection unit 200 includes a third resistor R3 and a third MOS transistor Q3, where the driving end of the third MOS transistor Q3 is used for inputting an error correction control signal V3, a first end of the third MOS transistor Q3 is connected to a power supply VDD, a second end of the third MOS transistor Q3 is connected to the correction control unit 300, one end of the third resistor R3 is connected to the power supply VDD, and the other end of the third resistor R3 is connected to the driving end of the third MOS transistor Q3,
when the third MOS transistor Q3 is in the trimming period, the third MOS transistor Q3 can be turned off when the driving end receives the error trimming control signal V3;
when the third MOS transistor Q3 is in the non-trimming period, the third MOS transistor Q3 can be conducted to form a conducting current when the driving end of the third MOS transistor Q3 receives the error trimming control signal V3, and the conducting current is smaller than the current required by the trimming resistor to fuse.
It should be noted that, the third MOS transistor Q3 is a P-type MOS transistor, the driving end of the third MOS transistor Q3 is a gate, the first end of the third MOS transistor Q3 is a source, and the second end of the third MOS transistor Q3 is a drain.
It should be appreciated that during integrated circuit design and production and application, parameters such as reference voltage, reference current, oscillation frequency, etc. are typically calibrated by fuse trimming. The fuse trimming circuit shown in fig. 2 is exemplified by a trimming control unit including 1 trimming unit, that is, a trimming control unit including 1 trimming resistor R10 and a control module.
The fuse trimming control unit 100 includes a first resistor R1 and a first MOS transistor Q1. The first MOS transistor Q1 is a P-channel transistor, the source thereof is coupled to the power supply VDD, the gate thereof is controlled by the first fuse programming control signal V1, and the first MOS transistor Q1 is connected to the pull-up first resistor R1. The trimming bit control unit 300 includes a trimming resistor R10, a second resistor R2, and a second MOS transistor Q2. One end of the trimming resistor R10 is coupled with the drain electrode of the first MOS tube Q1; the second MOS transistor Q2 is an N-channel transistor, the source electrode thereof is coupled to the ground, the grid electrode thereof is controlled by a second fuse programming control signal V2, and the second resistor R2 is pulled down, and the drain electrode thereof is coupled to the other end of the trimming resistor R10.
When the first fuse programming control signal V1 controls the first MOS Q1 and the second fuse programming control signal V2 controls the second MOS Q2 to be turned on simultaneously, the power supply VDD flows a larger current through the first MOS Q1, the trimming resistor R10 and the second MOS Q2, so that the trimming resistor R10 is blown. The larger current flowing through trimming resistor R10 is referred to as fuse programming current. For example, the fuse programming current is 100 mA-150 mA. That is, the trimming resistor R10 is required to be blown by flowing a fuse programming current (100 mA to 150 mA) through the trimming resistor R10.
It should be understood that, since the fuse trimming control unit 100 needs to turn on the first MOS transistor Q1 when reading data. In particular, the data is sometimes read during the power-on process, so long as the second MOS Q2 in the control module 311 is interfered, the fuse is easily repaired. In order to solve the problem of the erroneous adjustment, the erroneous adjustment protection unit 200 is provided, and the third resistor R3 and the third MOS transistor Q3 are included in the erroneous adjustment protection unit 200. The third MOS transistor Q3 is a P-channel transistor, the source electrode of the third MOS transistor Q3 is coupled with the power supply VDD, the grid electrode of the third MOS transistor Q3 is controlled by the error correction control signal V3 and is connected with the third resistor R3 which is pulled up, and the drain electrode of the third MOS transistor Q3 is coupled with the drain electrode of the first MOS transistor Q1. In the non-fuse trimming period, the first MOS transistor Q1 and the second MOS transistor Q2 are both turned off, and the third MOS transistor Q3 is controlled to be turned on by the error trimming control signal V3.
In the embodiment of the invention, the output current of the third MOS transistor Q3 is far smaller than the current (100 mA-150 mA) required by blowing of the fuse trimming resistor, and is generally controlled to be between a few mA and ten mA. The mis-trimming control signal V3 of the mis-trimming protection unit 200 can control the third MOS transistor Q3 to be turned on only when the data is read. Thus, the first MOS Q1 in the fuse trimming control unit 100 and the second MOS Q2 in the control module 311 are simultaneously interfered, and the probability of being in the on state is greatly reduced. Even if the second MOS transistor Q2 in the control module 311 is interfered, the second MOS transistor Q2 is in a conductive state, and since the output current of the third MOS transistor Q3 is far less than the required current (100 mA-150 mA) for blowing the trimming resistor, the trimming resistor R10 in the trimming bit control unit 300 is not blown, so that the fuse is greatly protected from being trimmed by mistake in the data reading period.
In this embodiment of the present invention, each trimming bit unit 310 further includes a data reading module 312 and a data latch module 313, where the data reading module 312 is connected to the other end of the trimming resistor R10, the data latch module 313 is connected to the data reading module 312, and the data reading module 312 is configured to read the data trimmed by the fuse according to the data reading control signal, and the data latch module is configured to store the data trimmed by the fuse.
Still referring to fig. 2, the data reading module 312 includes: the driving end of the fourth MOS tube Q4 is used for inputting a first data reading control signal V4, the first end of the fourth MOS tube Q4 is connected with the other end of the trimming resistor R10, the second end of the fourth MOS tube Q4 is connected with one end of the first constant current source I1, the driving end of the fifth MOS tube Q5 is used for inputting a second data reading control signal V5, the first end of the fifth MOS tube Q5 is connected with the other end of the first constant current source I1, and the second end of the fifth MOS tube Q5 is connected with signal ground.
Specifically, the data latch module 313 includes: a sixth MOS transistor Q6, a seventh MOS transistor Q7, an eighth MOS transistor Q8, a ninth MOS transistor Q9, a tenth MOS transistor Q10 and an eleventh MOS transistor Q11,
the driving end of the sixth MOS tube Q6 is connected with the driving end of the ninth MOS tube Q9, the first end of the sixth MOS tube Q6 is connected with a power supply, the second end of the sixth MOS tube Q6 is connected with the first end of the seventh MOS tube Q7,
the driving end of the seventh MOS transistor Q7 is used for inputting a first data latch control signal V6, the second end of the seventh MOS transistor Q7 is connected with one end of the first constant current source I1,
the driving end of the eighth MOS transistor Q8 is used for inputting a second data latch control signal V7, the first end of the eighth MOS transistor Q8 is connected with one end of the first constant current source I1, the second end of the eighth MOS transistor Q8 is connected with the first end of the ninth MOS transistor Q9, the second end of the ninth MOS transistor Q9 is connected with the signal ground,
the driving end of the tenth MOS transistor Q10 and the driving end of the eleventh MOS transistor Q11 are both connected with one end of the first constant current source I1, the first end of the tenth MOS transistor Q10 is connected with the power supply VDD, the second end of the tenth MOS transistor Q10 is connected with the driving end of the sixth MOS transistor Q6,
a first end of the eleventh MOS transistor Q11 is connected with the driving end of the sixth MOS transistor Q6, a second end of the eleventh MOS transistor Q11 is connected with signal ground,
the second end of the tenth MOS transistor Q10 and the first end of the eleventh MOS transistor Q11 are both data latch signal ends V8.
In the embodiment of the invention, the first MOS transistor Q1, the fourth MOS transistor Q4, the sixth MOS transistor Q6, the seventh MOS transistor Q7 and the tenth MOS transistor Q10 are P-type MOS transistors, the fifth MOS transistor Q5, the eighth MOS transistor Q8, the seventh MOS transistor Q9 and the tenth MOS transistor Q11 are N-type MOS transistors, the driving ends of the first MOS transistor Q1, the fourth MOS transistor Q4, the sixth MOS transistor Q6, the seventh MOS transistor Q7 and the tenth MOS transistor Q10 are gates, the first ends of the first MOS transistor Q1, the fourth MOS transistor Q4, the sixth MOS transistor Q6, the seventh MOS transistor Q7 and the tenth MOS transistor Q10 are sources, the second ends of the first MOS transistor Q1, the fourth MOS transistor Q4, the sixth MOS transistor Q6, the seventh MOS transistor Q7 and the tenth MOS transistor Q10 are drains, the fifth MOS transistor Q5, the eighth MOS transistor Q8, the eighth MOS transistor Q9 and the eleventh transistor Q11 are drains, the first ends of the fifth MOS transistor Q5, the eighth MOS transistor Q8 and the eleventh transistor Q11 are gates, the first ends of the eighth MOS transistor Q11 and the eighth MOS transistor Q11 are drain.
In the embodiment of the present invention, the data reading module 312 is composed of a fourth MOS transistor Q4, a fifth MOS transistor Q5, and a first constant current source I1. The fourth MOS transistor Q4 is a P-channel transistor, the source electrode of the fourth MOS transistor Q4 is coupled with the drain electrode of the second MOS transistor Q2, the grid electrode is controlled by the first data reading control signal V4, and the drain electrode is coupled with one end of the first constant current source I1 and outputs a data signal; the fifth MOS transistor Q5 is an N-channel transistor, the source electrode of the fifth MOS transistor Q is grounded, the grid electrode of the fifth MOS transistor Q is controlled by the second data reading control signal V5, and the drain electrode of the fifth MOS transistor Q is coupled with the other end of the first constant current source I1. In the non-fuse trimming period, the first fuse programming control signal V1 controls the first MOS Q1 to be turned on and the second fuse programming control signal V2 controls the second MOS Q2 to be turned off, and the data reading module 312 reads the fuse trimmed data. Specifically, the first data reading control signal V4 controls the fourth MOS transistor Q4 to be turned on, and the second data reading control signal V5 controls the fifth MOS transistor Q5 to be turned on. Because the output current capacity of the first MOS transistor Q1 is larger than the fuse programming current (100 mA-150) when being conducted, the resistance value of the trimming resistor R10 is hundreds of ohms, and the first constant current source I1 is designed to be tens of microamps. If the trimming resistor R10 is not blown, the drain potential of the fourth MOS transistor Q4 is the power supply VDD; when the trimming resistor R10 is blown, the drain potential of the fourth MOS transistor Q4 is approximately equal to the signal ground. The first data read control signal V4 and the second data read control signal V5 are read data control signals. It is apparent that the data is read when the first data read control signal V4 is at a low level and the second data read control signal V5 is at a high level.
The data latch module 313 is composed of sixth to eleventh MOS transistors Q6 to Q11. The tenth MOS transistor Q10 and the eleventh MOS transistor Q11 form a first inverter, the input of which receives a data signal and outputs a latched data signal V8, the sixth MOS transistor Q6 and the ninth MOS transistor Q9 form a second inverter controlled by the seventh MOS transistor Q7 and the eighth MOS transistor Q8, the input of which receives an output signal of the first inverter and the output of which is coupled with the input end of the first inverter. The seventh MOS transistor Q7 and the eighth MOS transistor Q8 are a P-channel transistor and an N-channel transistor, respectively, and gates thereof are controlled by the first data latch control signal V6 and the second data latch control signal V7, respectively. The data output from the data reading module 312 is inverted by the first inverter in the data latch module 313 and input to the second inverter, and at this time, the data signal V8 output from the data reading module 312 is latched when the first data latch control signal V6 is at a low level and the second data latch control signal V7 is at a high level.
In the embodiment of the present invention, taking fig. 2 as an example, for example, the first MOS transistor Q1 has a width-to-length ratio (8.19 μm/0.5 μm) of 237 parallel connection; the width-to-length ratio of the second MOS tube Q2 is (8.19 μm/0.5 μm), and 3 MOS tubes are connected in parallel; the width-to-length ratio of the third MOS transistor Q3 is (60 μm/0.5 μm), the resistance of the first resistor R1, the resistance of the second resistor R2 and the resistance of the third resistor R3 are all 1MΩ, the trimming resistor R10 adopts low-resistance polycrystal, 5 square blocks are provided, about 40 Ω, and according to experience, the required current for burning the trimming resistor R10 is about 125mA. The first constant current source I1 is set to 1 mu A, and the output current of the third MOS transistor Q3 is 10 mu A.
Fig. 1 is a schematic diagram of a fuse bit control unit according to an embodiment of the present invention, including N fuse bit units. It includes a fuse trimming control unit 100, a mis-trimming protection unit 200, a first bit trimming unit 310, a second bit trimming unit 320, and so on, to an nth bit trimming unit. Each trimming bit unit comprises a trimming resistor, a control module, a data reading module and a data latching module. Specific circuit schematic diagrams of the control module, the data reading module and the data latch module can be shown with reference to fig. 2.
The N-bit fuse trimming can work in serial one-bit sequential fuse trimming, or grouping sequential fuse trimming, even when the number of bits is not much, the multi-bit fuse trimming is performed at one time.
For example, the width-to-length ratio of the first MOS transistor Q1 is (8.19 μm/0.5 μm), and 237 MOS transistors are connected in parallel; the width-to-length ratio of the second MOS tube Q2 is (8.19 μm/0.5 μm), and 3 MOS tubes are connected in parallel; the width-to-length ratio of the third MOS transistor Q3 is (60 μm/0.5 μm), the resistance of the first resistor R1, the resistance of the second resistor R2 and the resistance of the third resistor R3 are all 1MΩ, the trimming resistors R10, R20 … … RN0 are all low-resistance polycrystal, 5 square blocks are arranged, about 40 Ω, and according to experience, the required current of each of the fuse trimming resistors R10, R20 … … RN0 is about 125mA. The first constant current source I1 is set to 1 μa, and the output current (10×n) μa of the third MOS transistor Q3. For example, N is taken as 32, resulting in 320. Mu.A.
In summary, the fuse trimming circuit provided by the invention greatly protects the fuse from being trimmed by mistake in the data reading period.
It is to be understood that the above embodiments are merely illustrative of the application of the principles of the present invention, but not in limitation thereof. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the invention, and are also considered to be within the scope of the invention.
Claims (6)
1. A fuse trimming circuit, comprising: the fuse trimming control unit is connected with the error trimming protection unit, the error trimming protection unit and the fuse trimming control unit are connected with the trimming control unit,
the fuse trimming control unit is used for generating a first trimming starting signal in a trimming period according to a first fuse programming control signal and generating a first trimming turning-off signal in a non-trimming period;
the trimming bit control unit is used for generating a second trimming starting signal in a trimming period according to a second fuse programming control signal, generating a second trimming turning-off signal in a non-trimming period, and trimming parameters to be trimmed according to the first trimming starting signal and the second trimming starting signal in the trimming period;
the error trimming protection unit is used for generating a data reading off signal in a trimming period according to the error trimming protection signal and generating a data reading on signal in a non-trimming period, wherein the data reading on signal is smaller than the first trimming on signal;
the first fuse programming control signal and the second fuse programming control signal are programming control signals output by an external trimming control circuit;
the fuse trimming control unit comprises a first MOS tube and a first resistor, wherein the driving end of the first MOS tube is connected with the first fuse programming control signal, the first end of the first MOS tube is connected with a power supply, the second end of the first MOS tube is connected with the trimming control unit, one end of the first resistor is connected with the power supply, the other end of the first resistor is connected with the driving end of the first MOS tube,
when the trimming period is in, the first MOS tube can be conducted when the driving end of the first MOS tube receives the first fuse programming control signal, so that fuse programming current generated by the power supply flowing through the first MOS tube flows into the trimming bit control unit;
when the first MOS tube is in the non-trimming period, the first MOS tube can be turned off when the driving end of the first MOS tube receives the first fuse programming control signal;
the trimming control unit comprises N trimming units, each trimming unit is connected with the fuse trimming control unit, each trimming unit comprises a trimming resistor and a control module, one end of the trimming resistor is connected with the second end of the first MOS tube, the other end of the trimming resistor is connected with the control module,
the control module can be conducted according to the second fuse programming control signal when the trimming period is in the trimming period so as to allow the fuse programming current to flow into the trimming resistor;
the trimming resistor can be fused when the fuse programming current flows in so as to realize trimming of parameters to be trimmed;
wherein N is a natural number greater than or equal to 1, and the fuse programming current is greater than the current required by fusing of the trimming resistor;
each trimming bit unit further comprises a data reading module and a data latching module, wherein the data reading module is connected with the other end of the trimming resistor, the data latching module is connected with the data reading module, the data reading module is used for reading the data after trimming the fuse according to a data reading control signal, and the data latching module is used for storing the data after trimming the fuse;
the data reading module includes: the driving end of the fourth MOS tube is used for inputting a first data reading control signal, the first end of the fourth MOS tube is connected with the other end of the trimming resistor, the second end of the fourth MOS tube is connected with one end of the first constant current source, the driving end of the fifth MOS tube is used for inputting a second data reading control signal, the first end of the fifth MOS tube is connected with the other end of the first constant current source, and the second end of the fifth MOS tube is connected with signal ground.
2. The fuse trimming circuit of claim 1, wherein the control module comprises a second MOS tube and a second resistor, wherein the driving end of the second MOS tube is used for inputting a second fuse programming control signal, the first end of the second MOS tube is connected with the other end of the trimming resistor, the second end of the second MOS tube is connected with the signal ground, one end of the second resistor is connected with the driving end of the second MOS tube, the other end of the second resistor is connected with the signal ground,
when the trimming period is in, the second MOS tube can be conducted when the driving end of the second MOS tube receives the second fuse programming control signal, so that the fuse programming current flows into the trimming resistor;
when the second MOS tube is in the non-trimming period, the second MOS tube can be turned off when the driving end of the second MOS tube receives the second fuse programming control signal.
3. The fuse trimming circuit of claim 1, wherein the data latch module comprises: a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube and an eleventh MOS tube,
the driving end of the sixth MOS tube is connected with the driving end of the ninth MOS tube, the first end of the sixth MOS tube is connected with a power supply, the second end of the sixth MOS tube is connected with the first end of the seventh MOS tube,
the driving end of the seventh MOS tube is used for inputting a first data latch control signal, the second end of the seventh MOS tube is connected with one end of the first constant current source,
the driving end of the eighth MOS tube is used for inputting a second data latch control signal, the first end of the eighth MOS tube is connected with one end of the first constant current source, the second end of the eighth MOS tube is connected with the first end of the ninth MOS tube, the second end of the ninth MOS tube is connected with the signal ground,
the driving end of the tenth MOS tube and the driving end of the eleventh MOS tube are both connected with one end of the first constant current source, the first end of the tenth MOS tube is connected with a power supply, the second end of the tenth MOS tube is connected with the driving end of the sixth MOS tube,
the first end of the eleventh MOS tube is connected with the driving end of the sixth MOS tube, the second end of the eleventh MOS tube is connected with the signal ground,
the second end of the tenth MOS tube and the first end of the eleventh MOS tube are both data latch signal ends.
4. The fuse trimming circuit of claim 3, wherein the first, fourth, sixth, seventh and tenth MOS transistors are P-type MOS transistors, the fifth, eighth, ninth and eleventh MOS transistors are N-type MOS transistors, the driving ends of the first, fourth, sixth, seventh and tenth MOS transistors are gates, the first ends of the first, fourth, sixth, seventh and tenth MOS transistors are sources, the second ends of the first, fourth, sixth, seventh and tenth MOS transistors are drains, the driving ends of the fifth, eighth, ninth and eleventh MOS transistors are gates, and the first, eighth and eleventh MOS transistors are sources.
5. The fuse trimming circuit of claim 1, wherein the mis-trimming protection unit comprises a third resistor and a third MOS tube, wherein the driving end of the third MOS tube is used for inputting a mis-trimming control signal, the first end of the third MOS tube is connected with a power supply, the second end of the third MOS tube is connected with the trimming control unit, one end of the third resistor is connected with the power supply, the other end of the third resistor is connected with the driving end of the third MOS tube,
when the third MOS tube is in the trimming period, the third MOS tube can be turned off when the driving end of the third MOS tube receives the error trimming control signal;
when the third MOS tube is in the non-trimming period, the third MOS tube can be conducted when the driving end of the third MOS tube receives the error trimming control signal to form a conducting current, and the conducting current is smaller than the current required by the trimming resistor to fuse.
6. The fuse trimming circuit of claim 5, wherein the third MOS transistor is a P-type MOS transistor, the driving end of the third MOS transistor is a gate, the first end of the third MOS transistor is a source, and the second end of the third MOS transistor is a drain.
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| JP2002033452A (en) * | 2000-07-14 | 2002-01-31 | Nec Microsystems Ltd | Semiconductor integrated circuit with fuse resistance measuring feature |
| US8058921B2 (en) * | 2009-05-08 | 2011-11-15 | O2Micro, Inc. | Fuse circuits |
| CN106057783B (en) * | 2016-05-27 | 2019-07-12 | 上海路虹电子科技有限公司 | A kind of Zapping circuit |
| CN110830022B (en) * | 2018-08-10 | 2023-08-25 | 圣邦微电子（北京）股份有限公司 | Trimming circuit and chip |
| CN114647272A (en) * | 2020-12-18 | 2022-06-21 | 圣邦微电子（北京）股份有限公司 | Trimming fuse reading circuit |
| CN115567050B (en) * | 2022-08-30 | 2023-10-24 | 贵州振华风光半导体股份有限公司 | Fuse trimming circuit |
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