KR890004153B1 - Redundant decoder of semiconductor memory device - Google Patents

Abstract

The device that can check the defect of redundant cell included in static Random Access Memory is composed of the first means controlling normal decoder and redundant decoder with the redundant cell check-signal (RC), the second means generating redundant enable signal of middle node (35) between a resistor (R4) and fuse (40), the third means generating logic by the first and second output, the fourth transmitting free decoder address signal by controlling mission gate with the third output, the fifth NORing the fourth output, and the sixth means preventing the normal decoder selection. The normal decoder is selected to the address input by the redundant cell check signal.

Description

Redundant Decoder of Semiconductor Memory Devices

1 is a conventional normal low decoder.

2 is a conventional redundant low decoder.

3 is a normal low decoder according to the present invention.

4 is a redundant decoder according to the present invention.

5 (a) and 5 (b) are redundant row decoders and normal row decoders having four rows of redundant cells according to the present invention.

* Explanation of symbols for main parts of the drawings

60: redundant decoder enable means 61: redundant cell array check means

62-65: first gate means 66-69: second gate means

70-73: means of transmission 74: CMOS sensor circuit

75: cell array enable means

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundant decoder in a semiconductor memory device, and more particularly, to a redundant decoder capable of checking a defect of a redundant cell embedded in a static random access memory.

Recently, high density semiconductor memory devices have widely used redundancy techniques in order to prevent a decrease in production yield due to defects of normal memory cells in a memory cell array during a manufacturing process. The redundancy technique installs a spare memory cell array in addition to the normal memory cell array on the same chip so that if any memory cell in the normal memory cell array fails, the row (or column) containing the defective memory cell is not defective. To a row (or column) containing.

The technique of replacing a defective cell in a current memory cell array with a defective cell electrically or physically breaks the row or column of the defective normal memory cell and replaces the memory cell of the defective row or column with the row or column of the redundant cell. It is realized by being selected by the address signal to select.

1 shows a conventional normal row decoder and a cell array, in which a normal cell array 11 (12) of a second row is connected to a normal decoder 10, and a normal decoder. Each of the normal decoders, to which the normal cell arrays are connected in rows 13 and 14, of two rows of 15, 16, and 17, respectively, has the outputs A0-A3 and B0- of the predecoder. Two inputs that use the four input NOR circuit and the four input NOR circuit with B3, C0-C3, and D0-D3 as inputs and the predecoder outputs E0 and E1 as the type forces. It consists of two MOS NAND circuits, a CMOS inverter that uses the output of each NAND gate, a fuse F0 between the output terminal of the NOR circuit and the input terminal of the NAND circuit, and a high resistance connected between the input terminal of the NAND circuit and ground. do. The normal decode 10 fuses between the CMOS noah circuit 1, which takes in the outputs A0, B0, C0, D0 of the predecoder, the output terminal of the noah circuit 1, and the node 6 of the predecoder. F0 is connected, high resistance R1 is connected between the node and ground, and the node 6 outputs the output of the NOA circuit 1, and the outputs E0 and E1 of the predecoder are used as the type force. The two input CMOS NAND circuits 2 and 3 are connected, and the output terminals of the NAND gates 2 and 3 are connected to the CMOS inverters 4 and 5, respectively. When P0 and D0 are selected and output, PMOS transistors (hereinafter referred to as PMOS) M1, M3, M5, and M7 of the NOR circuit 1 are turned ON and NMOS transistors (hereinafter referred to as NMOS) M2 and M4. M6 and M8 are turned off so that the NOR circuit 1 outputs "high" to the input terminals of the NAND circuits 2 and 3, and E0 is selected in the predecoder. When output to the NAND gate 2, the inverter 4 connected to the NAND gate 2 outputs "high", and one row 11 of the normal cell array is selected through the word line 7, and the predecoder is selected. When E1 is selected and is output to the NAND gate 3, the inverter 5 connected to the NAND gate 3 outputs "high" so that one row 12 of the normal cell array is selected through the word line 8. do.

FIG. 2 shows a conventional redundant decoder and redundant cell array, and shows a case of using two rows of redundant cell arrays for convenience.

The redundant decoder described above includes a P-Mouse 19 having an Enable Fuse FE for enabling the Redundant Decoder connected to the gate, and a connection node point 20 of the P-Mouse and the Enable-Fuse FE. A high resistance R2 connected between the ground and ground and the first signal terminal 21 connected directly to the P-MOS, the second signal terminal 22, the third signal terminal 23, and the fourth signal terminal 24; And the output of the high resistance R3 and the node 26 connected between the fifth signal terminal 25 and the node 26 and the ground between the fourth signal terminal and the fifth signal terminal as one input. Two input CMOS NAND circuits 27 and 28 having the output powers E0 and E1 of the predecoder as the type force, and the CMOS inverters 29 and 30 respectively connected to the NAND gates 27 and 28, respectively. Consists of.

The first signal terminal 21 is connected to one P-Mouse and one fuse connected in parallel and the signal of A0-A3 is connected to the gate of each P-Mouse, the second signal terminal 22 Is the same structure as the third signal terminal 23 and the fourth signal terminal 24, and the second signal terminal 22 is the B0-B3 signal, and the third signal terminal 23 is the C0- at the gate of each P-MOS. The C3 signal, the fourth signal terminal 24 is connected to the signal of D0-D3, the fifth signal terminal is connected to 16 N modose and one fuse connected in series and each N MOS The signals of A0-A3, B0-B3, C0-C3, and D0-D3 are connected to the gate, respectively. When redundancy is not used, the high resistance is applied to the node 20 so that the power supply voltage V _CC is mostly applied to R2, so that the node 20 becomes “high” and the P-MOS 19 is turned off. In addition, since the node is kept at zero due to the high resistance, the redundant decoder and the redundant cell arrays 31 and 32 do not operate.

If a defect occurs in the normal cell array and the redundant cell array is used, for example, if the defect occurs in the normal cell array 11 of FIG. 1, the fuse F0 of the normal decoder 10 is first fused. This prevents a defective normal cell array 11 from being selected. At the same time, when fusing the enable fuse FE of the redundant decoder, P-MOS is turned on, and the redundant decoder is enabled, and the fuse F2-F4 is fused in the first signal stage 21 to signal A1-A3. To block F1-F8 at the second signal stage 22 to block V1-B3 signals, and at the third signal stage 23 to fuse F10-F12 to block C1-C3 signals, The fourth signal stage 24 fuses F14-F16 to block D1-D3 signals, and the fifth signal stage 25 fuses F17, F21, F25, and F29 except A0, B0, C0, and D0. Ensure that only signals are connected.

After fusing as described above, if signals of A0, B0, C0, D0, and E0 are output from the predecoder, the normal cell 11 is not selected, but the redundant cell 31 is selected through the redundant decoder to be normal. It can be seen that cell 11 has been replaced by redundancy cell 31. In this case, the repair is performed without determining whether the redundant cell array is defective or not. If the normal cell is replaced with a defective redundant cell, a malfunction occurs even after repair.

It is therefore an object of the present invention to provide a normal decoder and a redundant decoder capable of combined check of a redundant cell array, which enables replacing a defective normal cell with a defect free redundant cell.

Hereinafter, with reference to the accompanying drawings will be described in detail.

3 illustrates a redundant row decoder and redundant cell array in accordance with the present invention.

The redundant decoder of the present invention connects a high resistance R4 and a fuse F40 between a power supply terminal and ground, and outputs the node to the node 35 between the high resistance R4 and the fuse F40. Redundant cell array shank means 61 of means 60 and a high resistance R5 connected between a redundant cell check signal (RC) terminal 33 and the signal terminal 33 and ground; First gate means connected to the decoder enable means 60 and the cell array shank means 61 and outputting two signals which are opposite to each other and turning on a gate for transmitting a predetermined address signal according to the RC signal ( 62) (63) (64) (65), and second gate means (66) (67) (68) (69) connected to the decoder enable signal means and outputting two signals which are opposite to each other; Connected to the first gate means and the second gate means to the output of the means; D) transmission means (70) (71) (72) (73) consisting of a transmission gate for transmitting a predetermined address signal and a fuse connected in series with the transmission gate; Two input NAND gates having the output of the NMOS circuit 74 and the output of the NOA circuit as the input power, and the output E0 and E1 of the predecoder as the type force, and an inverter connected to the output terminal of each NAND gate. An array enable means 75, and high resistances R6, R7, R8, and R9 connected between the respective transmission means and the power supply stage.

In FIG. 3, the first gate means comprises a two-input noah gate that takes in the output of the decoder enable means and the cell array shank means, and an inverter connected to the noah gate. It is connected to the coder enable means and outputs a signal opposite to each other through the first inverter and the second inverter, the transmission means is a transmission gate and the second input to the two opposite outputs of the first gate means The two opposite outputs from the two gate means are connected to the input of three transmission gates.

4 shows a normal decoder according to the present invention, which shows a normal decoder in the case of using two rows of redundant cell arrays and a cell array shank as a predecoder signal of A0, B0, C0, and D0. It is. The normal decoder circuit 10 has the same reference numeral as in FIG. 1 and uses the same reference numeral, and adds P-MOS 80 that uses the RC signal as the gate input between P-MOS M1 having AC as the input signal and the power supply terminal. The difference is that it is made.

The operations of the normal decoder and the redundant decoder are as follows.

First, when the normal decoder is in operation, the RC signal stage 33 and the node 35 of FIG. 3 are kept at zero level, so the p-MOS of FIG. 4 is turned on and according to the address signal. In the redundant decoder, the outputs of the NOR gates 40, 41, 42, 43, and the inverters 48, 50, 52, 54 are high to the PMOS of the transmission gate. And the outputs of the inverters 44, 45, 46, 47, 49, 51, 53, 53 are connected to the N gate of the transmission gate in a low state, so that the transmission gate (T1- T16) is off so that the redundant decoder and redundant cell array do not operate.

Second, when the redundant cell array is checked, if the RC signal stage of FIG. 3 is kept high, the input of the first gate means 62 is changed as shown in the transmission means 70 in the redundant decoder so that the noah gate is changed. 40 outputs a low to P-MOS of transmission gate T1, and inverter 44 outputs a high to N-MOS to turn the transmission gate on, thereby causing the A0 signal to pass through transmission gate T1 and fuse F41. B0 in the transfer means 71, C0 in the transfer means 72, and D0 in the transfer means 73 are transferred to the Noah circuit 74 to the input of the cell array enable means 75. It outputs high and the redundant cells 76 or 77 are selected according to the outputs E0, E1 of the predecoder. In addition, the normal cells corresponding to the signals A0, B0, C0, and D0 of the predecoder during the check of the redundant cell are turned off by the RC signal, so the normal cell decoder does not operate. Signal from predecoder Even when A0, B0, C0, and D0 enter, it is possible to prevent both the normal cell and the pendant cell from being selected.

Third, when using a redundant cell without defect after confirming that the redundant cell is not defective, for example, the cell array 11 is defective, first fuse fuse F0 of the normal decoder to detect a defective cell array. After impossible to meet the selection of, fuse F40 of the redundant decoder enable means of FIG. 3 is fused to enable the redundant decoder.

Fusing F0 with F0 in the normal decoder gives a low state to the input terminals of the NAND circuits (2) and (3) and outputs a low state to the inverters (4) and (5) connected to the NAND circuit. Line 7 (8) is not selected. In an enabled redundant decoder, the first gate means and the second gate means turn on the respective transmission gates to output the outputs A0-A3, B0-B3, C0-C3, and D0-D3 of the predecoder. It can be delivered to). The fuses in the other delivery means except for the fuse F41 of the transfer means 701, the fuse F45 of the shear means 71 and the fuse F49 of the shear means 72 and the fuse F53 of the transfer means 73 When it is wooded, when a signal of A0, B0, C0, D0 is received, the redundant cell array is selected instead of the normal cell array.

In the above, only the two rows of redundant cell arrays are considered, but in the fifth (a) and the fifth (b) diagrams, redundant decoders, normal decoders, and respective decoders when there are four rows of redundant cell arrays are shown. The connected cell arrays are shown.

FIG. 5 (a) shows a redundant decoder with four rows of redundant cell arrays, where block 81 will be identical to the redundant decoder in FIG. 3 and blocks 82 and 83 each represent a cell array ( 76) The same as (77), block 84 is the same component as block 81, but the first gate, the first so that the cell array (85) and (86) cell array is selected when the RC signal is high; The transmission gate of the two gate means and the transmission means is connected.

5 (b) shows a normal decoder having a redundant decoder with four rows of redundant cell arrays, in which blocks 88, 92 and 95 are the normal decoder blocks 10 of FIG. (13) is the same as (14), and blocks (89) (90) (93) (94) (96) (97) are normal cell array blocks (11) (12) (15) (16) (17) ( 18), the RC signal becomes high and the redundancy decoder is enabled and when a predetermined signal is input to check the redundancy cell, the same signal is input and enabled so that a normal decoder is enabled. RC signal is inputted to the normal decoder of FIG. 5 (b) which inputs a predetermined signal selected from the decoders 81 and 84 of FIG. 5 (a) in order not to select two decoders. When the RC signal is turned high by connecting the P-mode to be connected, the redundancy cell array is selected as the predetermined signal, but the P-cell is high in the normal cell array. It is off because it is not activated.

By adding one more redundant decoder connected to the RC signal stage in the same way as above, at the same time, when the RC signal becomes high, P is the gate input to the normal decoder selected as the same signal as the output of the selected predecoder. The redundant cell array can be expanded by connecting the mods.

As described above, in the memory cell array which is gradually integrated and increased in probability of defects, the present invention checks whether the redundant cell array is defective before replacing the defective normal cell and the redundant cell. By replacing the generated normal cell, there is an advantage that the redundancy cell can be effectively repaired by preventing the malfunction of the redundancy cell and causing malfunction even after replacing the cell.

Claims (5)

A static random access memory device having a normal decoder and a redundant decoder, comprising: first means for controlling operations of the normal decoder and the redundant decoder by switching in response to a redundant cell check signal RC; Second means for generating a redundant decoder enable signal from an intermediate node point 35 of the high resistance R4 to which the power is applied and the fuse 40, the output of the first means and the second means A third means for generating a predetermined logic by an output, a fourth means for controlling a transmission gate in accordance with an output of the third means, and transmitting a predecoder address signal, and for outputting the output of the fourth means. A fifth means and a sixth means for preventing the normal decoder from being selected as an input of a predetermined address by the redundant cell check signal in the normal decoder. Redundant decoder circuitry. 2. The circuit of claim 1, wherein the first means is configured to ground a resistor (R5) at the output of the redundant cell check signal stage (RC) to obtain a normal decoder and a redundant decoder selection level signal. 3. The third means according to claim 1, wherein the third means inputs a redundant cell check signal and a redundant decoder enable signal to the noar gates 40 and 41 by the inverters 44 and 45 from the noar gates 40 and 41. First gate means for obtaining different outputs, and second means for inverting the redundant decoder signals at inverters 48 and 50 to obtain different outputs by inverters 45 and 51. Circuit. The method of claim 1, wherein the fourth means applies different outputs of the fifth means to the transmission gates T1-T16 to input input decoder signals A0-A3, B0-B3, C0-C3, Circuitry, configured to carry D0-D4). The circuit according to claim 1, wherein the sixth means is configured by connecting a P-MOS transistor whose gate input is a redundant cell check signal to a normal decoder for selecting a predetermined address.

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