JP2010157923A - Clock generating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain, in a simple circuit configuration, a clock generating circuit capable of shortening the time required for lock, even if a reference clock at any frequency within a wideband frequency range is received. <P>SOLUTION: The clock generating circuit includes a delay unit 11 for generating a first delay clock, by making a reference clock through a first number of voltage controlled delay elements 12-1 to 12-N delayed and for generating a second delay clock, by delaying the reference clock through a second number of voltage controlled delay elements 12-1 to 12-K; a phase comparator 21 for comparing a phase of the reference clock with that of the first delay clock; a charge pump 22 for outputting a delay control current; a delay control unit 23; a determination unit 13a for comparing the phase of the reference clock with that of the second delay clock and determine the phase difference between the reference clock and the first delay clock; and a charge control unit 13b for performing a control, such that when the phase difference is greater than the threshold, the delay control current becomes a first value; and when the phase difference is smaller than or equal to the threshold, the delay control current becomes a second value which is smaller than the first value. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a clock generation circuit.

  A delay locked loop circuit (hereinafter abbreviated as a DLL circuit; DLL; Delay Locked Loop) includes a reference clock and a delay clock with respect to a reference clock output from a voltage control delay line (hereinafter abbreviated as VCDL; Voltage Controlled Delay Line). This circuit locks the delay amount. The DLL circuit outputs the delay clock to the semiconductor integrated circuit so that the clock of the semiconductor integrated circuit can be synchronized. The DLL circuit is required to shorten the time until locking.

  Patent Documents 1 and 2 describe a technique for shortening the time until locking.

  In the DLL circuit disclosed in Patent Document 1, in addition to the phase comparator 21, the charge pump 22, and the loop filter 23, a set value determination circuit 26 and a voltage setting circuit 27 are provided as a circuit for generating the control voltage VC. It has been. In order to switch between a state in which the control voltage VC is generated by the phase comparator 21, the charge pump 22 and the loop filter 23, and a state in which the control voltage VC is generated by the set value determination circuit 26 and the voltage setting circuit 27. And a power supply control circuit 29 is provided. That is, in the DLL circuit disclosed in Patent Document 1, two circuits for generating the control voltage VC are provided, and a circuit for switching which of the two systems is activated is provided. This complicates the circuit configuration as a whole. This may increase the chip area.

Patent Document 2 describes a PLL circuit 300 shown in FIG. 5 of Patent Document 2 as a specific configuration of the PLL circuit 100 shown in FIG. 1 of Patent Document 2. In the PLL circuit 300, the lock detection circuit 6 includes a charging circuit 15, an N-channel MOS transistor (discharge circuit) 20, and a capacitor 21. Charging circuit 15 charges capacitor 21 by supplying a charging current to capacitor 21 in response to signal UP or signal DOWN received from phase comparator 51 ′. N-channel MOS transistor 20, by leak a small current _{I L} from the drain node N15 of the source side to a fixed potential Vs, to discharge the capacitor 21.

Here, the device characteristics of the N-channel MOS transistor 20 and the like must be designed with high accuracy. That is, the discharge current _{I L} to the N-channel MOS transistor 20 from the capacitor 21, if the charging circuit 15 at the time of locking smaller than the charging current to the capacitor 21, stops the current of the charge pump 10, PLL circuit 300 does not operate . Conversely, the discharge current I _L from the capacitor 21 to the N-channel MOS transistor 20, if the charging circuit 15 at the time of locking is greater than the charging current to the capacitor 21, the phase comparator 21, the following operation will have to go. The phase comparator 21 continues to output the UP signal and the DOWN signal having an offset in order to match the discharge current _IL and the charging current.

That, PLL circuit (or DLL circuit) shown in Patent Document 2, when the phase relationship (or delay) is locked, and the discharge current _{I L} to the charging current and the N-channel MOS transistor 20 from the charging circuit 15 If they are not exactly the same, they cannot operate stably. In this way, it is practically difficult to design a PLL circuit (or DLL circuit) so that the charging current and the discharging current _IL are completely the same.
JP 2006-025131 A Japanese Patent No. 3561035

  By the way, in a device using a DLL circuit, the frequency of the reference clock may be in a wide band. In this case, it is necessary to shorten the time until the DLL circuit is locked, regardless of the frequency of the reference clock received in the continuous frequency range over a wide band.

  In addition, some devices that use DLL circuits are required to be downsized. In this case, in order to reduce the mounting area of the DLL circuit, it is necessary to reduce the chip area of the DLL circuit. For this purpose, it is necessary to simplify the configuration of the DLL circuit.

  An object of the present invention is to realize a clock generation circuit capable of shortening the time required to lock a reference clock of any frequency in a frequency range over a wide band with a simple circuit configuration.

  A clock generation circuit according to one aspect of the present invention includes a first number of voltage-controlled delay elements connected in series, and delays a reference clock by the first number of voltage-controlled delay elements. A first delay clock having a first delay amount with respect to the clock is generated and output, and the reference clock is used as a second number of voltages that are part of the first number of voltage controlled delay elements. A delay unit that generates a second delay clock having a second delay amount smaller than the first delay amount with respect to the reference clock by being delayed by a control delay element; a phase of the reference clock; A phase comparator that compares the phase of one delay clock and outputs a rising signal or a falling signal according to the comparison result; and a charge that outputs a delay control current according to the rising signal or the falling signal And generating a delay control voltage in response to the delay control current and supplying the generated delay control voltage to each of the first number of voltage control delay elements. A delay control unit that controls the first delay amount so that one delay clock is synchronized, and the reference clock and the first delay clock are compared by comparing the phase of the reference clock with the phase of the second delay clock. When the determination unit determines whether the phase difference from the delay clock is equal to or less than a threshold value, and the determination unit determines that the phase difference is greater than the threshold value, the delay control current is set to a first value. When the determination unit determines that the phase difference is equal to or less than the threshold value, the charge pump is controlled so that the delay control current becomes a second value smaller than the first value. Characterized by comprising a Yaji controller.

  According to the present invention, it is possible to realize a clock generation circuit capable of shortening the time required to lock any frequency reference clock in a wide frequency range with a simple circuit configuration.

  A DLL circuit 1 according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a diagram showing a configuration of a DLL circuit 1 according to the first embodiment of the present invention. Hereinafter, the p-channel MOS transistor is abbreviated as pMOS, and the n-channel MOS transistor is abbreviated as nMOS.

  The DLL circuit (clock generation circuit) 1 receives the reference clock CK0 and outputs a delayed clock CK-N delayed with respect to the reference clock CK0. DLL is an abbreviation for Delay Locked Loop. The reference clock CK0 has a duty ratio r.

  The DLL circuit 1 includes a VCDL (delay unit) 11, a phase comparator (phase comparator) 21, an inverter 35, a charge pump 22, a loop filter (delay controller) 23, and a determination circuit 13. Here, VCDL is an abbreviation for Voltage Controlled Delay Line (voltage control delay line).

  The VCDL 11 includes N (first number) voltage-controlled delay elements 12-1 to 12-N connected in series. Each of the N voltage control delay elements 12-1 to 12 -N has a propagation delay amount corresponding to the control voltage VC received from the loop filter 23. The propagation delay amounts of the N voltage controlled delay elements 12-1 to 12-N are preferably the same. For example, N = 32.

  The VCDL 11 delays the reference clock CK0 by the N voltage control delay elements 12-1 to 12-N, thereby having a delay clock (first delay clock) having a first delay amount with respect to the reference clock CK0. CK-N is generated and output. The first delay amount corresponds to the total propagation delay amount of the N voltage controlled delay elements 12-1 to 12-N.

At the same time, the VCDL 11 uses the K (second number) voltage-controlled delay elements 12-1 to 12-K as the reference clock CK0 as a part of the N voltage-controlled delay elements 12-1 to 12-N. Delay. Thereby, the VCDL 11 generates a delay clock (second delay clock) CK-K having a second delay amount with respect to the reference clock CK0. The second delay amount is smaller than the first delay amount. The K voltage control delay elements 12-1 to 12-K are less than N in the N voltage control delay elements 12-1 to 12-N and more than the number obtained by multiplying N by (1-r). This is a voltage controlled delay element. That is,
N × (1-r) <K <N Equation 1
It is. For example, when the duty ratio r = 0.5 of the reference clock CK0,
N / 2 <K <N Expression 2
It is. For example, when r = 0.5 and N = 32, K = 17 from Equation 2.

  Here, the second delay amount corresponds to the total propagation delay amount of the K voltage control delay elements 12-1 to 12-K. That is, since the second delay amount depends on the number of voltage controlled delay elements to be used, the frequency of the reference clock CK0 is smaller than the first delay amount regardless of the frequency.

  The phase comparator 21 receives a reference clock CK0 from the outside, and receives a delay clock CK-N from the VCDL 11. The phase comparator 21 compares the phase of the reference clock CK0 with the phase of the delay clock CK-N, and outputs the rising signal UP or the falling signal DOWN according to the comparison result to the charge pump 22. The descending signal DOWN has, for example, an H level as an active level.

  When the inverter 35 receives the rising signal UP from the phase comparator 21, the inverter 35 inverts the logic level of the rising signal UP and outputs the rising signal UP￣ with the logic level inverted to the charge pump 22. For example, the L level is the active level of the rising signal UP￣.

  The charge pump 22 outputs a delay control current to the loop filter 23 in response to the rising signal UP￣ or the falling signal DOWN. The charge pump 22 includes an output node NCP, a charging unit 221, and a discharging unit 222. Charging unit 221 supplies a charging current to output node NCP in response to rising signal UP. Discharge unit 222 sucks a discharge current from output node NCP in response to falling signal DOWN.

  The charging unit 221 includes a source current source (charging current source) 29, an additional source current source (variable current source) 33, and a pMOS switch 31. The discharge unit 222 includes a sink current source (discharge current source) 30, an additional sink current source (variable current source) 34, and an nMOS switch 32.

  The output node NCP connects the drain of the pMOS switch 31, the drain of the nMOS switch 32, and the input terminal of the loop filter 23 to each other. The output node NCP is a node for outputting a delay control current.

  The source current source 29 is a constant current source that outputs a constant current. The additional source current source 33 is a variable current source that outputs a current corresponding to the charge control signal CR supplied from the determination circuit 13.

  The pMOS switch 31 is turned on to connect the source current source 29 and the additional source current source 33 and the output node NCP when receiving the active level (for example, L level) rising signal UP. As a result, the sum of the constant current flowing out from the source current source 29 and the current flowing out from the additional source current source 33 is supplied to the loop filter 23 via the output node NCP as a charging current. That is, the charge pump 22 outputs a charging current in the direction from the charge pump 22 toward the loop filter 23 to the loop filter 23 as a delay control current.

  The sink current source 30 is a constant current source that absorbs a constant current. The additional sink current source 34 is a variable current source that sucks current corresponding to the charge control signal CR supplied from the determination circuit 13.

  The nMOS switch 32 is turned on so as to connect the sink current source 30 and the additional sink current source 34 and the output node NCP when receiving the falling signal DOWN of the active level (for example, H level). As a result, the sum of the constant current sucked by sink current source 30 and the current sucked by additional sink current source 34 is sucked as discharge current from loop filter 23 via output node NCP. That is, the charge pump 22 outputs a discharge current in the direction from the loop filter 23 toward the charge pump 22 to the loop filter 23 as a delay control current.

  The loop filter 23 generates a delay control voltage VC according to the delay control current. That is, the loop filter 23 smoothes the delay control current by removing the high frequency component of the delay control current. The loop filter 23 generates the delay control voltage VC by converting the smoothed delay control current to the delay control voltage VC. The loop filter 23 supplies the generated delay control voltage VC to each of the N voltage control delay elements 12-1 to 12-N. The loop filter 23 also serves to alleviate fluctuations in the delay control voltage VC at the delay control node NC and reduce the jitter of the delay clock CK-N. Thereby, the loop filter 23 performs control so that the reference clock CK0 and the delay clock CK-N are synchronized. In other words, the loop filter 23 controls the first delay amount so that the first delay clock is synchronized with the reference clock CK0.

  The determination circuit 13 includes a determination unit 13a and a charge control unit 13b.

  The determination unit 13a receives the reference clock CK0 from the outside, and receives the delay clock CK-K from the output terminal (intermediate tap) of the voltage control delay element 12-K. The determination unit 13a determines whether the DLL circuit 1 is in the vicinity of the locked state by comparing the phase of the reference clock CK0 and the phase of the delay clock CK-K. Specifically, the determination unit 13a determines whether or not the phase difference between the reference clock CK0 and the delay clock CK-N is equal to or less than a threshold value.

  For example, when the level of the delay clock CK-K is at the first logic level (for example, L level) at the timing synchronized with the reference clock CK0, the determination unit 13a determines the phase difference between the reference clock CK0 and the delay clock CK-N. Is determined to be greater than the threshold. The determination unit 13a determines that the phase difference between the reference clock CK0 and the delay clock CK-N is a threshold when the level of the delay clock CK-K is at the second logic level (for example, H level) at the timing synchronized with the reference clock CK0. It is determined that: The determination unit 13a supplies the determination result to the charge control unit 13b.

  The charge control unit 13b generates a charge control signal CR according to the determination result, and supplies the generated charge control signal CR to the charge pump 22 via the charge control node NI. Thereby, the charge control unit 13b charges the delay control current so that the delay control current becomes the first value when the determination unit 13a determines that the phase difference between the reference clock CK0 and the delay clock CK-N is larger than the threshold. The pump 22 is controlled. In the charge control unit 13b, when the determination unit 13a determines that the phase difference between the reference clock CK0 and the delay clock CK-N is equal to or less than the threshold value, the delay control current becomes a second value smaller than the first value. Thus, the charge pump 22 is controlled.

  Specifically, the charge control unit 13b performs the following control when the determination unit 13a determines that the phase difference between the reference clock CK0 and the delay clock CK-N is larger than the threshold value. The charge control unit 13b controls the charging unit 221 and the discharging unit 222 so that the charging unit 221 starts the first charging current or the discharging unit 222 sucks the first discharging current.

  The charge control unit 13b performs the following control when the determination unit 13a determines that the phase difference between the reference clock CK0 and the delay clock CK-N is equal to or less than the threshold value. The charge control unit 13b controls the charging unit 221 and the discharging unit 222 such that the charging unit 221 starts the second charging current or the discharging unit 222 sucks the second discharging current. The second charging current is smaller than the first charging current. The second discharge current is smaller than the first discharge current.

  For example, when it is determined that the phase difference between the reference clock CK0 and the delay clock CK-N is larger than the threshold value, the charge control unit 13b sends the charge control signal CR of the active level (for example, H level) to the additional source current source 33 and The additional sink current source 34 is supplied. As a result, the additional source current source 33 is turned on, so that the charging unit 221 uses the first charging current, which is a combination of the constant current flowing out from the source current source 29 and the current flowing out from the additional source current source 33, as the output node NCP. Pour into. Alternatively, the additional sink current source 34 is turned on, so that the discharge unit 222 sucks the first discharge current, which is a combination of the constant current sucked by the sink current source 30 and the current sucked by the additional source current source 33, from the output node NCP.

  For example, when it is determined that the phase difference between the reference clock CK0 and the delay clock CK-N is equal to or less than the threshold value, the charge control unit 13b outputs a charge control signal CR having a non-active level (for example, L level) as an additional source current source. 33 and the additional sink current source 34. As a result, the additional source current source 33 is turned off, so that the charging unit 221 supplies the constant current output from the source current source 29 as the second charging current to the output node NCP in response to the active level increase signal UP. put out. Alternatively, since additional sink current source 34 is turned off, discharge unit 222 sucks the constant current sucked by sink current source 30 from output node NCP as the second discharge current in response to active level falling signal DOWN.

  In this way, the delay clock CK-N is generated using the N voltage control delay elements 12-1 to 12-N, and the K voltage control delay elements 12-1 to 12-K, which are fewer than N, are used. To generate a delay clock CK-K. Then, by comparing the phase of the reference clock CK0 and the phase of the delay clock CK-K, it is determined whether or not the phase difference between the reference clock CK0 and the delay clock CK-N is equal to or less than a threshold value. As a result, it can be determined that the delay clock CK-N and the reference clock CK0 have approached the synchronized state before the delayed clock CK-N to be output and the reference clock CK are synchronized.

  Further, when the delay clock CK-N and the reference clock CK0 are synchronized, that is, far from the lock state, the lock operation is performed according to the large delay control current of the first value, so that the DLL circuit is in the vicinity of the lock state. The locking operation up to can be performed at high speed. In addition, since the lock operation is performed according to the small second-value delay control current when the DLL circuit is in the vicinity of the lock state, fluctuations in the delay control voltage can be reduced. That is, regardless of the frequency of the reference clock in a wide frequency range, a large lock operation can be performed at a high speed when the clock is far from the locked state, and fluctuations in the delay control voltage near the locked state can be reduced. This makes it possible to shorten the time until locking regardless of the reference clock having any frequency in the frequency range over a wide band.

  Further, the circuit for generating the delay control voltage is a one-system circuit including the phase comparator 21, the determination circuit 13, the charge pump 22, and the loop filter 23. For this reason, the circuit configuration is simplified as a whole. Further, since the determination circuit 13 only needs to have a function of performing phase comparison between the reference clock CK0 and the delay clock CK-K and outputting a control signal according to the comparison result, it is realized with a simple circuit configuration. Is possible. Also from this point, the circuit configuration is simplified as a whole.

  Therefore, according to the present embodiment, it is possible to realize a DLL circuit that can shorten the time required to lock any frequency reference clock in a frequency range over a wide band with a simple circuit configuration.

  In addition, since the fluctuation of the delay control voltage in the vicinity of the locked state can be reduced, the jitter of the DLL circuit can be reduced before the locked state is reached.

  Further, instead of providing a plurality of charge pumps, the charge pump current is increased by the additional current source (addition source current source, additional sink current source) of the charge pump. For this reason, the number of gates driven by the phase comparator is small, and the burden on the phase comparator is small.

  Furthermore, since both the additional source current source and the additional sink current source are prepared as the additional current source of the charge pump, the balance of the charge pump is good.

  Next, the internal configuration of each of the N voltage controlled delay elements 12-1 to 12-N will be described with reference to FIG. FIG. 2 is a diagram illustrating an internal configuration of each of the N voltage controlled delay elements 12-1 to 12-N according to the first embodiment of the present invention.

  The voltage control delay element 12 -K includes nMOSs 121 to 124 and pMOSs 125 and 126. The nMOSs 123 and 125 operate as the inverter INV1, and the nMOSs 124 and 126 operate as the inverter INV2. The nMOSs 121 and 122 can be regarded as substantially constant current sources when the inverters INV1 and INV2 respond. The propagation delay amount of this delay element is substantially determined depending on this current value. As a result, the voltage control delay element 12-K outputs the delay clock CK-K having a delay amount corresponding to the determined propagation delay amount with respect to the input delay clock CK- (K-1). Output to -K.

  Here, the delay control voltage VC is supplied to the gates of the nMOSs 121 and 122 via the delay control node NC. That is, by controlling the gate voltages of the nMOSs 121 and 122, the drain current values of the nMOSs 121 and 122 can be controlled, and as a result, the propagation delay amount of the present delay element can be controlled. In the case of FIG. 2, when the gate voltages of the nMOSs 121 and 122 increase, the propagation delay amount of the delay element decreases.

  Thus, since each voltage control delay element is comprised using several nMOS and several pMOS, each voltage control delay element is realizable with a simple circuit structure.

  The internal configurations of the other voltage control delay elements 12-1 to 12- (K-1) and 12- (K + 1) to 12-N are the same as the internal configuration of the voltage control delay element 12-K.

  Next, the internal configuration of the determination circuit 13 will be described with reference to FIG. FIG. 3 is a diagram showing an internal configuration of the determination circuit 13 in the first embodiment of the present invention.

  The determination circuit 13 includes a rising edge detection type D flip-flop 14 of the CK terminal. That is, the determination unit 13 a and the charge control unit 13 b include a D flip-flop 14.

  The determination unit 13a includes portions corresponding to the D terminal and the CK terminal in the D flip-flop 14, receives the reference clock CK0 on one of the D terminal and CK terminal, and receives the delayed clock CK-K on the other of the D terminal and CK terminal. receive. FIG. 3 illustrates a case where the reference clock CK0 is received at the D terminal and the delay clock CK-K is received at the CK terminal.

  The determination unit 13a determines that the DLL circuit 1 is not in the vicinity of the locked state if the level of the delayed clock CK-K received at the D terminal is L level at the rising edge of the reference clock CK0 received at the CK terminal. In this case, the determination unit 13a continues to supply an L level signal indicating that it is not in the vicinity of the locked state to the charge control unit 13b as a determination result until the next rising edge of the reference clock CK0.

  The determination unit 13a determines that the DLL circuit 1 is in the vicinity of the locked state if the level of the delayed clock CK-K received at the D terminal is H level when the reference clock CK0 received at the CK terminal rises. In this case, the determination unit 13a continues to supply an H-level signal indicating that it is in the vicinity of the locked state to the charge control unit 13b as a determination result until the next rising edge of the reference clock CK0.

  The charge control unit 13b includes a portion corresponding to the Q terminal or the QB terminal in the D flip-flop, and outputs a charge control signal CR for controlling the charge pump from the Q terminal or the QB terminal to the charge control node NI. FIG. 3 illustrates the case where the charge control signal CR is output from the QB terminal to the charge control node NI.

  When the charge control unit 13b receives an L level signal indicating that it is not in the vicinity of the locked state from the determination unit 13a, the charge control unit 13b charges the H level signal from the QB terminal so that the delay control current becomes the first value. Output as control signal CR. In this case, the charge control unit 13b continues to output the H level charge control signal CR from the QB terminal until the next rising edge of the reference clock CK0. That is, the charge control unit 13b receives the charge control signal CR of the active level (for example, H level) from the additional source current source 33 and the additional sink while the determination unit 13a determines that the DLL circuit 1 is not in the vicinity of the locked state. The supply to the current source 34 is continued.

  When the charge control unit 13b receives an H level signal indicating that it is in the vicinity of the locked state from the determination unit 13a, the charge control unit 13b charges the L level signal from the QB terminal so that the delay control current becomes the second value. Output as control signal CR. In this case, the charge control unit 13b continues to output the L level charge control signal CR from the QB terminal until the next rising edge of the reference clock CK0. That is, the charge control unit 13b adds the non-active level (for example, L level) charge control signal CR to the additional source current source 33 and the additional source current source 33 while the determination unit 13a determines that the DLL circuit 1 is in the vicinity of the locked state. The supply continues to the sink current source 34.

  Thus, in this embodiment, since the determination circuit 13 including the determination unit 13a and the charge control unit 13b includes the D flip-flop, the determination unit 13a and the charge control unit 13b can be realized with a simple circuit configuration.

  Next, the internal configurations of the source current source 29 and the additional source current source 33 in the charging unit 221 and the internal configurations of the sink current source 30 and the additional sink current source 34 in the discharge unit 222 will be described with reference to FIG. I will explain. FIG. 4 is a diagram showing an internal configuration of each of the source current source 29, the additional source current source 33, the sink current source 30, and the additional sink current source 34 in the first embodiment of the present invention.

  The source current source 29 includes a pMOS 291. The pMOS 291 has a source connected to the power supply voltage VDD and a drain connected to the pMOS switch 31. The source current source 29 is supplied with a constant voltage (for example, ground voltage) from a constant voltage supply circuit (not shown). Thereby, the pMOS 291 flows a constant drain current to the pMOS switch 31 side as a constant current.

  The additional source current source 33 includes a pMOS 331, an inverter 333, and a pMOS 332.

  In the pMOS 331, the source is connected to the power supply voltage VDD, the drain is connected to the pMOS 332, and a constant voltage (for example, ground voltage) is supplied to the gate from a constant voltage supply circuit (not shown). As a result, the pMOS 331 causes a current to flow to the pMOS 332 side.

  The inverter 333 is connected between the charge control node NI and the gate of the pMOS 332. Inverter 333 receives charge control signal CR via charge control node NI and generates charge control signal CR￣ whose logic level is inverted. In the charge control signal CR, for example, the H level is an active level. For example, the L level of the charge control signal CR￣ is an active level. The inverter 333 supplies the generated charge control signal CR to the gate of the pMOS 332. For example, when the inverter 333 receives the H level charge control signal CR, the inverter 333 supplies the L level charge control signal CR to the gate of the pMOS 332. For example, the inverter 333 supplies the H level charge control signal CR to the gate of the pMOS 332 when receiving the L level charge control signal CR.

  The pMOS 332 has a source connected to the pMOS 331 and a drain connected to the pMOS switch 31. In the pMOS 332, the charge control signal CR is supplied from the inverter 333 to the gate. Thereby, the pMOS 332 is turned on when an active level (for example, L level) charge control signal CR 信号 is supplied to the gate, thereby causing the pMOS 331 and a current corresponding to the charge control signal CR￣ to flow to the pMOS switch 31 side. put out.

Here, if the current that the source current source 29 flows is Ic29 and the current that the additional source current source 33 flows is Ic33,
Ic29 <Ic33 (Equation 3)
It is preferable that For example, if M is an integer greater than 1,
Ic29 + Ic33 = M × Ic29 Expression 4
It is preferable that In this case, the DLL circuit 1 can flow a charging current M times as a delay control current when it is far from the locked state as compared to when it is in the vicinity of the locked state.

  For example, when Ic29 = 5 μA and Ic33 = 45 μA, M = 10. In this case, since the DLL circuit 1 can flow a charging current M times as a delay control current when it is far from the locked state compared to when it is in the vicinity of the locked state, the DLL circuit 1 performs the locking operation 10 times faster. be able to.

  On the other hand, the sink current source 30 includes an nMOS 301. The nMOS 301 has a source connected to the ground voltage GND and a drain connected to the nMOS switch 32. The sink current source 30 is supplied with a constant voltage (for example, power supply voltage) to the gate. Thereby, the nMOS 301 sucks a constant drain current from the nMOS switch 32 side as a constant current.

  The additional sink current source 34 includes an nMOS 341 and an nMOS 342.

  The nMOS 341 has a source connected to the ground voltage GND, a drain connected to the nMOS 342, and a constant voltage (for example, a ground voltage) is supplied to the gate from a constant voltage supply circuit (not shown). As a result, the nMOS 341 sucks current from the nMOS 342 side.

  The nMOS 342 has a source connected to the nMOS 341 and a drain connected to the nMOS switch 32. In the nMOS 342, the charge control signal CR is supplied to the gate through the charge control node NI. As a result, the nMOS 342 is turned on when an active level (for example, H level) charge control signal CR is supplied to the gate, thereby sucking in the current corresponding to the charge control signal CR together with the nMOS 341 from the nMOS switch 32 side.

Here, if the current that the sink current source 30 sinks is Id29 and the current that the additional sink current source 34 sinks is Id33,
Id29 <Id33 ... Formula 5
It is preferable that For example, if M is an integer greater than 1,
Id29 + Id33 = M × Id29 Expression 6
It is preferable that In this case, since the DLL circuit 1 can flow the M times the discharge current as the delay control current when it is far from the locked state as compared with when it is in the vicinity of the locked state, the DLL circuit 1 performs the locking operation at M times faster. be able to.

  For example, when Id29 = 5 μA and Id33 = 45 μA, M = 10. In this case, the DLL circuit 1 can flow a charging current M times as a delay control current when it is far from the locked state as compared to when it is in the vicinity of the locked state.

  As described above, in the present embodiment, when the DLL circuit 1 is far from the locked state as compared to when it is in the vicinity of the locked state, the M times charging current or the M times discharging current is allowed to flow as the delay control current. Can do. As a result, the DLL circuit 1 can perform a locking operation M times (for example, 10 times) faster when it is far from the locked state than when it is in the vicinity of the locked state.

  Further, the DLL circuit 1 can flow a 1 / M times charging current or a 1 / M times discharging current as a delay control current when the DLL circuit 1 is in the vicinity of the locked state as compared to when it is far from the locked state. Thereby, the DLL circuit 1 can effectively reduce the period during which the delay control voltage fluctuates when it is in the vicinity of the locked state (see FIG. 6).

  Furthermore, since the charging unit 221 is configured using a plurality of pMOSs and one inverter, and the discharging unit 222 is configured using a plurality of nMOSs, the charge pump 22 can be realized with a simple circuit configuration.

  Next, the operation of the DLL circuit 1 will be described with reference to FIG. FIG. 5 is a timing chart showing the operation of the DLL circuit 1 according to the first embodiment of the present invention.

  FIG. 5A shows the operation of the DLL circuit 1 when the DLL circuit 1 is activated. FIG. 5B shows the operation of the DLL circuit 1 in the vicinity of the locked state of the DLL circuit 1. FIG. 5C shows the operation of the DLL circuit 1 when the DLL circuit 1 is locked.

  “CK0” indicates the waveform of the reference clock CK0. “CK-K” indicates the waveform of the delayed clock CK-K. “CK-N” indicates the waveform of the delayed clock CK-N. “UP” indicates the waveform of the rising signal UP. “DOWN” indicates a waveform of the falling signal DOWN. “CR” indicates the waveform of the charge control signal CR. Note that the waveform of the charge control signal CR￣ is obtained by inverting the waveform of the charge control signal CR.

  As shown in FIG. 5A, when the DLL circuit is activated, the level of the delay control voltage VC of the delay control node NC of the VCDL 11 is the level of the power supply voltage VDD. For this reason, the delay time b1 when the delay clock CK-N rises is shorter than the delay time a1 when the reference clock CK0 rises.

  The delayed clock CK-K input to the determination circuit 13 has a pulse as shown in FIG. That is, when the reference clock CK0 rises (a1 or c1), the delay clock CK-K is at the H level. For this reason, the QB output of the D flip-flop 14 of FIG. 3, that is, the charge control signal CR becomes H level, and the additional source current source 33 and the additional sink current source 34 are turned on. At this time, the charge pump 22 supplies a current of, for example, 50 μA, and approaches the vicinity of the locked state approximately M (for example, 10) times faster than when the additional source current source 33 and the additional sink current source 34 are not provided.

  The DLL circuit 1 controls the propagation delay amount of each of the N voltage controlled delay elements so that the rise time b1 of the delay clock CK-N and the rise time c1 of the reference clock CK0 are simultaneous. Therefore, the phase comparator 21 outputs the falling signal DOWN having the same time as the time difference between the rising edge b1 of the delay clock CK-N and the rising edge c1 of the reference clock CK0. Then, since the first discharge current is sucked from the output node NCP by the sink current source 30 and the additional sink current source 34, the voltage of the output node NCP decreases. Then, the level of the delay control voltage VC output from the loop filter 23 to the delay control node NC also decreases, and the propagation delay amount of each of the N voltage control delay elements increases. Accordingly, the position b1 shifts backward when the delay clock CK-N rises.

  As shown in FIG. 5B, the DLL circuit 1 is in the vicinity of the lock state when the positions of the delay clock CK-N rise time a2 and the reference clock CK0 rise time d2 are close to each other to some extent. It is just before. When the DLL circuit 1 is immediately before the lock state, the delay clock CK-K is at the L level at the rising edge a2 of the reference clock CK0, so that the charge control signal CR is at the H level.

  When the position b2 of the delay clock CK-N rises and the position c2 of the reference clock CK0 rises sufficiently, the DLL circuit 1 is in the vicinity of the locked state. When the DLL circuit 1 is in the vicinity of the locked state, the delay clock CK-K is at the H level at the rising edge of the reference clock CK0, so that the charge control signal CR is at the L level. Therefore, the charge control signal CR becomes L level after the rising edge c2 of the reference clock CK0. Therefore, the additional source current source 33 and the additional sink current source 34 are set to be turned off, and only a current of, for example, 5 μA flows through the charge pump. Even in this state, the phase comparator 21 outputs the falling signal DOWN according to the time difference between the rising edge b2 of the delay clock CK-N and the rising edge c2 of the reference clock CK0. For this reason, when the delay clock CK-N rises, b2 is further delayed and approaches the locked state.

  Then, as shown in FIG. 5C, when the rising edge b3 of the delay clock CK-N and the rising edge c3 of the reference clock CK0 are simultaneous, the DLL circuit 1 is locked. In the locked state, the pulse widths of the falling signal DOWN and the rising signal UP of the phase comparator 21 are the same, and the voltage fluctuation at the charge control node NC falls within the voltage range to be transitioned. In this state, the charge pump 22 operates with a small current of, for example, 5 μA, and not only can the current consumption be reduced, but also the voltage fluctuation at the charge control node NC is small, so the jitter of the delay clock CK-N is small.

  In this way, the phase of the reference clock CK0 is compared with the phase of the delayed clock CK-K whose phase difference in the locked state with respect to the reference clock CK0 is larger than (1-r) period and smaller than one period. . Thereby, it can be determined whether or not the DLL circuit 1 is in the vicinity of the locked state.

  Next, in order to clarify the effect of the present invention, FIG. 6 shows a simulation result of the temporal change of the delay control voltage VC in the DLL circuit 1 according to the first embodiment of the present invention. FIG. 6 is a diagram showing a simulation result of a temporal change in the delay control voltage VC in the DLL circuit 1 according to the first embodiment of the present invention.

  FIG. 6 shows temporal changes in the level of the delay control voltage VC at the delay control node NC of the VCDL 11 from the time when the DLL circuit 1 is started. During the period from the activation of the DLL circuit 1 to the timing d, the charge pump 22 turns on the sink current source 30 and the additional sink current source 34 to flow a current of 50 μA. For this reason, the timing d near the lock is reached about 10 times faster than when only the sink current source 30 supplies only a current of 5 μA. After the timing d, the additional source current source 33 and the additional sink current source 34 are turned off, and the delay control voltage VC gradually changes to the lock timing e by the source current source 29 and the sink current source 30. After the lock timing e, the current flowing through the source current source 29 and the sink current source 30 is balanced, so that the delay control voltage VC varies within the voltage range to be transitioned. In other words, during the period from timing d to e, the delay control voltage VC does not vary beyond the voltage range to be transitioned, and the variation of the delay control voltage VC is reduced.

  As described above, according to the present embodiment, since the charge pump current is increased or decreased by the determination by the logic of the determination circuit, the time to the lock state can be shortened even when the frequency of the reference clock is wide. In the locked state, the jitter of the delayed clock CK-N can be reduced and the phase offset is also small.

  Further, since the determination circuit is composed of a logic circuit, it is not necessary to prepare an intermediate voltage and a charging circuit is not necessary. Therefore, the DLL circuit according to this embodiment has a simple circuit configuration and a small occupied area.

  Next, a DLL circuit 1i according to a second embodiment of the present invention will be described.

  The DLL circuit 1i includes a charge pump 22i. As shown in FIG. 7, the charge pump 22i includes a charging unit 221i. The charging unit 221i does not include the additional source current source 33 (see FIG. 4). FIG. 7 is a diagram showing the configuration of the charge pump 22i in the second embodiment of the present invention.

  Here, an nMOS current source control type voltage control delay element similar to that of the first embodiment is used as the voltage control delay element. Therefore, the level of the delay control voltage VC with respect to the VCDL 11 at the time of starting the DLL circuit 1i is the level of the power supply voltage VDD which is an active level. For this reason, the charge pump 22i does not require an additional source current source in the current increase mode far from the locked state. Therefore, the additional source current source is removed, and only the additional sink current source 34 is used as the additional current source. This eliminates the need for an additional source current source composed of pMOS, and has the effect of reducing the occupied area.

  The above description has been given using an example in which an nMOS current source control type voltage control delay element similar to the first embodiment is used as the voltage control delay element. On the other hand, when a voltage-controlled delay element of the pMOS current source control type is used as the voltage-controlled delay element, the level of the delay control voltage VC with respect to VCDL at the time of starting the DLL circuit becomes the level of the ground voltage GND that is the active level. In this case, it is desirable that the additional current source is only the additional source current source and the additional sink current source is omitted.

  Next, a DLL circuit 1j according to a third embodiment of the present invention will be described with reference to FIG. FIG. 8 is a diagram showing a configuration of a DLL circuit 1j according to the third embodiment of the present invention.

  The DLL circuit 1j includes L charge pumps 46-1 to 46-L, that is, a plurality of charge pumps 46-1 to 46-L, and a determination circuit 13j.

  Each of the L charge pumps 46-1 to 46-L is the same as that obtained by removing the additional source current source 33 and the additional sink current source 34 from the charge pump 22 in the first embodiment.

The determination circuit 13j includes a charge control unit 13bj. When it is determined by the determination unit 13a that the charge control unit 13bj is not in the vicinity of the locked state, the third number Q1 (≦ L) of the charge pumps 46-1 in the L charge pumps 46-1 to 46-L. Operate ~ 46-Q1. When the determination unit 13a determines that the charge control unit 13bj is in the vicinity of the locked state, the fourth number Q2 of charge pumps 46-1 to 46-Q2 in the L charge pumps 46-1 to 46-L. To work. The fourth number Q2 is smaller than the third number Q1. That is,
0 <Q2 <Q1 ≦ L Expression 7
It is.

  For example, when L = 2, from Equation 7, for example, Q1 = 2 and Q2 = 1. In this case, the charge control unit 13bj operates the two charge pumps 46-1 and 46-2 when the DLL circuit is far from the locked state and the charge control signal output from the determination circuit 13j is at the H level. When the DLL circuit is in the vicinity of the locked state and the charge control current output from the determination circuit 13j becomes L level, the charge pump 46-2 is turned off and one charge pump 46-1 is operated.

  This configuration has an advantage that the diffusion capacitance parasitic on the source electrodes of the pMOS switch 31 and the nMOS switch 32 used near the locked state is small.

  In the first to third embodiments, the determination circuit 13 may have the configuration shown in FIGS. 9 (a) to 9 (d). FIG. 9 is a diagram showing another internal configuration example of the determination circuit 13 in the first to third embodiments of the present invention.

  9A is the same as the configuration of FIG. 3 in that the determination circuit 13 includes a rising edge detection type D flip-flop 41 of the CK terminal, but a signal input to the D terminal and the CK terminal. Are different. The reference clock CK0 is input to the D terminal, and the delay clock CK-K is input to the CK terminal. The charge control signal CR is output from the Q terminal to the charge control node NI. The delay clock CK-K and the reference clock CK0 input to the determination circuit 13 have a pulse rising phase difference in the locked state larger than a half cycle when the positive duty ratio in the reference clock CK0 is 0.5, for example. The relationship of less than one cycle is satisfied. Further, the delay clock input to the determination circuit 13 satisfies the relationship that if the positive duty ratio in the reference clock CK0 is 0.3, it is greater than 0.7 (= 1-0.3) period and smaller than 1 period. It is better to use a delay clock like this. For example, it is preferable to use the delayed clocks CK-22 to CK-31 when N = 32.

  9B is the same as the configuration of FIG. 3 in that the determination circuit 13 is composed of a D flip-flop 41 of the rising edge detection type of the CK terminal, but a signal input to the D terminal and the CK terminal. Are different. The delayed clock CK-K is input to the D terminal, and the delayed clock CK-N is input to the CK terminal. The charge control signal CR is output from the Q terminal to the charge control node NI. The delay clock CK-K and the delay clock CK-N input to the determination circuit 13 are different in the rising phase difference of the pulses in the locked state when the positive duty ratio in the reference clock CK0 is 0.5, for example. The relationship of larger and smaller than one cycle is satisfied.

  In FIG. 9C, the determination circuit 13 includes an AND gate 43 and a D latch 44. The reference clock CK0 having a positive duty ratio of 0.5 is used. The input of the AND gate 43 is input with the delay clock CK- (K-2) and the delay clock CK-K, and the output is connected to the D terminal of the D latch 44. The reference clock CK 0 is input to the CK terminal of the D latch 44. The charge control signal CR is output from the Q terminal to the charge control node NI. The positive duty ratio of the input pulse to the D terminal of the D latch 44 is reduced by passing through the AND gate 43. Among the clocks input to the determination circuit 13, at least two of the delayed clock CK-K and the reference clock CK0 satisfy the relationship that the rising phase difference of the pulses in the locked state is larger than a half cycle and smaller than one cycle. ing.

  In FIG. 9D, the determination circuit 13 is composed of a rising edge detection type JK flip-flop 45 of the CK terminal. The reference clock CK0 having a positive duty ratio of 0.5 is used. A delay clock CK-N is input to the J terminal, a delay clock CK-K is input to the CK terminal, and a reference clock CK0 is input to the K terminal. The charge control signal CR is output from the Q terminal to the charge control node NI. Among the clocks input to the determination circuit 13, at least two of the delayed clock CK-K and the reference clock CK0 satisfy the relationship that the rising phase difference of the pulses in the locked state is larger than a half cycle and smaller than one cycle. ing.

  In the above description, the determination circuit is described as the rising pulse synchronization type logic circuit, but instead, it may be configured as a falling synchronization type logic circuit.

  The VCDL 11 is an nMOS current source control type voltage control delay element, but the voltage control delay element of the present invention is not limited to this. For example, it may be a pMOS current source control type voltage control delay element, an nMOS-pMOS both current source control type voltage control delay element, or an input differential-output differential type voltage control. It may be a delay element.

1 is a diagram showing a configuration of a DLL circuit 1 according to a first embodiment of the present invention. The figure which shows each internal structure of N voltage control delay elements 12-1 to 12-N in 1st Embodiment of this invention. The figure which shows the internal structure of the determination circuit 13 in 1st Embodiment of this invention. The figure which shows each internal structure of the source current source 29 in the 1st Embodiment of this invention, the additional source current source 33, the sink current source 30, and the additional sink current source 34. 3 is a timing chart showing the operation of the DLL circuit 1 according to the first embodiment of the present invention. The figure which shows the simulation result of the time change of the delay control voltage VC in the DLL circuit 1 which concerns on 1st Embodiment of this invention. The figure which shows the structure of the charge pump 22i in 2nd Embodiment of this invention. The figure which shows the structure of the DLL circuit 1j which concerns on 3rd Embodiment of this invention. The figure which shows the other internal structural example of the determination circuit 13 in the 1st-3rd embodiment of this invention.

Explanation of symbols

1, 1i, 1j DLL circuit

Claims (6)

A first number of voltage controlled delay elements connected in series, and having a first delay amount with respect to the reference clock by delaying the reference clock by the first number of voltage controlled delay elements; 1 delay clock is generated and output, and the reference clock is delayed by a second number of voltage controlled delay elements that are part of the first number of voltage controlled delay elements. A delay unit for generating a second delay clock having a second delay amount smaller than the first delay amount;
A phase comparator that compares the phase of the reference clock with the phase of the first delay clock and outputs a rising signal or a falling signal according to the comparison result;
A charge pump that outputs a delay control current in response to the rising signal or the falling signal;
A delay control voltage is generated according to the delay control current, and the generated delay control voltage is supplied to each of the first number of voltage control delay elements, whereby the first delay with respect to the reference clock. A delay control unit that controls the first delay amount so that clocks are synchronized;
A determination unit that determines whether or not a phase difference between the reference clock and the first delay clock is equal to or less than a threshold value by comparing the phase of the reference clock and the phase of the second delay clock;
When the determination unit determines that the phase difference is greater than the threshold value, the delay control current is a first value, and when the determination unit determines that the phase difference is equal to or less than the threshold value, A charge control unit for controlling the charge pump so that a delay control current becomes a second value smaller than the first value;
A clock generation circuit comprising: The difference between the phase of the reference clock and the phase of the second delay clock is determined when the duty ratio of the reference clock is r when the first delay clock is synchronized with the reference clock. 2. The clock generation circuit according to claim 1, wherein the clock generation circuit is larger than (1-r) times the period of the reference clock and smaller than the period of the reference clock. The determination unit determines that the phase difference is greater than the threshold when the level of the second delay clock is at the first logic level at a timing synchronized with the reference clock, and a timing synchronized with the reference clock. 3. The clock generation circuit according to claim 1, wherein when the level of the second delayed clock is at a second logic level, the phase difference is determined to be equal to or less than the threshold value. The determination unit and the charge control unit include a D flip-flop,
The determination unit includes portions corresponding to a D terminal and a CK terminal in the D flip-flop, receives the reference clock in one of the D terminal and the CK terminal, and receives the reference clock in the other of the D terminal and the CK terminal. 2 delay clocks,
The charge control unit includes a portion corresponding to a Q terminal or a QB terminal in the D flip-flop, and outputs a signal for controlling the charge pump from the Q terminal or the QB terminal. 3 clock generation circuit; The charge pump is
An output node;
A charging unit for flowing a charging current to the output node in response to the rising signal;
A discharge unit that draws a discharge current from the output node in response to the falling signal;
Including
When the determination unit determines that the phase difference is greater than the threshold value, the charge control unit causes the charging unit to discharge a first charging current or the discharging unit absorbs a first discharging current, When the determination unit determines that the phase difference is equal to or less than the threshold value, the charging unit starts to flow a second charging current smaller than the first charging current, or the discharging unit is more than the first discharging current. 5. The clock generation circuit according to claim 1, wherein the charging unit and the discharging unit are controlled so as to absorb a small second discharge current. 6. The clock generation circuit includes a plurality of the charge pumps,
When the determination unit determines that the phase difference is larger than the threshold, the charge control unit operates a third number of the charge pumps in the plurality of charge pumps, and the phase difference is equal to or less than the threshold. 6. The charge pump according to claim 1, wherein the number of the charge pumps is less than the third number of the plurality of charge pumps when the determination unit determines that the charge pump is determined to be 2. The clock generation circuit according to item 1.

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