JP2010154922A - Memory control device and game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory control device and a game machine that can efficiently use a ROM. <P>SOLUTION: The memory control device (701) is connected with multiple control CPUs and a communal ROM (702) that stores data utilized by the multiple control CPUs. The memory control device receives a chip selection signal and address information of the communal ROM to access from the control CPUs (CPUs 401). Next, the memory control device converts the received address information according to the control CPUs (CPUs 401) that have sent the chip select signal. Then, the memory control device accesses the communal ROM by the converted address information. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a memory control device and a gaming machine, and more particularly to a memory control device that allows a plurality of control CPUs to share a ROM and a gaming machine including the memory control device.

In recent years, pachinko machines, which are a type of gaming machine, perform a visual and auditory presentation of a lottery process and a lottery result using a liquid crystal display unit and a speaker. Increases expectations. Such a pachinko machine generally includes display control means for performing visual effects and audio control means for performing auditory effects. For example, in the gaming machine described in Patent Document 1, display control means for controlling the display of the liquid crystal display screen, lamp control means for controlling the electrical wrap, and various sound output controls. Voice control means is provided. In the gaming machine described in Patent Document 1, each control unit has a control CPU, ROM, and RAM. The ROM of the display control unit includes image data to be displayed on the liquid crystal screen, and the ROM of the audio control unit. Voice data is stored. Each control means performs visual and auditory effects using various data stored in such ROM.
JP 2004-254914 A

  As described above, in recent pachinko machines, visual effects and auditory effects are more complicated and sophisticated in order to increase the player's expectation. Along with this, image data for performing visual effects and audio data for performing auditory effects increase, and the ROM for storing these data has also increased in capacity. Therefore, there is a problem that the cost is greatly affected. In addition, since each control means has a ROM individually, the usage rate of the ROM in each control means is biased and inefficient.

  Therefore, an object of the present invention is to provide a memory control device capable of using a ROM more efficiently and a gaming machine including the same.

  The present invention employs the following configuration in order to solve the above problems. Note that the reference numerals in parentheses, supplementary explanations, and the like are examples of the correspondence with the embodiments described later in order to help understanding of the present invention, and do not limit the present invention.

  The first invention is a memory control device connected to a plurality of control CPUs (FIG. 4: CPU 201, CPU 301, etc.) and a shared ROM (FIG. 5: shared ROM 702) for storing data used by the plurality of control CPUs. (FIG. 5: bus controller 701). The memory control device receives a chip select signal from the control CPU (for example, CPU 401) and address information of the shared ROM to be accessed. Next, the memory control device converts the received address information in accordance with the control CPU (CPU 401) that transmitted the chip select signal. Then, the memory control device accesses the shared ROM using the converted address information.

  According to the first invention, the shared ROM can be shared by a plurality of control CPUs. As a result, the ROM can be used efficiently.

  In the second invention, when the memory control device receives a chip select signal from the control CPU (FIG. 5: CPU 401), the control CPU differs from the control CPU (FIG. 5: CPU 401) that has transmitted the chip select signal. A signal (FIG. 5: inhibition signal) for inhibiting access to the shared ROM may be transmitted to (FIG. 5: CPU 501).

  According to the second invention, simultaneous access from the plurality of control CPUs to the shared ROM can be suppressed.

  In the third invention, the memory control device is connected to a plurality of shared ROMs less than the number of the control CPUs, and the address information transmitted from the control CPU is transmitted to the control CPU that transmitted the chip select signal. Conversion based on the received address information, and access to a predetermined shared ROM among the plurality of shared ROMs may be performed using the converted address information.

  According to the third invention, a plurality of shared ROMs can be used by a plurality of control CPUs. As a result, the ROM can be used more efficiently.

  According to a fourth aspect of the present invention, a game comprising a main control CPU that controls a lottery in a game and a sub-control CPU that controls a game operation performed based on a control signal from the main control CPU as the plurality of control CPUs. A gaming machine provided with the memory control device.

  According to the fourth invention, it is possible to provide a gaming machine capable of sharing a ROM among a plurality of control CPUs. Thereby, ROM can be used efficiently and the cost reduction of a game machine can be implement | achieved.

  According to the present invention, it is possible to provide a memory control device capable of sharing a ROM among a plurality of control CPUs and using the ROM more efficiently, and a gaming machine including the memory control device.

(Description of gaming machine)
Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, a gaming machine according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a schematic front view showing an example of a gaming machine 1 according to an embodiment of the present invention.

  In FIG. 1, a gaming machine 1 is a pachinko gaming machine configured to pay out a winning ball when a gaming ball launched by an instruction operation by a player wins a prize, for example. This gaming machine 1 includes a game board 2 on which game balls are launched, and a frame member 5 surrounding the game board 2.

  A game area 20 for playing a game with a game ball is formed on the front surface of the game board 2. In the game area 20, a rail member that forms a passage where a game ball launched from a launching device 211 (see FIG. 4) described later rises along the main surface of the game board 2 and goes to the upper position of the game area 20 ( (Not shown) and a guide member (not shown) for guiding the raised game ball to the right side of the game area 20.

  In addition, the game board 2 is provided with an image display unit 21 that displays images for various effects at positions that are easily visible to the player. The image display unit 21 notifies the player of the symbol lottery result (symbol variation result) by displaying, for example, a decorative symbol according to the progress of the game by the player, or notices by the appearance of a character or the appearance of an item. Display the production. The image display unit 21 is described as a liquid crystal display device, an EL (Electro Luminescence) display device, an LED (Light Emitting Diode) dot display device, and a 7-segment display (hereinafter referred to as a 7-segment display device). However, any other display device may be used. Further, a movable accessory 22 and a board lamp 23 used for various effects are provided on the front surface of the game board 2. The movable accessory 22 is configured to be movable with respect to the game board 2 and performs various effects by moving it with a predetermined operation in accordance with the progress of the game by the player. The board lamp 23 emits light according to the progress of the game by the player, thereby performing various effects by light.

  The game area 20 is provided with a game nail and a windmill (both not shown) that change the direction in which the game ball falls downward. Further, in the game area 20, various bonuses related to winning and lottery are arranged at predetermined positions. In FIG. 1, a start opening 25, a gate 27, a large winning opening 28, and a normal winning opening 29 are arranged on the game board 2 as examples of various prizes related to winning and lottery. Further, the game area 20 is provided with a discharge port 24 for discharging out of the game area 20 a game ball that has not been won in the winning area among the game balls launched into the game area 20.

  The start opening 25 wins when a game ball enters, and a special symbol lottery (a jackpot lottery) is started. The starting opening 25 operates a predetermined special electric accessory (big winning opening 28) and / or a predetermined special symbol display (for example, a special symbol display 31 described later). It is a winning mouth related to the winning. When the game ball passes through the gate 27, a normal symbol lottery (open / close lottery) is started.

  The start port 25 includes an electric tulip 26 in the vicinity of the entrance of the game ball as an example of a normal electric accessory. The electric tulip 26 has a pair of wings imitating tulip flowers, and the pair of wings opens and closes left and right by driving an electric tulip opening / closing unit 112 (for example, an electric solenoid), which will be described later. Lights up or blinks together. When the pair of blade portions of the electric tulip 26 are closed, the opening width guided to the entrance of the start port 25 is relatively narrow, so that the game ball is difficult to enter the start port 25. On the other hand, the electric tulip 26 is configured so that the game ball can easily enter the starting port 25 because the opening width guided to the inlet of the starting port 25 increases when the pair of blade portions opens left and right. When the electric tulip 26 wins the normal symbol lottery by passing the game ball through the gate 27, the pair of blade portions open for a specified time (for example, 6 seconds) while lighting or flashing, and the specified number of times (for example, 3) Open and close).

  The special winning opening 28 is located below the start opening 25 and is opened according to the result of the special symbol lottery. The special winning opening 28 is normally in a closed state so that no game balls can enter, but depending on the result of the special symbol lottery, it protrudes from the main surface of the game board 2 and is in an open state. The game ball is easy to enter. For example, the grand prize winning opening 28 is a predetermined number of rounds (for example, 30 seconds have elapsed or the game is open until the game ball is won or the accumulated cumulative time of 10 gaming balls is within 1.8 seconds). , 15 times or 2 times). Further, the lottery does not start at the normal winning opening 29 even if a game ball wins.

  In addition, a display 3 is provided at a predetermined position (for example, lower right) of the game board 2 to display the result of the above-described special symbol lottery or normal symbol lottery and the number of holds. FIG. 2 is an explanatory diagram showing an example of the display 3 disposed in the gaming machine 1. As shown in FIG. 2, the display 3 includes a special symbol display 31, a special symbol hold display 32, a normal symbol display 33, a normal symbol hold display 34, and a game state display 35.

  The special symbol display 31 displays the lottery result when the display symbol fluctuates in response to the winning of the game ball at the start opening 25. The normal symbol display 33 changes the display symbol corresponding to the game ball passing through the gate 27 and displays the lottery result. The special symbol hold indicator 32 displays the number of times the special symbol lottery is held. The normal symbol hold display 34 displays the number of times the normal symbol lottery is held. The game status indicator 35 displays the game status at the time when the gaming machine 1 is powered on. A plurality of gaming states (for example, a normal gaming state, a probability variation gaming state, a time-saving gaming state, and a latent gaming state) are set in the gaming machine 1.

  Returning to FIG. 1, a handle 51, a lever 52, a stop button 53, a speaker 55, a frame lamp 56, an effect button 57, an effect key 58 and the like are provided on the frame member 5 which is the front surface of the gaming machine 1.

  When the player touches the handle 51 and performs an operation to rotate the lever 52 in the clockwise direction, the launching device 211 (at 100 hits per minute) with a hitting force corresponding to the operation angle (for example, 100 per minute). FIG. 5) electrically fires a game ball.

  The stop button 53 is provided on the lower side surface of the handle 51, and even when the player touches the handle 51 and rotates the lever 52 in the clockwise direction, the game ball is released by being pressed by the player. Is temporarily stopped.

  The speaker 55 and the frame lamp 56 respectively notify the gaming state and situation of the gaming machine 1 and perform various effects. The speaker 55 performs various effects using music, voice, and sound effects. Further, the frame lamp 56 performs various effects by light depending on a pattern by lighting / flashing, a difference in emission color, or the like. Note that the frame lamp 56 may change the light irradiation direction and produce an effect by changing the irradiation direction.

  FIG. 3 is a partial plan view showing an effect button 57 and an effect key 58 for accepting an operation from the player. The effect button 57 and the effect key 58 are provided for the player to input the effect. The production key 58 includes a center key and a plurality of keys arranged in a substantially cross shape. The effect button 57 and the effect key 58 are each pressed by the player to perform a predetermined effect. For example, the player can select any of a plurality of images displayed on the image display unit 21 by operating four surrounding keys and a center key of the effect key 58.

  Next, with reference to FIG. 4, a control device that performs operation control and signal processing in the gaming machine 1 will be described. FIG. 4 is a block diagram illustrating an example of a configuration of a control device provided in the gaming machine 1.

  As shown in FIG. 4, the control device of the gaming machine 1 includes a main control unit 100, a launch control unit 200, a payout control unit 300, an effect control unit 400, an image sound control unit 500, and a lamp control unit 600. Yes.

  The main control unit 100 includes a CPU (Central Processing Unit) 101, a ROM (Read Only Memory) 102, and a RAM (Random Access Memory) 103. The CPU 101 performs arithmetic processing when performing various controls related to the number of payout prize balls, such as internal lottery and determination of winning. The ROM 102 stores programs executed by the CPU 101, various data, and the like, and the RAM 103 is used as a work memory for the CPU 101. Hereinafter, main functions of the main control unit 100 will be described.

  The main control unit 100 performs a special symbol lottery when a game ball wins the start opening 25, and sends determination result data indicating whether or not the special symbol lottery is won to the effect control unit 400. In addition, the main control unit 100 includes data indicating a variation setting of the winning probability determined according to the special symbol lottery (for example, a variation setting from 1/300 to 1/30) and a special symbol variation time reduction setting, Data indicating the setting for shortening the normal symbol variation time determined according to the normal symbol lottery is sent to the effect control unit 400. Although not described in detail, the main control unit 100 controls the opening / closing of the electric tulip 26, the opening / closing control of the big winning opening 28 according to the result of the special symbol lottery, the place where the game ball has won (the starting opening 25, the big winning prize). An instruction to the payout control unit 300 according to the mouth 28 and the normal winning opening 29), the control of the launch control unit 200 regarding the launch of the game ball, and the like are performed.

  In order to realize the above-described functions, the main control unit 100 includes a start port switch 111, an electric tulip opening / closing unit 112, a gate switch 113, a big winning port switch 114, a big winning port opening / closing unit 115, a normal winning port switch 116, A special symbol display 31, a special symbol hold indicator 32, a normal symbol indicator 33, and a normal symbol hold indicator 34 are connected.

  The start port switch 111 detects that a game ball has won the start port 25 and sends a detection signal to the main control unit 100. The electric tulip opening / closing unit 112 opens and closes the pair of blade portions of the electric tulip 26 in response to a control signal sent from the main control unit 100. The gate switch 113 detects that the game ball has passed through the gate 27 and sends a detection signal to the main control unit 100. The big prize opening switch 114 detects that a game ball has won the big prize opening 28 and sends a detection signal to the main control unit 100. The special prize opening / closing unit 115 opens and closes the special prize opening 28 in response to a control signal sent from the main control unit 100. The normal winning port switch 116 detects that a game ball has won the normal winning port 29 and sends a detection signal to the main control unit 100.

  The main control unit 100 also displays on the special symbol display 31 the result of the special symbol lottery started by winning the game ball in the starting port 25. The main control unit 100 displays on the special symbol hold indicator 32 the number of times the lottery is put on hold in accordance with the winning of the game ball to the start opening 25. The main control unit 100 displays the result of the normal symbol lottery started by passing the game ball to the gate 27 on the normal symbol display 33. Then, the main control unit 100 displays the number of holdings on which the lottery is put on hold according to the passing of the game ball to the gate 27 on the normal symbol holding display 34.

  The launch control unit 200 includes a CPU 201, a ROM 202, and a RAM 203. The CPU 201 performs arithmetic processing when performing various controls related to the launching device 211. The ROM 202 stores programs executed by the CPU 201 and various data, and the RAM 203 is used as a work memory for the CPU 201.

  When the position of the lever 52 is in the neutral position, the lever 52 is in a firing stop state without outputting a signal. When the lever 52 is rotated in the clockwise direction, the lever 52 outputs a signal corresponding to the rotation angle to the launch control unit 200 as a hitting ball firing command signal. The launch control unit 200 controls the launch operation of the launch device 211 based on the hit ball launch command signal.

  The payout control unit 300 includes a CPU 301, a ROM 302, and a RAM 303. The CPU 301 performs a calculation process when controlling the payout of the payout ball. The ROM 302 stores programs executed by the CPU 301, various data, and the like, and the RAM 303 is used as a working memory for the CPU 301 and the like. Then, the payout control unit 300 controls payout of the payout ball based on the command sent from the main control unit 100.

  Specifically, the payout control unit 300 acquires from the main control unit 100 a command for paying out a predetermined number of prize balls according to the place where the game ball has won. Then, the payout driving unit 311 is controlled so as to pay out the number of prize balls specified by the command. Here, the payout drive unit 311 is configured by a drive motor or the like that sends out a game ball from a game ball storage unit (ball tank).

  The effect control unit 400 includes a CPU 401, a ROM 402, a RAM 403, and an RTC (real time clock) 404. The CPU 401 performs a calculation process when controlling the effect. The ROM 402 stores programs executed by the CPU 401, various data, and the like, and the RAM 403 is used as a working memory for the CPU 401. The RTC 404 measures the current date and time. Although details will be described later, the ROM 402 is physically realized by using a partial area of one shared ROM 702 (see FIG. 5) shared with the ROM 502 of the image sound control unit 500.

  The production control unit 400 sets production contents based on data indicating the special symbol lottery result and the like sent from the main control unit 100. At that time, when the player presses the effect button 57 or the effect key 58, the effect control unit 400 may set the effect content according to the operation input. In addition, when the game for the gaming machine 1 is interrupted for a predetermined period or longer, the effect control unit 400 sets an effect for waiting for a customer as one of the effects. Furthermore, when the main control unit 100 outputs data indicating that the winning probability at the time of the special symbol lottery is changed, or when outputting data indicating that the special symbol change time at the time of the special symbol lottery is shortened, When the data indicating that the normal symbol variation time at the time of the normal symbol lottery is shortened is output, the effect control unit 400 sets the effect contents corresponding to the contents indicated by the output data. Then, the effect control unit 400 sends commands for instructing execution of the set effect contents to the image sound control unit 500 and the lamp control unit 600, respectively.

  The image sound control unit 500 includes a CPU 501, a ROM 502, and a RAM 503. The CPU 501 performs arithmetic processing when controlling the image and sound expressing the content of the effect. The ROM 502 stores programs executed by the CPU 501 and various data, and the RAM 503 is used as a working memory for the CPU 501. Although details will be described later, the ROM 502 is physically realized by using a partial area of one shared ROM 702 (see FIG. 5), similarly to the ROM 402.

  The image sound control unit 500 controls the image displayed on the image display unit 21 and the sound output from the speaker 55 based on the command sent from the effect control unit 400. Specifically, in the ROM 502 of the image sound control unit 500, a symbol image or background image displayed during the game on the image display unit 21, a decorative symbol for notifying the player of the lottery result, and a notice effect for the player. Image data such as characters and items to be displayed is stored. Further, the ROM 502 of the image sound control unit 500 synchronizes with the image displayed on the image display unit 21 or independently of the displayed image, such as music and sound output from the speaker 55, and further, a jingle or the like. Various acoustic data such as sound effects are stored. The CPU 501 of the image sound control unit 500 selects and reads out the data corresponding to the command sent from the effect control unit 400 from the image data and sound data stored in the ROM 502. The CPU 501 performs image processing for background image display, symbol image display, symbol image variation, character / item display, and the like using the read image data. Further, the CPU 501 performs voice processing using the read acoustic data. Then, the CPU 501 displays the image indicated by the image processed image data on the image display unit 21. Further, the CPU 501 outputs the sound indicated by the sound data subjected to the sound processing from the speaker 55.

  The lamp control unit 600 includes a CPU 601, a ROM 602, and a RAM 603. The CPU 601 performs arithmetic processing when controlling the light emission of the panel lamp 23 and the frame lamp 56 and the operation of the movable accessory 22. The ROM 602 stores programs executed by the CPU 601 and various data, and the RAM 603 is used as a working memory for the CPU 601.

  The lamp control unit 600 controls the lighting / flashing of the panel lamp 23 and the frame lamp 56, the emission color, and the like based on the command sent from the effect control unit 400. In addition, the lamp control unit 600 controls the operation of the movable accessory 22 based on the command sent from the effect control unit 400.

(Explanation about ROM sharing)
Next, with reference to FIG. 5, the ROM used by each control device in the gaming machine 1 will be described. FIG. 5 is an explanatory diagram for explaining a shared ROM accessed by a plurality of control CPUs. FIG. 5 shows a state where the ROM 402 of the effect control unit 400 and the ROM 502 of the image sound control unit 500 in FIG. 4 are shared by one shared ROM 702 as an example of the shared ROM.

  The bus controller 701 performs access control to the shared ROM 702 by performing predetermined processing. The bus controller 701 is realized by a single integrated circuit, for example. The bus controller 701 changes the address designation to the shared ROM 702 according to the CPU that has requested access to the shared ROM 702. Detailed processing of the bus controller 701 will be described later.

  The shared ROM 702 is a read-only memory for storing various data. For example, an EEPROM is used. The shared ROM 702 has a capacity of 128 MB, for example. The shared ROM 702 is shared by the CPU 401 of the effect control unit 400 and the CPU 501 of the image sound control unit 500 via the bus controller 701.

  As shown in FIG. 5, the CPU 401 of the effect control unit 400 and the CPU 501 of the image sound control unit 500 are connected to the bus controller 701 by a data bus 703 and an address bus 704. Although not explicitly shown in FIG. 5, the bus controller 701 is connected to the shared ROM 702 by a data bus 703 and an address bus 704. The CPU 401 is connected to the bus controller 701 by a CS (Chip Select) signal line 71. Similarly, the CPU 501 is connected to the bus controller 701 by a CS signal line 72. Further, the bus controller 701 is connected to the shared ROM 702 via the CS signal line 70. The data bus 703 and the address bus 704 are actually composed of a plurality of conductive wires.

  Further, the CPU 401 of the effect control unit 400 and the bus controller 701 are connected by a read signal line (READ) 81. Similarly, the CPU 501 of the image sound control unit 500 and the bus controller 701 are connected by a read signal line (READ) 82. Further, the bus controller 701 and the shared ROM 702 are connected by a read signal line (READ) 80.

  The bus controller 701 and the shared ROM 702 are arranged on the same substrate, for example. For example, the bus controller 701 and the shared ROM 702 may be arranged on the same base as the effect control unit 400. The image sound control unit 500 may be mounted on a base different from the effect control unit 400 or may be mounted on the same base.

  Next, the detailed operation of the bus controller 701 will be described. The bus controller 701 determines the address range of the shared ROM 702 in advance so as to be different for each CPU that has transmitted the chip select signal. For example, the bus controller 701 uses the shared ROM 702 address range 000000-3FFFFFF (hexadecimal notation; 64 MB in capacity; hereinafter referred to as a production control area) for the CPU 401, and the shared ROM 702 address range 400000-7FFFFFF (capacity) for the CPU 501. 64 MB, hereinafter referred to as an image sound area).

  The effect control area of the shared ROM 702 is the ROM 402 of the effect control unit 400 described above, and stores programs executed by the CPU 401, various data, and the like. The image sound area of the shared ROM 702 is the ROM 502 of the image sound control unit 500 described above, and stores programs executed by the CPU 501 and various data (image data and sound data).

  When the CPU 401 of the effect control unit 400 designates an address and obtains data stored in the shared ROM 702, the CPU 401 designates an address at which data to be obtained via the address bus 704 is stored, and a CS signal line A chip select signal is transmitted to the bus controller 701 via a read signal line 81 and a chip select signal is transmitted to the bus controller 701, respectively. Specifically, the CPU 401 deactivates the CS signal line 71 (LOW level) and deactivates the read signal line 81 (LOW level). The bus controller 701 receives a chip select signal and a read signal transmitted from the CPU 401.

  The bus controller 701 receives address information designated by the CPU 401 via the address bus 704. The bus controller 701 updates the address information based on the received address information and the address range previously assigned to the CPU 401. Specifically, the bus controller 701 updates the address information by adding the smallest address in the address range assigned to the CPU 401 to the address designated by the CPU 401. For example, when the address designated by the CPU 401 is the address 0000100, the bus controller 701 updates a value 0000100 obtained by adding 0000100 to 0000100 as a new address (in this case, the same address is obtained as a result). The bus controller 701 specifies the updated address to access the shared ROM 702, and transmits a chip select signal and a read signal via the CS signal line 70 and the read signal line 80, respectively. As a result, the bus controller 701 acquires data stored in the address 0000100 of the shared ROM 702 via the data bus 703 and transmits the acquired data to the CPU 401. In this way, the CPU 401 can access the effect control area of the shared ROM 702.

  Similarly, when the CPU 501 of the image sound control unit 500 designates an address and acquires data stored in the shared ROM 702, the CPU 501 designates an address where data to be obtained is stored via the address bus 704. The chip select signal is transmitted to the bus controller 701 via the CS signal line 72, and the read signal is transmitted via the read signal line 82, respectively. The bus controller 701 that has received the chip select signal and the address information updates the address information by adding the smallest address in the address range assigned to the CPU 501 to the received address. Specifically, when the address specified by the CPU 501 is the address 000100, the bus controller 701 updates the value 4000100 obtained by adding 4000000 to 000100 as a new address. Then, the bus controller 701 specifies the updated address 4000100 to access the shared ROM 702, and transmits a chip select signal and a read signal. Thereby, the bus controller 701 acquires the data stored in the address 4000100 of the shared ROM 702 via the data bus 703 and transmits the acquired data to the CPU 501. In this way, the CPU 501 can access the image sound area of the shared ROM 702.

  For example, when the CPU 401 tries to access data in the area of the CPU 501 (the image sound area of the shared ROM 702), the bus controller 701 does not access the image sound area. In this way, the bus controller 701 performs exclusive control, whereby each control CPU can access different areas of the shared ROM 702.

  On the other hand, when the bus controller 701 receives a chip select signal from the CPU 401 or the CPU 501, it sends a signal (suppression signal) for suppressing access to the shared ROM 702 to a CPU different from the CPU that transmitted the chip select signal. Send. For example, when the bus controller 701 receives a chip select signal from the CPU 401, the bus controller 701 notifies the CPU 501 that the CPU 401 has accessed the shared ROM 702. The CPU 501 that has received this notification does not access the shared ROM 702. This notification can be realized, for example, when the bus controller 701 transmits an interrupt request to the CPU 401. For example, the CPU 401 that has received the interrupt request transmits an access request to the shared ROM 702 to the bus controller 701 after a predetermined time has elapsed. Alternatively, the CPU 401 that has received the interrupt request transmits an access request to the shared ROM 702 to the bus controller 701 when receiving the interrupt request again from the bus controller 701. In this way, simultaneous access from the two CPUs to the shared ROM can be suppressed.

  As described above, the CPU 401 and the CPU 501 can access the areas of the shared ROM 702 assigned to them. That is, the CPU 401 and the CPU 501 can share and use the shared ROM 702 via the bus controller 701. Thus, by sharing one ROM among a plurality of control CPUs, the number of parts can be reduced and the cost can be reduced as compared with the case where the control CPU and the ROM are connected one-to-one. .

  In the above description, the shared ROM 702 is shared by the CPU 401 of the effect control unit 400 and the CPU 501 of the image sound control unit 500. However, other combinations, for example, the CPU 101 of the main control unit 100 and the CPU 401 of the effect control unit 400 share. The ROM may be shared. Two or more CPUs may use the shared ROM. In this case, it is preferable to share the ROM between CPUs considered to have little simultaneous access to the shared ROM.

  In the above description, the case where one shared ROM is used by a plurality of CPUs has been described. However, a plurality of shared ROMs may be used by a plurality of CPUs. For example, two shared ROMs may be used by three CPUs. FIG. 6 is a diagram illustrating a state in which two shared ROMs are used by three control CPUs. When two shared ROMs are used by three CPUs, for example, address information is converted as follows. That is, as shown in FIG. 6, the bus controller 701 allocates 2/3 capacity (128 MB) of the first shared ROM (capacity 192 MB) to the first CPU, and supplies it to the second CPU. Thus, the remaining 1/3 (64 MB) of the first shared ROM and 1/3 (64 MB) of the second shared ROM (capacity 192 MB) are allocated. The bus controller 701 allocates the remaining 2/3 (128 MB) of the second shared ROM to the third CPU.

  When there is an access request from the first CPU to a predetermined address for the ROM, the bus controller 701 accesses the address of the first shared ROM. Further, when the second CPU accesses the 20th MB address of the ROM, the bus controller 701 designates the 84th MB address of the first shared ROM and acquires data from the first shared ROM. To do. On the other hand, when the second CPU accesses the 90th MB address to the ROM, the bus controller 701 specifies the 26th MB address of the second shared ROM and acquires data from the first shared ROM. To do. The address (26 MB) in the second shared ROM is obtained by the difference between the designated address (90 MB) and the capacity of the first shared ROM allocated to the second CPU (64 MB). In this way, by controlling the ROM accessed by the bus controller and its address, a plurality of shared ROMs can be used by a plurality of CPUs.

  Furthermore, in this embodiment, an example in which a single shared ROM is accessed from a plurality of CPUs has been shown. However, in another embodiment, a single CPU is accessed to a plurality of ROMs via a bus controller. Also good. That is, in this case, the bus controller changes the ROM to be accessed according to the address information from the CPU.

  In addition, the present invention can be used not only in gaming machines but also in other information processing apparatuses. For example, the present invention can be used for personal computers, game machines, and the like.

Schematic front view showing an example of a gaming machine 1 according to an embodiment of the present invention Explanatory drawing which shows an example of the indicator 3 arrange | positioned at the gaming machine 1 Partial plan view showing a production button 57 and a production key 58 for accepting an operation from the player The block diagram which shows an example of a structure of the control apparatus provided in the gaming machine 1 Explanatory diagram for explaining a shared ROM accessed by a plurality of control CPUs The figure which showed a mode that two shared ROMs were utilized by three control CPUs

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Game machine 2 Game board 3 Display 5 Frame member 20 Game area 21 Image display part 22 Movable accessory 23 Board lamp 24 Discharge port 25 Start-up port 26 Electric tulip 27 Gate 28 Big winning port 29 Normal winning port 31 Special symbol display 31 32 Special symbol hold indicator 33 Normal symbol indicator 34 Normal symbol hold indicator 35 Game status indicator 51 Handle 52 Lever 53 Stop button 55 Speaker 56 Frame lamp 57 Effect button 58 Effect key 100 Main control unit 101, 201, 301, 401, 501, 601 CPU
102, 202, 302, 402, 502, 602 ROM
103, 203, 303, 403, 503, 603 RAM
111 Start Switch 112 Electric Tulip Opening / Closing Unit 113 Gate Switch 114 Grand Prize Opening Port Switch 115 Large Winning Port Opening / Closing Unit 116 Normal Winning Port Switch 200 Launch Control Unit 211 Launching Device 300 Delivery Control Unit 311 Delivery Drive Unit 400 Production Control Unit 500 Image Sound Control unit 600 Lamp control unit 70, 71, 72 CS signal line 701 Bus controller 702 Shared ROM
703 Data bus 704 Address bus 80, 81, 82 Read signal line

Claims (4)

A memory control device connected to a plurality of control CPUs and a shared ROM for storing data used by the plurality of control CPUs,
The chip select signal from the control CPU and the address information of the shared ROM to be accessed are received, the received address information is converted according to the control CPU that transmitted the chip select signal, and the converted address information is used as the address information. A memory control device that accesses a shared ROM.   When a chip select signal is received from the control CPU, a signal for inhibiting access to the shared ROM is transmitted to the control CPU different from the control CPU that has transmitted the chip select signal. The memory control device according to claim 1.   The address information transmitted from the control CPU is connected to a plurality of shared ROMs smaller than the number of the control CPUs, and is converted based on the control CPU that transmitted the chip select signal and the transmitted address information. 2. The memory control device according to claim 1, wherein access to a predetermined shared ROM among the plurality of shared ROMs is performed by using the address information. A gaming machine comprising, as the plurality of control CPUs, a main control CPU that controls a lottery in a game and a sub control CPU that controls a game operation performed based on a control signal from the main control CPU,
A gaming machine comprising the memory control device according to any one of claims 1 to 3.

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