JP2010153627A - Production method for backside irradiation version solid-state image pickup device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a production method for producing a proper product with comparatively simple processes for a backside irradiation version solid-state image pickup device. <P>SOLUTION: A method for producing a backside irradiation version solid-state image pickup device includes a bonding process for bonding a second silicon wafer of the support side on the front surface side of a first silicon wafer where a photo diode and a multilayered wiring layer are formed (S20); a thin film process for thinning the first silicon wafer to a target thickness from the backside (S30-S80) after the bonding process (S20); and a dry chemical planarization (DCP) process for applying DCP processing to the backside of the first silicon wafer for performing planarization using partial plasma etching (S70) in the thin film process (S30-S80). <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a back-illuminated solid-state imaging device.

Conventionally, as shown in FIG. 3, the back-illuminated solid-state imaging device is a first silicon wafer 11 having a two-layer epi (p ₋ / p ₊ / substrate) structure as a silicon substrate for forming a photodiode and a multilayer wiring layer. After forming the multilayer wiring layer 11w on the p ₋ layer 11a next to the photodiode (step A10), the p _- layer 11a is bonded to the second silicon wafer 12 on the support side (step A20), and an etch stop method is used. Then, the substrate 11c of the first silicon wafer 11 is etched or polished (step A30), and then the p ₊ layer 11b of the first silicon wafer 11 is removed (step A40), and a light receiving portion (color filter or lens) is formed on the photodiode. The device layer 11d for forming the layer) is manufactured (step A50).

Note that the etch stop method utilizes the characteristic that the etching rate differs depending on the dopant concentration, and the p ₊ layer 11b of the first silicon wafer 11 is a stop layer used for the etch stop method, and the second silicon wafer 12 Before bonding, oxygen is introduced into the surface layer of the first silicon wafer 11 by ion implantation or the like, and high-temperature heat treatment is performed, so that a silicon oxide film layer is formed in advance.

Here, for example, Patent Document 1 discloses a technique related to a back-illuminated solid-state imaging device, so please refer to it.
JP 2008-210846 A

However, in the above manufacturing method, the process involved in forming the p ₊ layer 11b serving as the stop layer is complicated, defects are introduced under high-temperature heat treatment during the formation of the p ₊ layer 11b, and in-plane non-uniformity of etching or polishing is involved. There are various problems such as the possibility of over-etching or over-polishing failure, and the need to control the transition layer to the device region due to the difference in dopant concentration.
The present invention has been devised in view of such problems, and an object of the present invention is to provide a method for manufacturing a back-illuminated solid-state image pickup device capable of obtaining a non-defective product through a relatively simple process.

  In order to achieve the above object, according to the first aspect of the present invention, there is provided a backside illumination type solid-state imaging device comprising: a second silicon on a support side on a surface side of a first silicon wafer on which a photodiode and a multilayer wiring layer are formed; A bonding step of bonding wafers; and a thinning step of thinning the first silicon wafer to a target thickness from the back surface side after the bonding step, and in the thinning step, the first silicon wafer A dry chemical flattening process for performing flattening by performing dry chemical flattening using local plasma etching on the back surface of the substrate is characterized.

  The method for manufacturing a backside illumination type solid-state imaging device according to the present invention described in claim 2 is the method for manufacturing a backside illumination type solid-state imaging device according to claim 1, wherein the second silicon wafer is provided before the bonding step. And a target thickness setting step of setting the sum of the acquired thickness in-plane distribution of the second silicon wafer and the remaining target thickness of the first silicon wafer as a final target thickness in-plane distribution. In addition, in the thinning process, immediately before the dry chemical planarization process, the thickness in-plane distribution of the entire first silicon wafer and the second silicon wafer immediately before the dry chemical planarization process is obtained, and the entire A dry chemical flattening allowance setting step for setting a dry chemical flattening allowance based on the difference between the thickness in-plane distribution and the final target thickness in-plane distribution. It is set to.

  According to the present invention, with respect to processing from the back surface side of the first silicon wafer on which the light receiving portion is formed on the front surface side, the processing allowance of the first silicon wafer is set in an appropriate process, and a reference surface (bonding interface) By using dry chemical planarization (DCP) processing that can correct unevenness on the surface, it can be processed to a desired thickness without an etch stopper (stop layer), and excellent in-plane film thickness uniformity The back-illuminated solid-state imaging device can be manufactured. That is, a good product can be obtained by a relatively simple process.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
1 and 2 are for explaining a method of manufacturing a backside illumination type solid-state imaging device according to an embodiment of the present invention. FIG. 1 is a flowchart of the manufacturing method, and FIG. It is a schematic diagram which shows the state of the image pick-up element. In FIG. 2, the dimensions of each layer of the image sensor are exaggerated for easy understanding of the invention, and hatches and dots are appropriately added to each layer so that each layer can be easily identified.

[Overview]
In this embodiment, as shown in FIG. 2, the back-illuminated solid-state imaging device (hereinafter also simply referred to as imaging device) is a device-side silicon wafer (first silicon wafer) on which a photodiode and a multilayer wiring layer 1w are formed. 1 and a support side silicon wafer (second silicon wafer) 2 to be a support substrate are bonded to each other, and as shown in FIG. 1, a target thickness setting step S10, a bonding step S20, , Thinning grinding step S30, thinning polishing step S40, thickness measurement step S50, DCP processing allowance setting step (dry chemical flattening allowance setting step) S60, and DCP processing step (dry chemical flattening step) S70 and surface roughness improvement polishing process S80 are manufactured through this order.

Each of the thinning grinding step S30 to the surface roughness improving polishing step S80 is one step of the thinning step. Further, the device-side silicon wafer 1 used here is different from the above-described conventional first silicon wafer 11 in that no stop layer is formed.
Each of the above steps will be described in detail below with reference to FIGS.

[1. Target thickness setting process]
In the target thickness setting step S10, before the support-side silicon wafer 2 is bonded to the device-side silicon wafer 1, a thickness (remaining target thickness) t ₁ to be left on the device-side silicon wafer 1 is set in advance and the support-side silicon wafer is set. get 2 of the thickness plane distribution t _2, by adding its device side residual target thickness t ₁ and the support within the thickness plane of side silicon wafer 2 distribution t ₂ of the silicon wafer 1, the final imaging element of the whole A thickness in-plane distribution (final target thickness in-plane distribution) t ₃ is calculated.

Final target thickness in-plane distribution t ₃ = device-side silicon wafer remaining target thickness t ₁
+ Thickness in-plane distribution t _{2 of} support side silicon wafer

[2. Bonding process]
In the bonding step S20, the support-side silicon wafer 2 is bonded to the surface of the device-side silicon wafer 1 (the surface on the side where the photodiode and the multilayer wiring layer 1w are formed). And in this bonding, the adhesion reinforcement | strengthening heat processing is performed in order to improve adhesiveness.

[3. Thin film grinding process]
In the thin film grinding step S30, the device-side silicon wafer 1 is ground from the back side. The grinding allowance is set to, for example, “average value of final target thickness in-plane distribution t ₃ +15 μm”. The 15 μm is a first predetermined value set in advance, and can be appropriately changed to other numerical values.

Here, the thickness variation of the thickness in-plane distribution t ₂ of the support-side silicon wafer 2 increases the DCP processing load required for correcting the unevenness. Although the grinding process is an in-plane batch process, it is preferable that the TTV (Total Thickness Value) amount after the grinding process is 1 μm or less. In addition, the amount of TTV unique to the grinding machine is scrutinized, and the machining allowance is set so as not to overgrind.

[4. Thin film polishing process]
In the thinning polishing step S40, the device-side silicon wafer 1 is polished from the back side. The processing allowance for this polishing is set to, for example, “average value of final target thickness in-plane distribution t ₃ +2 μm”. Note that 2 μm is a second predetermined value set in advance, and can be appropriately changed to other numerical values.

  Further, like the above-described grinding process, the polishing process is also an in-plane collective process, and it is preferable that the amount of TTV is 1 μm or less. In addition, the amount of TTV unique to the polishing machine is scrutinized, and the machining allowance is set so as not to be over-polished.

[5. Thickness measurement process]
In Thickness measurement step S50, the thickness on the entire imaging element distribution (thin thickness after plane distribution) after polishing to measure t _4.

[6. DCP machining allowance setting process]
In DCP machining allowance setting step S60, from the thickness measuring step S50 thinning thickness after plane distribution t ₄ when measured in the surface roughness improved polishing amount t ₅ to a final target thickness plane distribution t ₃ and later subtracted value , DCP machining allowance t _DCP is set.

DCP machining allowance t _DCP = thickness in-plane distribution after thinning t ₄
- final target thickness plane distribution t ₃ - the surface roughness improved polishing amount t ₅
The DCP machining allowance t _DCP is set at all measurement points, and the machining allowance t _DCP and measurement coordinates are converted into the DCP machining stage speed.

[7. DCP processing step]
In the DCP machining step S70, DCP (Dry using local plasma etching is applied to the back surface of the device-side silicon wafer 1 in accordance with the DCP machining margin (in-plane distribution data) of all measurement points set in the DCP machining margin setting step S60. Chemical Planarization (dry chemical flattening) is applied and flattened.

  DCP processing is a well-known method in which etching gas is turned into plasma by microwaves to generate ions and reactive radicals, and local plasma etching is performed using these radicals as main etchants. When the spray nozzle for spraying the etching gas is scanned with respect to the back surface of the device-side silicon wafer 1, the etching gas is sprayed from the spray nozzle while changing the speed of the stage (stage for chucking the imaging device) at each measurement point. Thus, local processing can be performed with high accuracy.

Here, the target thickness setting step S10 and the thickness measuring step S50, the thickness plane distribution t ₂ and the thin film within the thickness plane after reduction distribution t ₄ of the support side silicon wafer 2 is acquired over 25 points in a plane as a measuring point It is preferable. In addition, since it is possible to perform etching at intervals of 1 mm or more in DCP processing, it is more preferable to measure at an in-plane pitch of 1 to 3 mm.

[8. Surface roughness improvement polishing process]
Since DCP processing uses local plasma etching, the surface roughness is inferior to a normal polished surface. Therefore, in the surface roughness improving polishing step S80, polishing is performed to such an extent that the amount of TTV is not deteriorated (for example, about 0.1 μm), and the surface roughness is improved to the same level as a normal polished surface.

Specific examples and comparative examples will be described below.
[Example 1]
A device-side silicon wafer 1 having a multilayer wiring layer 1w of 200 mm, bonding the supporting side silicon wafer 2 which has acquired the thickness plane distribution t ₂ in advance 1mm pitch, performs adhesion enhancing treatment (target thickness setting step S10, bonding step S20), and thereafter processing from the back side of the device side silicon wafer 1 by grinding until “average value of final target thickness in-plane distribution t ₃ of the entire imaging device + about 15 μm” (thinning of the film) grinding step S30), followed by machining to a "mean value + about 2μm final target thickness plane distribution t ₃ of the whole image pickup device" in the polishing process (thinning polishing step S40).

After this polishing, the thickness in-plane distribution t ₄ of the entire image sensor is measured (thickness measurement step S50), and the difference from the final target thickness in-plane distribution t ₃ is obtained at each measurement point to set the DCP machining allowance t _DCP. (DCP processing allowance setting step S60), DCP processing and surface roughness improving polishing are performed (DCP processing step S70, surface roughness improving polishing step S80), and after the final structure, the device side from the bonding interface The thickness in-plane distribution of the silicon wafer 1 was measured. As a result, the variation in film thickness uniformity was ± about 0.10 μm, which was confirmed to be favorable.

[Example 2]
An imaging device is manufactured in the same flow as in the first embodiment except that the thickness in-plane distributions t ₂ and t ₄ are obtained by using 25 points in the plane as measurement points in each of the thickness measurement steps S10 and S50. The thickness in-plane distribution of the device side silicon wafer 1 from the bonded interface was measured. As a result, the variation in film thickness uniformity was ± 0.12 μm, which was confirmed to be favorable.

[Comparative Example 1]
In the same flow as in Example 1, the in-plane distribution of the thickness of the device-side silicon wafer 1 from the bonding interface was measured when grinding and mirror polishing were performed up to the target remaining film thickness using the bonding interface as a reference. As a result, the variation in film thickness uniformity was ± about 0.7 μm, and it was confirmed that the film thickness uniformity was inferior to that of Examples 1 and 2.

[effect]
Thus, according to the manufacturing method of the backside illumination type solid-state imaging device of the present invention, the device-side silicon wafer 1 is processed in an appropriate process with respect to processing from the backside of the device-side silicon wafer 1 that forms the light receiving portion on the front surface side. By using the DCP process that can correct the irregularities on the reference surface (bonding interface), it can be processed to the desired thickness without an etch stopper (stop layer). A back-illuminated solid-state imaging device with excellent film thickness uniformity can be manufactured. That is, a good product can be obtained by a relatively simple process.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

It is a flowchart which shows the manufacturing method of the back irradiation type solid-state image sensor which concerns on one Embodiment of this invention. It is a schematic diagram which shows the state of the image pick-up element which passed through each process of the manufacturing method of the backside illumination type solid-state image sensor which concerns on one Embodiment of this invention, or in each process. It is a schematic diagram explaining the manufacturing method of the conventional back irradiation type solid-state image sensor.

Explanation of symbols

1 Device side silicon wafer (first silicon wafer)
2 Support side silicon wafer (second silicon wafer)

Claims (2)

A bonding step of bonding the second silicon wafer on the support side to the surface side of the first silicon wafer on which the photodiode and the multilayer wiring layer are formed;
A thinning step of thinning the first silicon wafer from the back side to a target thickness after the bonding step;
In the thinning step, a back-illuminated solid comprising a dry chemical flattening step of performing a dry chemical flattening process using a local plasma etching on the back surface of the first silicon wafer. Manufacturing method of imaging device. Before the bonding step, the thickness in-plane distribution of the second silicon wafer is acquired, and the sum of the acquired thickness in-plane distribution of the second silicon wafer and the remaining target thickness of the first silicon wafer is the final target. While providing a target thickness setting step to set as a thickness in-plane distribution,
In the thinning step, immediately before the dry chemical planarization step, the in-plane thickness distribution of the entire first silicon wafer and the second silicon wafer immediately before the dry chemical planarization step is obtained, and the total thickness is obtained. 2. The backside irradiation according to claim 1, further comprising a dry chemical planarization allowance setting step for setting a dry chemical planarization allowance based on a difference between the in-plane distribution and the final target thickness in-plane distribution. Type solid-state imaging device manufacturing method.

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